target/linux/generic/patches-3.6/065-8139cp-fixes.patch

   1 commit 01ffc0a7f1c1801a2354719dedbc32aff45b987d
   2 Author: David Woodhouse <dwmw2@infradead.org>
   3 Date:   Sat Nov 24 12:11:21 2012 +0000
   4
   5     8139cp: re-enable interrupts after tx timeout
   6
   7     Recovery doesn't work too well if we leave interrupts disabled...
   8
   9     Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
  10     Acked-by: Francois Romieu <romieu@fr.zoreil.com>
  11     Signed-off-by: David S. Miller <davem@davemloft.net>
  12
  13 commit 871f0d4c153e1258d4becf306eca6761bf38b629
  14 Author: David Woodhouse <dwmw2@infradead.org>
  15 Date:   Thu Nov 22 03:16:58 2012 +0000
  16
  17     8139cp: enable bql
  18
  19     This adds support for byte queue limits on RTL8139C+
  20
  21     Tested on real hardware.
  22
  23     Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
  24     Acked-By: Dave Täht <dave.taht@bufferbloat.net>
  25     Signed-off-by: David S. Miller <davem@davemloft.net>
  26
  27 commit a9dbe40fc10cea2efe6e1ff9e03c62dd7579c5ba
  28 Author: David Woodhouse <dwmw2@infradead.org>
  29 Date:   Wed Nov 21 10:27:19 2012 +0000
  30
  31     8139cp: set ring address after enabling C+ mode
  32
  33     This fixes (for me) a regression introduced by commit b01af457 ("8139cp:
  34     set ring address before enabling receiver"). That commit configured the
  35     descriptor ring addresses earlier in the initialisation sequence, in
  36     order to avoid the possibility of triggering stray DMA before the
  37     correct address had been set up.
  38
  39     Unfortunately, it seems that the hardware will scribble garbage into the
  40     TxRingAddr registers when we enable "plus mode" Tx in the CpCmd
  41     register. Observed on a Traverse Geos router board.
  42
  43     To deal with this, while not reintroducing the problem which led to the
  44     original commit, we augment cp_start_hw() to write to the CpCmd register
  45     *first*, then set the descriptor ring addresses, and then finally to
  46     enable Rx and Tx in the original 8139 Cmd register. The datasheet
  47     actually indicates that we should enable Tx/Rx in the Cmd register
  48     *before* configuring the descriptor addresses, but that would appear to
  49     re-introduce the problem that the offending commit b01af457 was trying
  50     to solve. And this variant appears to work fine on real hardware.
  51
  52     Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
  53     Cc: stable@kernel.org [3.5+]
  54     Signed-off-by: David S. Miller <davem@davemloft.net>
  55
  56 diff --git a/drivers/net/ethernet/realtek/8139cp.c b/drivers/net/ethernet/realtek/8139cp.c
  57 index 1c81825..6cb96b4 100644
  58 --- a/drivers/net/ethernet/realtek/8139cp.c
  59 +++ b/drivers/net/ethernet/realtek/8139cp.c
  60 @@ -648,6 +648,7 @@ static void cp_tx (struct cp_private *cp)
  61  {
  62         unsigned tx_head = cp->tx_head;
  63         unsigned tx_tail = cp->tx_tail;
  64 +       unsigned bytes_compl = 0, pkts_compl = 0;
  65
  66         while (tx_tail != tx_head) {
  67                 struct cp_desc *txd = cp->tx_ring + tx_tail;
  68 @@ -666,6 +667,9 @@ static void cp_tx (struct cp_private *cp)
  69                                  le32_to_cpu(txd->opts1) & 0xffff,
  70                                  PCI_DMA_TODEVICE);
  71
  72 +               bytes_compl += skb->len;
  73 +               pkts_compl++;
  74 +
  75                 if (status & LastFrag) {
  76                         if (status & (TxError | TxFIFOUnder)) {
  77                                 netif_dbg(cp, tx_err, cp->dev,
  78 @@ -697,6 +701,7 @@ static void cp_tx (struct cp_private *cp)
  79
  80         cp->tx_tail = tx_tail;
  81
  82 +       netdev_completed_queue(cp->dev, pkts_compl, bytes_compl);
  83         if (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1))
  84                 netif_wake_queue(cp->dev);
  85  }
  86 @@ -843,6 +848,8 @@ static netdev_tx_t cp_start_xmit (struct sk_buff *skb,
  87                 wmb();
  88         }
  89         cp->tx_head = entry;
  90 +
  91 +       netdev_sent_queue(dev, skb->len);
  92         netif_dbg(cp, tx_queued, cp->dev, "tx queued, slot %d, skblen %d\n",
  93                   entry, skb->len);
  94         if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1))
  95 @@ -937,6 +944,8 @@ static void cp_stop_hw (struct cp_private *cp)
  96
  97         cp->rx_tail = 0;
  98         cp->tx_head = cp->tx_tail = 0;
  99 +
 100 +       netdev_reset_queue(cp->dev);
 101  }
 102
 103  static void cp_reset_hw (struct cp_private *cp)
 104 @@ -957,8 +966,38 @@ static void cp_reset_hw (struct cp_private *cp)
 105
 106  static inline void cp_start_hw (struct cp_private *cp)
 107  {
 108 +       dma_addr_t ring_dma;
 109 +
 110         cpw16(CpCmd, cp->cpcmd);
 111 +
 112 +       /*
 113 +        * These (at least TxRingAddr) need to be configured after the
 114 +        * corresponding bits in CpCmd are enabled. Datasheet v1.6 §6.33
 115 +        * (C+ Command Register) recommends that these and more be configured
 116 +        * *after* the [RT]xEnable bits in CpCmd are set. And on some hardware
 117 +        * it's been observed that the TxRingAddr is actually reset to garbage
 118 +        * when C+ mode Tx is enabled in CpCmd.
 119 +        */
 120 +       cpw32_f(HiTxRingAddr, 0);
 121 +       cpw32_f(HiTxRingAddr + 4, 0);
 122 +
 123 +       ring_dma = cp->ring_dma;
 124 +       cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
 125 +       cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
 126 +
 127 +       ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
 128 +       cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
 129 +       cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
 130 +
 131 +       /*
 132 +        * Strictly speaking, the datasheet says this should be enabled
 133 +        * *before* setting the descriptor addresses. But what, then, would
 134 +        * prevent it from doing DMA to random unconfigured addresses?
 135 +        * This variant appears to work fine.
 136 +        */
 137         cpw8(Cmd, RxOn | TxOn);
 138 +
 139 +       netdev_reset_queue(cp->dev);
 140  }
 141
 142  static void cp_enable_irq(struct cp_private *cp)
 143 @@ -969,7 +1008,6 @@ static void cp_enable_irq(struct cp_private *cp)
 144  static void cp_init_hw (struct cp_private *cp)
 145  {
 146         struct net_device *dev = cp->dev;
 147 -       dma_addr_t ring_dma;
 148
 149         cp_reset_hw(cp);
 150
 151 @@ -979,17 +1017,6 @@ static void cp_init_hw (struct cp_private *cp)
 152         cpw32_f (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
 153         cpw32_f (MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4)));
 154
 155 -       cpw32_f(HiTxRingAddr, 0);
 156 -       cpw32_f(HiTxRingAddr + 4, 0);
 157 -
 158 -       ring_dma = cp->ring_dma;
 159 -       cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
 160 -       cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
 161 -
 162 -       ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
 163 -       cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
 164 -       cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
 165 -
 166         cp_start_hw(cp);
 167         cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */
 168
 169 @@ -1192,6 +1219,7 @@ static void cp_tx_timeout(struct net_device *dev)
 170         cp_clean_rings(cp);
 171         rc = cp_init_rings(cp);
 172         cp_start_hw(cp);
 173 +       cp_enable_irq(cp);
 174
 175         netif_wake_queue(dev);
 176