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kernel: update bcma and ssb to version from wireless-testing/master tag master-2013...
[openwrt/staging/wigyori.git] / target / linux / generic / patches-3.7 / 025-bcma_backport.patch
1 --- a/arch/mips/bcm47xx/serial.c
2 +++ b/arch/mips/bcm47xx/serial.c
3 @@ -62,7 +62,7 @@ static int __init uart8250_init_bcma(voi
4
5 p->mapbase = (unsigned int) bcma_port->regs;
6 p->membase = (void *) bcma_port->regs;
7 - p->irq = bcma_port->irq + 2;
8 + p->irq = bcma_port->irq;
9 p->uartclk = bcma_port->baud_base;
10 p->regshift = bcma_port->reg_shift;
11 p->iotype = UPIO_MEM;
12 --- a/drivers/bcma/Kconfig
13 +++ b/drivers/bcma/Kconfig
14 @@ -26,6 +26,7 @@ config BCMA_HOST_PCI_POSSIBLE
15 config BCMA_HOST_PCI
16 bool "Support for BCMA on PCI-host bus"
17 depends on BCMA_HOST_PCI_POSSIBLE
18 + default y
19
20 config BCMA_DRIVER_PCI_HOSTMODE
21 bool "Driver for PCI core working in hostmode"
22 @@ -65,6 +66,14 @@ config BCMA_DRIVER_GMAC_CMN
23
24 If unsure, say N
25
26 +config BCMA_DRIVER_GPIO
27 + bool "BCMA GPIO driver"
28 + depends on BCMA && GPIOLIB
29 + help
30 + Driver to provide access to the GPIO pins of the bcma bus.
31 +
32 + If unsure, say N
33 +
34 config BCMA_DEBUG
35 bool "BCMA debugging"
36 depends on BCMA
37 --- a/drivers/bcma/Makefile
38 +++ b/drivers/bcma/Makefile
39 @@ -6,6 +6,7 @@ bcma-y += driver_pci.o
40 bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o
41 bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o
42 bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o
43 +bcma-$(CONFIG_BCMA_DRIVER_GPIO) += driver_gpio.o
44 bcma-$(CONFIG_BCMA_HOST_PCI) += host_pci.o
45 bcma-$(CONFIG_BCMA_HOST_SOC) += host_soc.o
46 obj-$(CONFIG_BCMA) += bcma.o
47 --- a/drivers/bcma/bcma_private.h
48 +++ b/drivers/bcma/bcma_private.h
49 @@ -22,6 +22,8 @@
50 struct bcma_bus;
51
52 /* main.c */
53 +bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
54 + int timeout);
55 int __devinit bcma_bus_register(struct bcma_bus *bus);
56 void bcma_bus_unregister(struct bcma_bus *bus);
57 int __init bcma_bus_early_register(struct bcma_bus *bus,
58 @@ -31,6 +33,8 @@ int __init bcma_bus_early_register(struc
59 int bcma_bus_suspend(struct bcma_bus *bus);
60 int bcma_bus_resume(struct bcma_bus *bus);
61 #endif
62 +struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
63 + u8 unit);
64
65 /* scan.c */
66 int bcma_bus_scan(struct bcma_bus *bus);
67 @@ -45,11 +49,12 @@ int bcma_sprom_get(struct bcma_bus *bus)
68 /* driver_chipcommon.c */
69 #ifdef CONFIG_BCMA_DRIVER_MIPS
70 void bcma_chipco_serial_init(struct bcma_drv_cc *cc);
71 +extern struct platform_device bcma_pflash_dev;
72 #endif /* CONFIG_BCMA_DRIVER_MIPS */
73
74 /* driver_chipcommon_pmu.c */
75 -u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc);
76 -u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc);
77 +u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc);
78 +u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc);
79
80 #ifdef CONFIG_BCMA_SFLASH
81 /* driver_chipcommon_sflash.c */
82 @@ -84,9 +89,26 @@ extern void __exit bcma_host_pci_exit(vo
83 /* driver_pci.c */
84 u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address);
85
86 +extern int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc);
87 +
88 #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
89 bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc);
90 void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
91 #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
92
93 +#ifdef CONFIG_BCMA_DRIVER_GPIO
94 +/* driver_gpio.c */
95 +int bcma_gpio_init(struct bcma_drv_cc *cc);
96 +int bcma_gpio_unregister(struct bcma_drv_cc *cc);
97 +#else
98 +static inline int bcma_gpio_init(struct bcma_drv_cc *cc)
99 +{
100 + return -ENOTSUPP;
101 +}
102 +static inline int bcma_gpio_unregister(struct bcma_drv_cc *cc)
103 +{
104 + return 0;
105 +}
106 +#endif /* CONFIG_BCMA_DRIVER_GPIO */
107 +
108 #endif
109 --- a/drivers/bcma/core.c
110 +++ b/drivers/bcma/core.c
111 @@ -9,6 +9,25 @@
112 #include <linux/export.h>
113 #include <linux/bcma/bcma.h>
114
115 +static bool bcma_core_wait_value(struct bcma_device *core, u16 reg, u32 mask,
116 + u32 value, int timeout)
117 +{
118 + unsigned long deadline = jiffies + timeout;
119 + u32 val;
120 +
121 + do {
122 + val = bcma_aread32(core, reg);
123 + if ((val & mask) == value)
124 + return true;
125 + cpu_relax();
126 + udelay(10);
127 + } while (!time_after_eq(jiffies, deadline));
128 +
129 + bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg);
130 +
131 + return false;
132 +}
133 +
134 bool bcma_core_is_enabled(struct bcma_device *core)
135 {
136 if ((bcma_aread32(core, BCMA_IOCTL) & (BCMA_IOCTL_CLK | BCMA_IOCTL_FGC))
137 @@ -25,13 +44,15 @@ void bcma_core_disable(struct bcma_devic
138 if (bcma_aread32(core, BCMA_RESET_CTL) & BCMA_RESET_CTL_RESET)
139 return;
140
141 - bcma_awrite32(core, BCMA_IOCTL, flags);
142 - bcma_aread32(core, BCMA_IOCTL);
143 - udelay(10);
144 + bcma_core_wait_value(core, BCMA_RESET_ST, ~0, 0, 300);
145
146 bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
147 bcma_aread32(core, BCMA_RESET_CTL);
148 udelay(1);
149 +
150 + bcma_awrite32(core, BCMA_IOCTL, flags);
151 + bcma_aread32(core, BCMA_IOCTL);
152 + udelay(10);
153 }
154 EXPORT_SYMBOL_GPL(bcma_core_disable);
155
156 @@ -43,6 +64,7 @@ int bcma_core_enable(struct bcma_device
157 bcma_aread32(core, BCMA_IOCTL);
158
159 bcma_awrite32(core, BCMA_RESET_CTL, 0);
160 + bcma_aread32(core, BCMA_RESET_CTL);
161 udelay(1);
162
163 bcma_awrite32(core, BCMA_IOCTL, (BCMA_IOCTL_CLK | flags));
164 @@ -104,7 +126,13 @@ void bcma_core_pll_ctl(struct bcma_devic
165 if (i)
166 bcma_err(core->bus, "PLL enable timeout\n");
167 } else {
168 - bcma_warn(core->bus, "Disabling PLL not supported yet!\n");
169 + /*
170 + * Mask the PLL but don't wait for it to be disabled. PLL may be
171 + * shared between cores and will be still up if there is another
172 + * core using it.
173 + */
174 + bcma_mask32(core, BCMA_CLKCTLST, ~req);
175 + bcma_read32(core, BCMA_CLKCTLST);
176 }
177 }
178 EXPORT_SYMBOL_GPL(bcma_core_pll_ctl);
179 --- a/drivers/bcma/driver_chipcommon.c
180 +++ b/drivers/bcma/driver_chipcommon.c
181 @@ -4,12 +4,15 @@
182 *
183 * Copyright 2005, Broadcom Corporation
184 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
185 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
186 *
187 * Licensed under the GNU/GPL. See COPYING for details.
188 */
189
190 #include "bcma_private.h"
191 +#include <linux/bcm47xx_wdt.h>
192 #include <linux/export.h>
193 +#include <linux/platform_device.h>
194 #include <linux/bcma/bcma.h>
195
196 static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
197 @@ -22,23 +25,130 @@ static inline u32 bcma_cc_write32_masked
198 return value;
199 }
200
201 -void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
202 +u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
203 {
204 - u32 leddc_on = 10;
205 - u32 leddc_off = 90;
206 + if (cc->capabilities & BCMA_CC_CAP_PMU)
207 + return bcma_pmu_get_alp_clock(cc);
208
209 - if (cc->setup_done)
210 + return 20000000;
211 +}
212 +EXPORT_SYMBOL_GPL(bcma_chipco_get_alp_clock);
213 +
214 +static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc)
215 +{
216 + struct bcma_bus *bus = cc->core->bus;
217 + u32 nb;
218 +
219 + if (cc->capabilities & BCMA_CC_CAP_PMU) {
220 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
221 + nb = 32;
222 + else if (cc->core->id.rev < 26)
223 + nb = 16;
224 + else
225 + nb = (cc->core->id.rev >= 37) ? 32 : 24;
226 + } else {
227 + nb = 28;
228 + }
229 + if (nb == 32)
230 + return 0xffffffff;
231 + else
232 + return (1 << nb) - 1;
233 +}
234 +
235 +static u32 bcma_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
236 + u32 ticks)
237 +{
238 + struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
239 +
240 + return bcma_chipco_watchdog_timer_set(cc, ticks);
241 +}
242 +
243 +static u32 bcma_chipco_watchdog_timer_set_ms_wdt(struct bcm47xx_wdt *wdt,
244 + u32 ms)
245 +{
246 + struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
247 + u32 ticks;
248 +
249 + ticks = bcma_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
250 + return ticks / cc->ticks_per_ms;
251 +}
252 +
253 +static int bcma_chipco_watchdog_ticks_per_ms(struct bcma_drv_cc *cc)
254 +{
255 + struct bcma_bus *bus = cc->core->bus;
256 +
257 + if (cc->capabilities & BCMA_CC_CAP_PMU) {
258 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
259 + /* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP clock */
260 + return bcma_chipco_get_alp_clock(cc) / 4000;
261 + else
262 + /* based on 32KHz ILP clock */
263 + return 32;
264 + } else {
265 + return bcma_chipco_get_alp_clock(cc) / 1000;
266 + }
267 +}
268 +
269 +int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc)
270 +{
271 + struct bcm47xx_wdt wdt = {};
272 + struct platform_device *pdev;
273 +
274 + wdt.driver_data = cc;
275 + wdt.timer_set = bcma_chipco_watchdog_timer_set_wdt;
276 + wdt.timer_set_ms = bcma_chipco_watchdog_timer_set_ms_wdt;
277 + wdt.max_timer_ms = bcma_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
278 +
279 + pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
280 + cc->core->bus->num, &wdt,
281 + sizeof(wdt));
282 + if (IS_ERR(pdev))
283 + return PTR_ERR(pdev);
284 +
285 + cc->watchdog = pdev;
286 +
287 + return 0;
288 +}
289 +
290 +void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
291 +{
292 + if (cc->early_setup_done)
293 return;
294
295 + spin_lock_init(&cc->gpio_lock);
296 +
297 if (cc->core->id.rev >= 11)
298 cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
299 cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP);
300 if (cc->core->id.rev >= 35)
301 cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);
302
303 + if (cc->capabilities & BCMA_CC_CAP_PMU)
304 + bcma_pmu_early_init(cc);
305 +
306 + cc->early_setup_done = true;
307 +}
308 +
309 +void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
310 +{
311 + u32 leddc_on = 10;
312 + u32 leddc_off = 90;
313 +
314 + if (cc->setup_done)
315 + return;
316 +
317 + bcma_core_chipcommon_early_init(cc);
318 +
319 if (cc->core->id.rev >= 20) {
320 - bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
321 - bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
322 + u32 pullup = 0, pulldown = 0;
323 +
324 + if (cc->core->bus->chipinfo.id == BCMA_CHIP_ID_BCM43142) {
325 + pullup = 0x402e0;
326 + pulldown = 0x20500;
327 + }
328 +
329 + bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, pullup);
330 + bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, pulldown);
331 }
332
333 if (cc->capabilities & BCMA_CC_CAP_PMU)
334 @@ -56,15 +166,33 @@ void bcma_core_chipcommon_init(struct bc
335 ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
336 (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT)));
337 }
338 + cc->ticks_per_ms = bcma_chipco_watchdog_ticks_per_ms(cc);
339
340 cc->setup_done = true;
341 }
342
343 /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
344 -void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
345 +u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
346 {
347 - /* instant NMI */
348 - bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
349 + u32 maxt;
350 + enum bcma_clkmode clkmode;
351 +
352 + maxt = bcma_chipco_watchdog_get_max_timer(cc);
353 + if (cc->capabilities & BCMA_CC_CAP_PMU) {
354 + if (ticks == 1)
355 + ticks = 2;
356 + else if (ticks > maxt)
357 + ticks = maxt;
358 + bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
359 + } else {
360 + clkmode = ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC;
361 + bcma_core_set_clockmode(cc->core, clkmode);
362 + if (ticks > maxt)
363 + ticks = maxt;
364 + /* instant NMI */
365 + bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
366 + }
367 + return ticks;
368 }
369
370 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
371 @@ -84,28 +212,99 @@ u32 bcma_chipco_gpio_in(struct bcma_drv_
372
373 u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value)
374 {
375 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
376 + unsigned long flags;
377 + u32 res;
378 +
379 + spin_lock_irqsave(&cc->gpio_lock, flags);
380 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
381 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
382 +
383 + return res;
384 }
385 +EXPORT_SYMBOL_GPL(bcma_chipco_gpio_out);
386
387 u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
388 {
389 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
390 + unsigned long flags;
391 + u32 res;
392 +
393 + spin_lock_irqsave(&cc->gpio_lock, flags);
394 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
395 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
396 +
397 + return res;
398 }
399 +EXPORT_SYMBOL_GPL(bcma_chipco_gpio_outen);
400
401 +/*
402 + * If the bit is set to 0, chipcommon controlls this GPIO,
403 + * if the bit is set to 1, it is used by some part of the chip and not our code.
404 + */
405 u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value)
406 {
407 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
408 + unsigned long flags;
409 + u32 res;
410 +
411 + spin_lock_irqsave(&cc->gpio_lock, flags);
412 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
413 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
414 +
415 + return res;
416 }
417 EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control);
418
419 u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value)
420 {
421 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
422 + unsigned long flags;
423 + u32 res;
424 +
425 + spin_lock_irqsave(&cc->gpio_lock, flags);
426 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
427 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
428 +
429 + return res;
430 }
431
432 u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value)
433 {
434 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
435 + unsigned long flags;
436 + u32 res;
437 +
438 + spin_lock_irqsave(&cc->gpio_lock, flags);
439 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
440 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
441 +
442 + return res;
443 +}
444 +
445 +u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value)
446 +{
447 + unsigned long flags;
448 + u32 res;
449 +
450 + if (cc->core->id.rev < 20)
451 + return 0;
452 +
453 + spin_lock_irqsave(&cc->gpio_lock, flags);
454 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLUP, mask, value);
455 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
456 +
457 + return res;
458 +}
459 +
460 +u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value)
461 +{
462 + unsigned long flags;
463 + u32 res;
464 +
465 + if (cc->core->id.rev < 20)
466 + return 0;
467 +
468 + spin_lock_irqsave(&cc->gpio_lock, flags);
469 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLDOWN, mask, value);
470 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
471 +
472 + return res;
473 }
474
475 #ifdef CONFIG_BCMA_DRIVER_MIPS
476 @@ -118,8 +317,7 @@ void bcma_chipco_serial_init(struct bcma
477 struct bcma_serial_port *ports = cc->serial_ports;
478
479 if (ccrev >= 11 && ccrev != 15) {
480 - /* Fixed ALP clock */
481 - baud_base = bcma_pmu_alp_clock(cc);
482 + baud_base = bcma_chipco_get_alp_clock(cc);
483 if (ccrev >= 21) {
484 /* Turn off UART clock before switching clocksource. */
485 bcma_cc_write32(cc, BCMA_CC_CORECTL,
486 @@ -141,7 +339,7 @@ void bcma_chipco_serial_init(struct bcma
487 return;
488 }
489
490 - irq = bcma_core_mips_irq(cc->core);
491 + irq = bcma_core_irq(cc->core);
492
493 /* Determine the registers of the UARTs */
494 cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART);
495 --- a/drivers/bcma/driver_chipcommon_nflash.c
496 +++ b/drivers/bcma/driver_chipcommon_nflash.c
497 @@ -5,11 +5,11 @@
498 * Licensed under the GNU/GPL. See COPYING for details.
499 */
500
501 +#include "bcma_private.h"
502 +
503 #include <linux/platform_device.h>
504 #include <linux/bcma/bcma.h>
505
506 -#include "bcma_private.h"
507 -
508 struct platform_device bcma_nflash_dev = {
509 .name = "bcma_nflash",
510 .num_resources = 0,
511 @@ -21,7 +21,7 @@ int bcma_nflash_init(struct bcma_drv_cc
512 struct bcma_bus *bus = cc->core->bus;
513
514 if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4706 &&
515 - cc->core->id.rev != 0x38) {
516 + cc->core->id.rev != 38) {
517 bcma_err(bus, "NAND flash on unsupported board!\n");
518 return -ENOTSUPP;
519 }
520 @@ -32,6 +32,9 @@ int bcma_nflash_init(struct bcma_drv_cc
521 }
522
523 cc->nflash.present = true;
524 + if (cc->core->id.rev == 38 &&
525 + (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT))
526 + cc->nflash.boot = true;
527
528 /* Prepare platform device, but don't register it yet. It's too early,
529 * malloc (required by device_private_init) is not available yet. */
530 --- a/drivers/bcma/driver_chipcommon_pmu.c
531 +++ b/drivers/bcma/driver_chipcommon_pmu.c
532 @@ -13,12 +13,13 @@
533 #include <linux/export.h>
534 #include <linux/bcma/bcma.h>
535
536 -static u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
537 +u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
538 {
539 bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
540 bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
541 return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
542 }
543 +EXPORT_SYMBOL_GPL(bcma_chipco_pll_read);
544
545 void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
546 {
547 @@ -55,6 +56,109 @@ void bcma_chipco_regctl_maskset(struct b
548 }
549 EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
550
551 +static u32 bcma_pmu_xtalfreq(struct bcma_drv_cc *cc)
552 +{
553 + u32 ilp_ctl, alp_hz;
554 +
555 + if (!(bcma_cc_read32(cc, BCMA_CC_PMU_STAT) &
556 + BCMA_CC_PMU_STAT_EXT_LPO_AVAIL))
557 + return 0;
558 +
559 + bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ,
560 + BIT(BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT));
561 + usleep_range(1000, 2000);
562 +
563 + ilp_ctl = bcma_cc_read32(cc, BCMA_CC_PMU_XTAL_FREQ);
564 + ilp_ctl &= BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK;
565 +
566 + bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ, 0);
567 +
568 + alp_hz = ilp_ctl * 32768 / 4;
569 + return (alp_hz + 50000) / 100000 * 100;
570 +}
571 +
572 +static void bcma_pmu2_pll_init0(struct bcma_drv_cc *cc, u32 xtalfreq)
573 +{
574 + struct bcma_bus *bus = cc->core->bus;
575 + u32 freq_tgt_target = 0, freq_tgt_current;
576 + u32 pll0, mask;
577 +
578 + switch (bus->chipinfo.id) {
579 + case BCMA_CHIP_ID_BCM43142:
580 + /* pmu2_xtaltab0_adfll_485 */
581 + switch (xtalfreq) {
582 + case 12000:
583 + freq_tgt_target = 0x50D52;
584 + break;
585 + case 20000:
586 + freq_tgt_target = 0x307FE;
587 + break;
588 + case 26000:
589 + freq_tgt_target = 0x254EA;
590 + break;
591 + case 37400:
592 + freq_tgt_target = 0x19EF8;
593 + break;
594 + case 52000:
595 + freq_tgt_target = 0x12A75;
596 + break;
597 + }
598 + break;
599 + }
600 +
601 + if (!freq_tgt_target) {
602 + bcma_err(bus, "Unknown TGT frequency for xtalfreq %d\n",
603 + xtalfreq);
604 + return;
605 + }
606 +
607 + pll0 = bcma_chipco_pll_read(cc, BCMA_CC_PMU15_PLL_PLLCTL0);
608 + freq_tgt_current = (pll0 & BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK) >>
609 + BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
610 +
611 + if (freq_tgt_current == freq_tgt_target) {
612 + bcma_debug(bus, "Target TGT frequency already set\n");
613 + return;
614 + }
615 +
616 + /* Turn off PLL */
617 + switch (bus->chipinfo.id) {
618 + case BCMA_CHIP_ID_BCM43142:
619 + mask = (u32)~(BCMA_RES_4314_HT_AVAIL |
620 + BCMA_RES_4314_MACPHY_CLK_AVAIL);
621 +
622 + bcma_cc_mask32(cc, BCMA_CC_PMU_MINRES_MSK, mask);
623 + bcma_cc_mask32(cc, BCMA_CC_PMU_MAXRES_MSK, mask);
624 + bcma_wait_value(cc->core, BCMA_CLKCTLST,
625 + BCMA_CLKCTLST_HAVEHT, 0, 20000);
626 + break;
627 + }
628 +
629 + pll0 &= ~BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK;
630 + pll0 |= freq_tgt_target << BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
631 + bcma_chipco_pll_write(cc, BCMA_CC_PMU15_PLL_PLLCTL0, pll0);
632 +
633 + /* Flush */
634 + if (cc->pmu.rev >= 2)
635 + bcma_cc_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD);
636 +
637 + /* TODO: Do we need to update OTP? */
638 +}
639 +
640 +static void bcma_pmu_pll_init(struct bcma_drv_cc *cc)
641 +{
642 + struct bcma_bus *bus = cc->core->bus;
643 + u32 xtalfreq = bcma_pmu_xtalfreq(cc);
644 +
645 + switch (bus->chipinfo.id) {
646 + case BCMA_CHIP_ID_BCM43142:
647 + if (xtalfreq == 0)
648 + xtalfreq = 20000;
649 + bcma_pmu2_pll_init0(cc, xtalfreq);
650 + break;
651 + }
652 +}
653 +
654 static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
655 {
656 struct bcma_bus *bus = cc->core->bus;
657 @@ -65,6 +169,25 @@ static void bcma_pmu_resources_init(stru
658 min_msk = 0x200D;
659 max_msk = 0xFFFF;
660 break;
661 + case BCMA_CHIP_ID_BCM43142:
662 + min_msk = BCMA_RES_4314_LPLDO_PU |
663 + BCMA_RES_4314_PMU_SLEEP_DIS |
664 + BCMA_RES_4314_PMU_BG_PU |
665 + BCMA_RES_4314_CBUCK_LPOM_PU |
666 + BCMA_RES_4314_CBUCK_PFM_PU |
667 + BCMA_RES_4314_CLDO_PU |
668 + BCMA_RES_4314_LPLDO2_LVM |
669 + BCMA_RES_4314_WL_PMU_PU |
670 + BCMA_RES_4314_LDO3P3_PU |
671 + BCMA_RES_4314_OTP_PU |
672 + BCMA_RES_4314_WL_PWRSW_PU |
673 + BCMA_RES_4314_LQ_AVAIL |
674 + BCMA_RES_4314_LOGIC_RET |
675 + BCMA_RES_4314_MEM_SLEEP |
676 + BCMA_RES_4314_MACPHY_RET |
677 + BCMA_RES_4314_WL_CORE_READY;
678 + max_msk = 0x3FFFFFFF;
679 + break;
680 default:
681 bcma_debug(bus, "PMU resource config unknown or not needed for device 0x%04X\n",
682 bus->chipinfo.id);
683 @@ -144,7 +267,7 @@ static void bcma_pmu_workarounds(struct
684 }
685 }
686
687 -void bcma_pmu_init(struct bcma_drv_cc *cc)
688 +void bcma_pmu_early_init(struct bcma_drv_cc *cc)
689 {
690 u32 pmucap;
691
692 @@ -153,7 +276,10 @@ void bcma_pmu_init(struct bcma_drv_cc *c
693
694 bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n",
695 cc->pmu.rev, pmucap);
696 +}
697
698 +void bcma_pmu_init(struct bcma_drv_cc *cc)
699 +{
700 if (cc->pmu.rev == 1)
701 bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
702 ~BCMA_CC_PMU_CTL_NOILPONW);
703 @@ -161,28 +287,45 @@ void bcma_pmu_init(struct bcma_drv_cc *c
704 bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
705 BCMA_CC_PMU_CTL_NOILPONW);
706
707 + bcma_pmu_pll_init(cc);
708 bcma_pmu_resources_init(cc);
709 bcma_pmu_workarounds(cc);
710 }
711
712 -u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
713 +u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc)
714 {
715 struct bcma_bus *bus = cc->core->bus;
716
717 switch (bus->chipinfo.id) {
718 + case BCMA_CHIP_ID_BCM4313:
719 + case BCMA_CHIP_ID_BCM43224:
720 + case BCMA_CHIP_ID_BCM43225:
721 + case BCMA_CHIP_ID_BCM43227:
722 + case BCMA_CHIP_ID_BCM43228:
723 + case BCMA_CHIP_ID_BCM4331:
724 + case BCMA_CHIP_ID_BCM43421:
725 + case BCMA_CHIP_ID_BCM43428:
726 + case BCMA_CHIP_ID_BCM43431:
727 case BCMA_CHIP_ID_BCM4716:
728 - case BCMA_CHIP_ID_BCM4748:
729 case BCMA_CHIP_ID_BCM47162:
730 - case BCMA_CHIP_ID_BCM4313:
731 - case BCMA_CHIP_ID_BCM5357:
732 + case BCMA_CHIP_ID_BCM4748:
733 case BCMA_CHIP_ID_BCM4749:
734 + case BCMA_CHIP_ID_BCM5357:
735 case BCMA_CHIP_ID_BCM53572:
736 + case BCMA_CHIP_ID_BCM6362:
737 /* always 20Mhz */
738 return 20000 * 1000;
739 - case BCMA_CHIP_ID_BCM5356:
740 case BCMA_CHIP_ID_BCM4706:
741 + case BCMA_CHIP_ID_BCM5356:
742 /* always 25Mhz */
743 return 25000 * 1000;
744 + case BCMA_CHIP_ID_BCM43460:
745 + case BCMA_CHIP_ID_BCM4352:
746 + case BCMA_CHIP_ID_BCM4360:
747 + if (cc->status & BCMA_CC_CHIPST_4360_XTAL_40MZ)
748 + return 40000 * 1000;
749 + else
750 + return 20000 * 1000;
751 default:
752 bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
753 bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
754 @@ -193,7 +336,7 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c
755 /* Find the output of the "m" pll divider given pll controls that start with
756 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
757 */
758 -static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
759 +static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
760 {
761 u32 tmp, div, ndiv, p1, p2, fc;
762 struct bcma_bus *bus = cc->core->bus;
763 @@ -222,14 +365,14 @@ static u32 bcma_pmu_clock(struct bcma_dr
764 ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
765
766 /* Do calculation in Mhz */
767 - fc = bcma_pmu_alp_clock(cc) / 1000000;
768 + fc = bcma_pmu_get_alp_clock(cc) / 1000000;
769 fc = (p1 * ndiv * fc) / p2;
770
771 /* Return clock in Hertz */
772 return (fc / div) * 1000000;
773 }
774
775 -static u32 bcma_pmu_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
776 +static u32 bcma_pmu_pll_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
777 {
778 u32 tmp, ndiv, p1div, p2div;
779 u32 clock;
780 @@ -260,7 +403,7 @@ static u32 bcma_pmu_clock_bcm4706(struct
781 }
782
783 /* query bus clock frequency for PMU-enabled chipcommon */
784 -static u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
785 +u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc)
786 {
787 struct bcma_bus *bus = cc->core->bus;
788
789 @@ -268,40 +411,43 @@ static u32 bcma_pmu_get_clockcontrol(str
790 case BCMA_CHIP_ID_BCM4716:
791 case BCMA_CHIP_ID_BCM4748:
792 case BCMA_CHIP_ID_BCM47162:
793 - return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
794 - BCMA_CC_PMU5_MAINPLL_SSB);
795 + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
796 + BCMA_CC_PMU5_MAINPLL_SSB);
797 case BCMA_CHIP_ID_BCM5356:
798 - return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
799 - BCMA_CC_PMU5_MAINPLL_SSB);
800 + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
801 + BCMA_CC_PMU5_MAINPLL_SSB);
802 case BCMA_CHIP_ID_BCM5357:
803 case BCMA_CHIP_ID_BCM4749:
804 - return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
805 - BCMA_CC_PMU5_MAINPLL_SSB);
806 + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
807 + BCMA_CC_PMU5_MAINPLL_SSB);
808 case BCMA_CHIP_ID_BCM4706:
809 - return bcma_pmu_clock_bcm4706(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
810 - BCMA_CC_PMU5_MAINPLL_SSB);
811 + return bcma_pmu_pll_clock_bcm4706(cc,
812 + BCMA_CC_PMU4706_MAINPLL_PLL0,
813 + BCMA_CC_PMU5_MAINPLL_SSB);
814 case BCMA_CHIP_ID_BCM53572:
815 return 75000000;
816 default:
817 - bcma_warn(bus, "No backplane clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
818 + bcma_warn(bus, "No bus clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
819 bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
820 }
821 return BCMA_CC_PMU_HT_CLOCK;
822 }
823 +EXPORT_SYMBOL_GPL(bcma_pmu_get_bus_clock);
824
825 /* query cpu clock frequency for PMU-enabled chipcommon */
826 -u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
827 +u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc)
828 {
829 struct bcma_bus *bus = cc->core->bus;
830
831 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
832 return 300000000;
833
834 + /* New PMUs can have different clock for bus and CPU */
835 if (cc->pmu.rev >= 5) {
836 u32 pll;
837 switch (bus->chipinfo.id) {
838 case BCMA_CHIP_ID_BCM4706:
839 - return bcma_pmu_clock_bcm4706(cc,
840 + return bcma_pmu_pll_clock_bcm4706(cc,
841 BCMA_CC_PMU4706_MAINPLL_PLL0,
842 BCMA_CC_PMU5_MAINPLL_CPU);
843 case BCMA_CHIP_ID_BCM5356:
844 @@ -316,10 +462,11 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr
845 break;
846 }
847
848 - return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
849 + return bcma_pmu_pll_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
850 }
851
852 - return bcma_pmu_get_clockcontrol(cc);
853 + /* On old PMUs CPU has the same clock as the bus */
854 + return bcma_pmu_get_bus_clock(cc);
855 }
856
857 static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
858 @@ -365,7 +512,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
859 tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
860 bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
861
862 - tmp = 1 << 10;
863 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
864 break;
865
866 case BCMA_CHIP_ID_BCM4331:
867 @@ -386,7 +533,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
868 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
869 0x03000a08);
870 }
871 - tmp = 1 << 10;
872 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
873 break;
874
875 case BCMA_CHIP_ID_BCM43224:
876 @@ -419,7 +566,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
877 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
878 0x88888815);
879 }
880 - tmp = 1 << 10;
881 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
882 break;
883
884 case BCMA_CHIP_ID_BCM4716:
885 @@ -453,7 +600,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
886 0x88888815);
887 }
888
889 - tmp = 3 << 9;
890 + tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
891 break;
892
893 case BCMA_CHIP_ID_BCM43227:
894 @@ -489,7 +636,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
895 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
896 0x88888815);
897 }
898 - tmp = 1 << 10;
899 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
900 break;
901 default:
902 bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
903 --- a/drivers/bcma/driver_chipcommon_sflash.c
904 +++ b/drivers/bcma/driver_chipcommon_sflash.c
905 @@ -5,14 +5,14 @@
906 * Licensed under the GNU/GPL. See COPYING for details.
907 */
908
909 +#include "bcma_private.h"
910 +
911 #include <linux/platform_device.h>
912 #include <linux/bcma/bcma.h>
913
914 -#include "bcma_private.h"
915 -
916 static struct resource bcma_sflash_resource = {
917 .name = "bcma_sflash",
918 - .start = BCMA_SFLASH,
919 + .start = BCMA_SOC_FLASH2,
920 .end = 0,
921 .flags = IORESOURCE_MEM | IORESOURCE_READONLY,
922 };
923 @@ -30,16 +30,43 @@ struct bcma_sflash_tbl_e {
924 u16 numblocks;
925 };
926
927 -static struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
928 - { "", 0x14, 0x10000, 32, },
929 +static const struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
930 + { "M25P20", 0x11, 0x10000, 4, },
931 + { "M25P40", 0x12, 0x10000, 8, },
932 +
933 + { "M25P16", 0x14, 0x10000, 32, },
934 + { "M25P32", 0x15, 0x10000, 64, },
935 + { "M25P64", 0x16, 0x10000, 128, },
936 + { "M25FL128", 0x17, 0x10000, 256, },
937 { 0 },
938 };
939
940 -static struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
941 +static const struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
942 + { "SST25WF512", 1, 0x1000, 16, },
943 + { "SST25VF512", 0x48, 0x1000, 16, },
944 + { "SST25WF010", 2, 0x1000, 32, },
945 + { "SST25VF010", 0x49, 0x1000, 32, },
946 + { "SST25WF020", 3, 0x1000, 64, },
947 + { "SST25VF020", 0x43, 0x1000, 64, },
948 + { "SST25WF040", 4, 0x1000, 128, },
949 + { "SST25VF040", 0x44, 0x1000, 128, },
950 + { "SST25VF040B", 0x8d, 0x1000, 128, },
951 + { "SST25WF080", 5, 0x1000, 256, },
952 + { "SST25VF080B", 0x8e, 0x1000, 256, },
953 + { "SST25VF016", 0x41, 0x1000, 512, },
954 + { "SST25VF032", 0x4a, 0x1000, 1024, },
955 + { "SST25VF064", 0x4b, 0x1000, 2048, },
956 { 0 },
957 };
958
959 -static struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
960 +static const struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
961 + { "AT45DB011", 0xc, 256, 512, },
962 + { "AT45DB021", 0x14, 256, 1024, },
963 + { "AT45DB041", 0x1c, 256, 2048, },
964 + { "AT45DB081", 0x24, 256, 4096, },
965 + { "AT45DB161", 0x2c, 512, 4096, },
966 + { "AT45DB321", 0x34, 512, 8192, },
967 + { "AT45DB642", 0x3c, 1024, 8192, },
968 { 0 },
969 };
970
971 @@ -62,7 +89,7 @@ int bcma_sflash_init(struct bcma_drv_cc
972 {
973 struct bcma_bus *bus = cc->core->bus;
974 struct bcma_sflash *sflash = &cc->sflash;
975 - struct bcma_sflash_tbl_e *e;
976 + const struct bcma_sflash_tbl_e *e;
977 u32 id, id2;
978
979 switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
980 @@ -84,6 +111,8 @@ int bcma_sflash_init(struct bcma_drv_cc
981 break;
982 }
983 break;
984 + case 0x13:
985 + return -ENOTSUPP;
986 default:
987 for (e = bcma_sflash_st_tbl; e->name; e++) {
988 if (e->id == id)
989 @@ -116,7 +145,7 @@ int bcma_sflash_init(struct bcma_drv_cc
990 return -ENOTSUPP;
991 }
992
993 - sflash->window = BCMA_SFLASH;
994 + sflash->window = BCMA_SOC_FLASH2;
995 sflash->blocksize = e->blocksize;
996 sflash->numblocks = e->numblocks;
997 sflash->size = sflash->blocksize * sflash->numblocks;
998 --- /dev/null
999 +++ b/drivers/bcma/driver_gpio.c
1000 @@ -0,0 +1,114 @@
1001 +/*
1002 + * Broadcom specific AMBA
1003 + * GPIO driver
1004 + *
1005 + * Copyright 2011, Broadcom Corporation
1006 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
1007 + *
1008 + * Licensed under the GNU/GPL. See COPYING for details.
1009 + */
1010 +
1011 +#include <linux/gpio.h>
1012 +#include <linux/export.h>
1013 +#include <linux/bcma/bcma.h>
1014 +
1015 +#include "bcma_private.h"
1016 +
1017 +static inline struct bcma_drv_cc *bcma_gpio_get_cc(struct gpio_chip *chip)
1018 +{
1019 + return container_of(chip, struct bcma_drv_cc, gpio);
1020 +}
1021 +
1022 +static int bcma_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
1023 +{
1024 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1025 +
1026 + return !!bcma_chipco_gpio_in(cc, 1 << gpio);
1027 +}
1028 +
1029 +static void bcma_gpio_set_value(struct gpio_chip *chip, unsigned gpio,
1030 + int value)
1031 +{
1032 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1033 +
1034 + bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0);
1035 +}
1036 +
1037 +static int bcma_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
1038 +{
1039 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1040 +
1041 + bcma_chipco_gpio_outen(cc, 1 << gpio, 0);
1042 + return 0;
1043 +}
1044 +
1045 +static int bcma_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
1046 + int value)
1047 +{
1048 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1049 +
1050 + bcma_chipco_gpio_outen(cc, 1 << gpio, 1 << gpio);
1051 + bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0);
1052 + return 0;
1053 +}
1054 +
1055 +static int bcma_gpio_request(struct gpio_chip *chip, unsigned gpio)
1056 +{
1057 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1058 +
1059 + bcma_chipco_gpio_control(cc, 1 << gpio, 0);
1060 + /* clear pulldown */
1061 + bcma_chipco_gpio_pulldown(cc, 1 << gpio, 0);
1062 + /* Set pullup */
1063 + bcma_chipco_gpio_pullup(cc, 1 << gpio, 1 << gpio);
1064 +
1065 + return 0;
1066 +}
1067 +
1068 +static void bcma_gpio_free(struct gpio_chip *chip, unsigned gpio)
1069 +{
1070 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1071 +
1072 + /* clear pullup */
1073 + bcma_chipco_gpio_pullup(cc, 1 << gpio, 0);
1074 +}
1075 +
1076 +static int bcma_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
1077 +{
1078 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1079 +
1080 + if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
1081 + return bcma_core_irq(cc->core);
1082 + else
1083 + return -EINVAL;
1084 +}
1085 +
1086 +int bcma_gpio_init(struct bcma_drv_cc *cc)
1087 +{
1088 + struct gpio_chip *chip = &cc->gpio;
1089 +
1090 + chip->label = "bcma_gpio";
1091 + chip->owner = THIS_MODULE;
1092 + chip->request = bcma_gpio_request;
1093 + chip->free = bcma_gpio_free;
1094 + chip->get = bcma_gpio_get_value;
1095 + chip->set = bcma_gpio_set_value;
1096 + chip->direction_input = bcma_gpio_direction_input;
1097 + chip->direction_output = bcma_gpio_direction_output;
1098 + chip->to_irq = bcma_gpio_to_irq;
1099 + chip->ngpio = 16;
1100 + /* There is just one SoC in one device and its GPIO addresses should be
1101 + * deterministic to address them more easily. The other buses could get
1102 + * a random base number. */
1103 + if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
1104 + chip->base = 0;
1105 + else
1106 + chip->base = -1;
1107 +
1108 + return gpiochip_add(chip);
1109 +}
1110 +
1111 +int bcma_gpio_unregister(struct bcma_drv_cc *cc)
1112 +{
1113 + return gpiochip_remove(&cc->gpio);
1114 +}
1115 --- a/drivers/bcma/driver_mips.c
1116 +++ b/drivers/bcma/driver_mips.c
1117 @@ -14,11 +14,33 @@
1118
1119 #include <linux/bcma/bcma.h>
1120
1121 +#include <linux/mtd/physmap.h>
1122 +#include <linux/platform_device.h>
1123 #include <linux/serial.h>
1124 #include <linux/serial_core.h>
1125 #include <linux/serial_reg.h>
1126 #include <linux/time.h>
1127
1128 +static const char * const part_probes[] = { "bcm47xxpart", NULL };
1129 +
1130 +static struct physmap_flash_data bcma_pflash_data = {
1131 + .part_probe_types = part_probes,
1132 +};
1133 +
1134 +static struct resource bcma_pflash_resource = {
1135 + .name = "bcma_pflash",
1136 + .flags = IORESOURCE_MEM,
1137 +};
1138 +
1139 +struct platform_device bcma_pflash_dev = {
1140 + .name = "physmap-flash",
1141 + .dev = {
1142 + .platform_data = &bcma_pflash_data,
1143 + },
1144 + .resource = &bcma_pflash_resource,
1145 + .num_resources = 1,
1146 +};
1147 +
1148 /* The 47162a0 hangs when reading MIPS DMP registers registers */
1149 static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev)
1150 {
1151 @@ -74,28 +96,41 @@ static u32 bcma_core_mips_irqflag(struct
1152 return dev->core_index;
1153 flag = bcma_aread32(dev, BCMA_MIPS_OOBSELOUTA30);
1154
1155 - return flag & 0x1F;
1156 + if (flag)
1157 + return flag & 0x1F;
1158 + else
1159 + return 0x3f;
1160 }
1161
1162 /* Get the MIPS IRQ assignment for a specified device.
1163 * If unassigned, 0 is returned.
1164 + * If disabled, 5 is returned.
1165 + * If not supported, 6 is returned.
1166 */
1167 -unsigned int bcma_core_mips_irq(struct bcma_device *dev)
1168 +static unsigned int bcma_core_mips_irq(struct bcma_device *dev)
1169 {
1170 struct bcma_device *mdev = dev->bus->drv_mips.core;
1171 u32 irqflag;
1172 unsigned int irq;
1173
1174 irqflag = bcma_core_mips_irqflag(dev);
1175 + if (irqflag == 0x3f)
1176 + return 6;
1177
1178 - for (irq = 1; irq <= 4; irq++)
1179 + for (irq = 0; irq <= 4; irq++)
1180 if (bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq)) &
1181 (1 << irqflag))
1182 return irq;
1183
1184 - return 0;
1185 + return 5;
1186 +}
1187 +
1188 +unsigned int bcma_core_irq(struct bcma_device *dev)
1189 +{
1190 + unsigned int mips_irq = bcma_core_mips_irq(dev);
1191 + return mips_irq <= 4 ? mips_irq + 2 : 0;
1192 }
1193 -EXPORT_SYMBOL(bcma_core_mips_irq);
1194 +EXPORT_SYMBOL(bcma_core_irq);
1195
1196 static void bcma_core_mips_set_irq(struct bcma_device *dev, unsigned int irq)
1197 {
1198 @@ -114,7 +149,7 @@ static void bcma_core_mips_set_irq(struc
1199 bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0),
1200 bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) &
1201 ~(1 << irqflag));
1202 - else
1203 + else if (oldirq != 5)
1204 bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(oldirq), 0);
1205
1206 /* assign the new one */
1207 @@ -123,9 +158,9 @@ static void bcma_core_mips_set_irq(struc
1208 bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) |
1209 (1 << irqflag));
1210 } else {
1211 - u32 oldirqflag = bcma_read32(mdev,
1212 - BCMA_MIPS_MIPS74K_INTMASK(irq));
1213 - if (oldirqflag) {
1214 + u32 irqinitmask = bcma_read32(mdev,
1215 + BCMA_MIPS_MIPS74K_INTMASK(irq));
1216 + if (irqinitmask) {
1217 struct bcma_device *core;
1218
1219 /* backplane irq line is in use, find out who uses
1220 @@ -133,7 +168,7 @@ static void bcma_core_mips_set_irq(struc
1221 */
1222 list_for_each_entry(core, &bus->cores, list) {
1223 if ((1 << bcma_core_mips_irqflag(core)) ==
1224 - oldirqflag) {
1225 + irqinitmask) {
1226 bcma_core_mips_set_irq(core, 0);
1227 break;
1228 }
1229 @@ -143,15 +178,31 @@ static void bcma_core_mips_set_irq(struc
1230 1 << irqflag);
1231 }
1232
1233 - bcma_info(bus, "set_irq: core 0x%04x, irq %d => %d\n",
1234 - dev->id.id, oldirq + 2, irq + 2);
1235 + bcma_debug(bus, "set_irq: core 0x%04x, irq %d => %d\n",
1236 + dev->id.id, oldirq <= 4 ? oldirq + 2 : 0, irq + 2);
1237 +}
1238 +
1239 +static void bcma_core_mips_set_irq_name(struct bcma_bus *bus, unsigned int irq,
1240 + u16 coreid, u8 unit)
1241 +{
1242 + struct bcma_device *core;
1243 +
1244 + core = bcma_find_core_unit(bus, coreid, unit);
1245 + if (!core) {
1246 + bcma_warn(bus,
1247 + "Can not find core (id: 0x%x, unit %i) for IRQ configuration.\n",
1248 + coreid, unit);
1249 + return;
1250 + }
1251 +
1252 + bcma_core_mips_set_irq(core, irq);
1253 }
1254
1255 static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq)
1256 {
1257 int i;
1258 static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
1259 - printk(KERN_INFO KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
1260 + printk(KERN_DEBUG KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
1261 for (i = 0; i <= 6; i++)
1262 printk(" %s%s", irq_name[i], i == irq ? "*" : " ");
1263 printk("\n");
1264 @@ -171,7 +222,7 @@ u32 bcma_cpu_clock(struct bcma_drv_mips
1265 struct bcma_bus *bus = mcore->core->bus;
1266
1267 if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
1268 - return bcma_pmu_get_clockcpu(&bus->drv_cc);
1269 + return bcma_pmu_get_cpu_clock(&bus->drv_cc);
1270
1271 bcma_err(bus, "No PMU available, need this to get the cpu clock\n");
1272 return 0;
1273 @@ -181,85 +232,143 @@ EXPORT_SYMBOL(bcma_cpu_clock);
1274 static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
1275 {
1276 struct bcma_bus *bus = mcore->core->bus;
1277 + struct bcma_drv_cc *cc = &bus->drv_cc;
1278 + struct bcma_pflash *pflash = &cc->pflash;
1279
1280 - switch (bus->drv_cc.capabilities & BCMA_CC_CAP_FLASHT) {
1281 + switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
1282 case BCMA_CC_FLASHT_STSER:
1283 case BCMA_CC_FLASHT_ATSER:
1284 bcma_debug(bus, "Found serial flash\n");
1285 - bcma_sflash_init(&bus->drv_cc);
1286 + bcma_sflash_init(cc);
1287 break;
1288 case BCMA_CC_FLASHT_PARA:
1289 bcma_debug(bus, "Found parallel flash\n");
1290 - bus->drv_cc.pflash.window = 0x1c000000;
1291 - bus->drv_cc.pflash.window_size = 0x02000000;
1292 + pflash->present = true;
1293 + pflash->window = BCMA_SOC_FLASH2;
1294 + pflash->window_size = BCMA_SOC_FLASH2_SZ;
1295
1296 - if ((bcma_read32(bus->drv_cc.core, BCMA_CC_FLASH_CFG) &
1297 + if ((bcma_read32(cc->core, BCMA_CC_FLASH_CFG) &
1298 BCMA_CC_FLASH_CFG_DS) == 0)
1299 - bus->drv_cc.pflash.buswidth = 1;
1300 + pflash->buswidth = 1;
1301 else
1302 - bus->drv_cc.pflash.buswidth = 2;
1303 + pflash->buswidth = 2;
1304 +
1305 + bcma_pflash_data.width = pflash->buswidth;
1306 + bcma_pflash_resource.start = pflash->window;
1307 + bcma_pflash_resource.end = pflash->window + pflash->window_size;
1308 +
1309 break;
1310 default:
1311 bcma_err(bus, "Flash type not supported\n");
1312 }
1313
1314 - if (bus->drv_cc.core->id.rev == 38 ||
1315 + if (cc->core->id.rev == 38 ||
1316 bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
1317 - if (bus->drv_cc.capabilities & BCMA_CC_CAP_NFLASH) {
1318 + if (cc->capabilities & BCMA_CC_CAP_NFLASH) {
1319 bcma_debug(bus, "Found NAND flash\n");
1320 - bcma_nflash_init(&bus->drv_cc);
1321 + bcma_nflash_init(cc);
1322 }
1323 }
1324 }
1325
1326 +void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
1327 +{
1328 + struct bcma_bus *bus = mcore->core->bus;
1329 +
1330 + if (mcore->early_setup_done)
1331 + return;
1332 +
1333 + bcma_chipco_serial_init(&bus->drv_cc);
1334 + bcma_core_mips_flash_detect(mcore);
1335 +
1336 + mcore->early_setup_done = true;
1337 +}
1338 +
1339 +static void bcma_fix_i2s_irqflag(struct bcma_bus *bus)
1340 +{
1341 + struct bcma_device *cpu, *pcie, *i2s;
1342 +
1343 + /* Fixup the interrupts in 4716/4748 for i2s core (2010 Broadcom SDK)
1344 + * (IRQ flags > 7 are ignored when setting the interrupt masks)
1345 + */
1346 + if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4716 &&
1347 + bus->chipinfo.id != BCMA_CHIP_ID_BCM4748)
1348 + return;
1349 +
1350 + cpu = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
1351 + pcie = bcma_find_core(bus, BCMA_CORE_PCIE);
1352 + i2s = bcma_find_core(bus, BCMA_CORE_I2S);
1353 + if (cpu && pcie && i2s &&
1354 + bcma_aread32(cpu, BCMA_MIPS_OOBSELINA74) == 0x08060504 &&
1355 + bcma_aread32(pcie, BCMA_MIPS_OOBSELINA74) == 0x08060504 &&
1356 + bcma_aread32(i2s, BCMA_MIPS_OOBSELOUTA30) == 0x88) {
1357 + bcma_awrite32(cpu, BCMA_MIPS_OOBSELINA74, 0x07060504);
1358 + bcma_awrite32(pcie, BCMA_MIPS_OOBSELINA74, 0x07060504);
1359 + bcma_awrite32(i2s, BCMA_MIPS_OOBSELOUTA30, 0x87);
1360 + bcma_debug(bus,
1361 + "Moved i2s interrupt to oob line 7 instead of 8\n");
1362 + }
1363 +}
1364 +
1365 void bcma_core_mips_init(struct bcma_drv_mips *mcore)
1366 {
1367 struct bcma_bus *bus;
1368 struct bcma_device *core;
1369 bus = mcore->core->bus;
1370
1371 - bcma_info(bus, "Initializing MIPS core...\n");
1372 + if (mcore->setup_done)
1373 + return;
1374
1375 - if (!mcore->setup_done)
1376 - mcore->assigned_irqs = 1;
1377 + bcma_debug(bus, "Initializing MIPS core...\n");
1378
1379 - /* Assign IRQs to all cores on the bus */
1380 - list_for_each_entry(core, &bus->cores, list) {
1381 - int mips_irq;
1382 - if (core->irq)
1383 - continue;
1384 -
1385 - mips_irq = bcma_core_mips_irq(core);
1386 - if (mips_irq > 4)
1387 - core->irq = 0;
1388 - else
1389 - core->irq = mips_irq + 2;
1390 - if (core->irq > 5)
1391 - continue;
1392 - switch (core->id.id) {
1393 - case BCMA_CORE_PCI:
1394 - case BCMA_CORE_PCIE:
1395 - case BCMA_CORE_ETHERNET:
1396 - case BCMA_CORE_ETHERNET_GBIT:
1397 - case BCMA_CORE_MAC_GBIT:
1398 - case BCMA_CORE_80211:
1399 - case BCMA_CORE_USB20_HOST:
1400 - /* These devices get their own IRQ line if available,
1401 - * the rest goes on IRQ0
1402 - */
1403 - if (mcore->assigned_irqs <= 4)
1404 - bcma_core_mips_set_irq(core,
1405 - mcore->assigned_irqs++);
1406 - break;
1407 + bcma_core_mips_early_init(mcore);
1408 +
1409 + bcma_fix_i2s_irqflag(bus);
1410 +
1411 + switch (bus->chipinfo.id) {
1412 + case BCMA_CHIP_ID_BCM4716:
1413 + case BCMA_CHIP_ID_BCM4748:
1414 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
1415 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
1416 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
1417 + bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_PCIE, 0);
1418 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
1419 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
1420 + break;
1421 + case BCMA_CHIP_ID_BCM5356:
1422 + case BCMA_CHIP_ID_BCM47162:
1423 + case BCMA_CHIP_ID_BCM53572:
1424 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
1425 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
1426 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
1427 + break;
1428 + case BCMA_CHIP_ID_BCM5357:
1429 + case BCMA_CHIP_ID_BCM4749:
1430 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
1431 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
1432 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
1433 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
1434 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
1435 + break;
1436 + case BCMA_CHIP_ID_BCM4706:
1437 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_PCIE, 0);
1438 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_4706_MAC_GBIT,
1439 + 0);
1440 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_PCIE, 1);
1441 + bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_USB20_HOST, 0);
1442 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_4706_CHIPCOMMON,
1443 + 0);
1444 + break;
1445 + default:
1446 + list_for_each_entry(core, &bus->cores, list) {
1447 + core->irq = bcma_core_irq(core);
1448 }
1449 + bcma_err(bus,
1450 + "Unknown device (0x%x) found, can not configure IRQs\n",
1451 + bus->chipinfo.id);
1452 }
1453 - bcma_info(bus, "IRQ reconfiguration done\n");
1454 + bcma_debug(bus, "IRQ reconfiguration done\n");
1455 bcma_core_mips_dump_irq(bus);
1456
1457 - if (mcore->setup_done)
1458 - return;
1459 -
1460 - bcma_chipco_serial_init(&bus->drv_cc);
1461 - bcma_core_mips_flash_detect(mcore);
1462 mcore->setup_done = true;
1463 }
1464 --- a/drivers/bcma/driver_pci_host.c
1465 +++ b/drivers/bcma/driver_pci_host.c
1466 @@ -35,11 +35,6 @@ bool __devinit bcma_core_pci_is_in_hostm
1467 chipid_top != 0x5300)
1468 return false;
1469
1470 - if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
1471 - bcma_info(bus, "This PCI core is disabled and not working\n");
1472 - return false;
1473 - }
1474 -
1475 bcma_core_enable(pc->core, 0);
1476
1477 return !mips_busprobe32(tmp, pc->core->io_addr);
1478 @@ -99,19 +94,19 @@ static int bcma_extpci_read_config(struc
1479 if (dev == 0) {
1480 /* we support only two functions on device 0 */
1481 if (func > 1)
1482 - return -EINVAL;
1483 + goto out;
1484
1485 /* accesses to config registers with offsets >= 256
1486 * requires indirect access.
1487 */
1488 if (off >= PCI_CONFIG_SPACE_SIZE) {
1489 addr = (func << 12);
1490 - addr |= (off & 0x0FFF);
1491 + addr |= (off & 0x0FFC);
1492 val = bcma_pcie_read_config(pc, addr);
1493 } else {
1494 addr = BCMA_CORE_PCI_PCICFG0;
1495 addr |= (func << 8);
1496 - addr |= (off & 0xfc);
1497 + addr |= (off & 0xFC);
1498 val = pcicore_read32(pc, addr);
1499 }
1500 } else {
1501 @@ -124,11 +119,9 @@ static int bcma_extpci_read_config(struc
1502 goto out;
1503
1504 if (mips_busprobe32(val, mmio)) {
1505 - val = 0xffffffff;
1506 + val = 0xFFFFFFFF;
1507 goto unmap;
1508 }
1509 -
1510 - val = readl(mmio);
1511 }
1512 val >>= (8 * (off & 3));
1513
1514 @@ -156,7 +149,7 @@ static int bcma_extpci_write_config(stru
1515 const void *buf, int len)
1516 {
1517 int err = -EINVAL;
1518 - u32 addr = 0, val = 0;
1519 + u32 addr, val;
1520 void __iomem *mmio = 0;
1521 u16 chipid = pc->core->bus->chipinfo.id;
1522
1523 @@ -164,16 +157,22 @@ static int bcma_extpci_write_config(stru
1524 if (unlikely(len != 1 && len != 2 && len != 4))
1525 goto out;
1526 if (dev == 0) {
1527 + /* we support only two functions on device 0 */
1528 + if (func > 1)
1529 + goto out;
1530 +
1531 /* accesses to config registers with offsets >= 256
1532 * requires indirect access.
1533 */
1534 - if (off < PCI_CONFIG_SPACE_SIZE) {
1535 - addr = pc->core->addr + BCMA_CORE_PCI_PCICFG0;
1536 + if (off >= PCI_CONFIG_SPACE_SIZE) {
1537 + addr = (func << 12);
1538 + addr |= (off & 0x0FFC);
1539 + val = bcma_pcie_read_config(pc, addr);
1540 + } else {
1541 + addr = BCMA_CORE_PCI_PCICFG0;
1542 addr |= (func << 8);
1543 - addr |= (off & 0xfc);
1544 - mmio = ioremap_nocache(addr, sizeof(val));
1545 - if (!mmio)
1546 - goto out;
1547 + addr |= (off & 0xFC);
1548 + val = pcicore_read32(pc, addr);
1549 }
1550 } else {
1551 addr = bcma_get_cfgspace_addr(pc, dev, func, off);
1552 @@ -185,19 +184,17 @@ static int bcma_extpci_write_config(stru
1553 goto out;
1554
1555 if (mips_busprobe32(val, mmio)) {
1556 - val = 0xffffffff;
1557 + val = 0xFFFFFFFF;
1558 goto unmap;
1559 }
1560 }
1561
1562 switch (len) {
1563 case 1:
1564 - val = readl(mmio);
1565 val &= ~(0xFF << (8 * (off & 3)));
1566 val |= *((const u8 *)buf) << (8 * (off & 3));
1567 break;
1568 case 2:
1569 - val = readl(mmio);
1570 val &= ~(0xFFFF << (8 * (off & 3)));
1571 val |= *((const u16 *)buf) << (8 * (off & 3));
1572 break;
1573 @@ -205,13 +202,14 @@ static int bcma_extpci_write_config(stru
1574 val = *((const u32 *)buf);
1575 break;
1576 }
1577 - if (dev == 0 && !addr) {
1578 + if (dev == 0) {
1579 /* accesses to config registers with offsets >= 256
1580 * requires indirect access.
1581 */
1582 - addr = (func << 12);
1583 - addr |= (off & 0x0FFF);
1584 - bcma_pcie_write_config(pc, addr, val);
1585 + if (off >= PCI_CONFIG_SPACE_SIZE)
1586 + bcma_pcie_write_config(pc, addr, val);
1587 + else
1588 + pcicore_write32(pc, addr, val);
1589 } else {
1590 writel(val, mmio);
1591
1592 @@ -282,7 +280,7 @@ static u8 __devinit bcma_find_pci_capabi
1593 /* check for Header type 0 */
1594 bcma_extpci_read_config(pc, dev, func, PCI_HEADER_TYPE, &byte_val,
1595 sizeof(u8));
1596 - if ((byte_val & 0x7f) != PCI_HEADER_TYPE_NORMAL)
1597 + if ((byte_val & 0x7F) != PCI_HEADER_TYPE_NORMAL)
1598 return cap_ptr;
1599
1600 /* check if the capability pointer field exists */
1601 @@ -396,12 +394,19 @@ void __devinit bcma_core_pci_hostmode_in
1602
1603 bcma_info(bus, "PCIEcore in host mode found\n");
1604
1605 + if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
1606 + bcma_info(bus, "This PCIE core is disabled and not working\n");
1607 + return;
1608 + }
1609 +
1610 pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL);
1611 if (!pc_host) {
1612 bcma_err(bus, "can not allocate memory");
1613 return;
1614 }
1615
1616 + spin_lock_init(&pc_host->cfgspace_lock);
1617 +
1618 pc->host_controller = pc_host;
1619 pc_host->pci_controller.io_resource = &pc_host->io_resource;
1620 pc_host->pci_controller.mem_resource = &pc_host->mem_resource;
1621 @@ -427,7 +432,7 @@ void __devinit bcma_core_pci_hostmode_in
1622 /* Reset RC */
1623 usleep_range(3000, 5000);
1624 pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE);
1625 - usleep_range(1000, 2000);
1626 + msleep(50);
1627 pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST |
1628 BCMA_CORE_PCI_CTL_RST_OE);
1629
1630 @@ -452,6 +457,8 @@ void __devinit bcma_core_pci_hostmode_in
1631 pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
1632 pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
1633 BCMA_SOC_PCI_MEM_SZ - 1;
1634 + pc_host->io_resource.start = 0x100;
1635 + pc_host->io_resource.end = 0x47F;
1636 pci_membase_1G = BCMA_SOC_PCIE_DMA_H32;
1637 pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
1638 tmp | BCMA_SOC_PCI_MEM);
1639 @@ -459,6 +466,8 @@ void __devinit bcma_core_pci_hostmode_in
1640 pc_host->mem_resource.start = BCMA_SOC_PCI1_MEM;
1641 pc_host->mem_resource.end = BCMA_SOC_PCI1_MEM +
1642 BCMA_SOC_PCI_MEM_SZ - 1;
1643 + pc_host->io_resource.start = 0x480;
1644 + pc_host->io_resource.end = 0x7FF;
1645 pci_membase_1G = BCMA_SOC_PCIE1_DMA_H32;
1646 pc_host->host_cfg_addr = BCMA_SOC_PCI1_CFG;
1647 pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
1648 @@ -485,6 +494,17 @@ void __devinit bcma_core_pci_hostmode_in
1649
1650 bcma_core_pci_enable_crs(pc);
1651
1652 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706 ||
1653 + bus->chipinfo.id == BCMA_CHIP_ID_BCM4716) {
1654 + u16 val16;
1655 + bcma_extpci_read_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL,
1656 + &val16, sizeof(val16));
1657 + val16 |= (2 << 5); /* Max payload size of 512 */
1658 + val16 |= (2 << 12); /* MRRS 512 */
1659 + bcma_extpci_write_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL,
1660 + &val16, sizeof(val16));
1661 + }
1662 +
1663 /* Enable PCI bridge BAR0 memory & master access */
1664 tmp = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
1665 bcma_extpci_write_config(pc, 0, 0, PCI_COMMAND, &tmp, sizeof(tmp));
1666 @@ -534,7 +554,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_
1667 static void bcma_core_pci_fixup_addresses(struct pci_dev *dev)
1668 {
1669 struct resource *res;
1670 - int pos;
1671 + int pos, err;
1672
1673 if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
1674 /* This is not a device on the PCI-core bridge. */
1675 @@ -547,8 +567,12 @@ static void bcma_core_pci_fixup_addresse
1676
1677 for (pos = 0; pos < 6; pos++) {
1678 res = &dev->resource[pos];
1679 - if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM))
1680 - pci_assign_resource(dev, pos);
1681 + if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM)) {
1682 + err = pci_assign_resource(dev, pos);
1683 + if (err)
1684 + pr_err("PCI: Problem fixing up the addresses on %s\n",
1685 + pci_name(dev));
1686 + }
1687 }
1688 }
1689 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_addresses);
1690 @@ -569,7 +593,7 @@ int bcma_core_pci_plat_dev_init(struct p
1691 pr_info("PCI: Fixing up device %s\n", pci_name(dev));
1692
1693 /* Fix up interrupt lines */
1694 - dev->irq = bcma_core_mips_irq(pc_host->pdev->core) + 2;
1695 + dev->irq = bcma_core_irq(pc_host->pdev->core);
1696 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
1697
1698 return 0;
1699 @@ -588,6 +612,6 @@ int bcma_core_pci_pcibios_map_irq(const
1700
1701 pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
1702 pci_ops);
1703 - return bcma_core_mips_irq(pc_host->pdev->core) + 2;
1704 + return bcma_core_irq(pc_host->pdev->core);
1705 }
1706 EXPORT_SYMBOL(bcma_core_pci_pcibios_map_irq);
1707 --- a/drivers/bcma/host_pci.c
1708 +++ b/drivers/bcma/host_pci.c
1709 @@ -238,7 +238,7 @@ static void __devexit bcma_host_pci_remo
1710 pci_set_drvdata(dev, NULL);
1711 }
1712
1713 -#ifdef CONFIG_PM
1714 +#ifdef CONFIG_PM_SLEEP
1715 static int bcma_host_pci_suspend(struct device *dev)
1716 {
1717 struct pci_dev *pdev = to_pci_dev(dev);
1718 @@ -261,11 +261,11 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bc
1719 bcma_host_pci_resume);
1720 #define BCMA_PM_OPS (&bcma_pm_ops)
1721
1722 -#else /* CONFIG_PM */
1723 +#else /* CONFIG_PM_SLEEP */
1724
1725 #define BCMA_PM_OPS NULL
1726
1727 -#endif /* CONFIG_PM */
1728 +#endif /* CONFIG_PM_SLEEP */
1729
1730 static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
1731 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
1732 @@ -275,6 +275,7 @@ static DEFINE_PCI_DEVICE_TABLE(bcma_pci_
1733 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
1734 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
1735 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
1736 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) },
1737 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
1738 { 0, },
1739 };
1740 --- a/drivers/bcma/main.c
1741 +++ b/drivers/bcma/main.c
1742 @@ -81,6 +81,37 @@ struct bcma_device *bcma_find_core(struc
1743 }
1744 EXPORT_SYMBOL_GPL(bcma_find_core);
1745
1746 +struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
1747 + u8 unit)
1748 +{
1749 + struct bcma_device *core;
1750 +
1751 + list_for_each_entry(core, &bus->cores, list) {
1752 + if (core->id.id == coreid && core->core_unit == unit)
1753 + return core;
1754 + }
1755 + return NULL;
1756 +}
1757 +
1758 +bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
1759 + int timeout)
1760 +{
1761 + unsigned long deadline = jiffies + timeout;
1762 + u32 val;
1763 +
1764 + do {
1765 + val = bcma_read32(core, reg);
1766 + if ((val & mask) == value)
1767 + return true;
1768 + cpu_relax();
1769 + udelay(10);
1770 + } while (!time_after_eq(jiffies, deadline));
1771 +
1772 + bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg);
1773 +
1774 + return false;
1775 +}
1776 +
1777 static void bcma_release_core_dev(struct device *dev)
1778 {
1779 struct bcma_device *core = container_of(dev, struct bcma_device, dev);
1780 @@ -108,6 +139,11 @@ static int bcma_register_cores(struct bc
1781 continue;
1782 }
1783
1784 + /* Only first GMAC core on BCM4706 is connected and working */
1785 + if (core->id.id == BCMA_CORE_4706_MAC_GBIT &&
1786 + core->core_unit > 0)
1787 + continue;
1788 +
1789 core->dev.release = bcma_release_core_dev;
1790 core->dev.bus = &bcma_bus_type;
1791 dev_set_name(&core->dev, "bcma%d:%d", bus->num, dev_id);
1792 @@ -137,6 +173,14 @@ static int bcma_register_cores(struct bc
1793 dev_id++;
1794 }
1795
1796 +#ifdef CONFIG_BCMA_DRIVER_MIPS
1797 + if (bus->drv_cc.pflash.present) {
1798 + err = platform_device_register(&bcma_pflash_dev);
1799 + if (err)
1800 + bcma_err(bus, "Error registering parallel flash\n");
1801 + }
1802 +#endif
1803 +
1804 #ifdef CONFIG_BCMA_SFLASH
1805 if (bus->drv_cc.sflash.present) {
1806 err = platform_device_register(&bcma_sflash_dev);
1807 @@ -152,6 +196,17 @@ static int bcma_register_cores(struct bc
1808 bcma_err(bus, "Error registering NAND flash\n");
1809 }
1810 #endif
1811 + err = bcma_gpio_init(&bus->drv_cc);
1812 + if (err == -ENOTSUPP)
1813 + bcma_debug(bus, "GPIO driver not activated\n");
1814 + else if (err)
1815 + bcma_err(bus, "Error registering GPIO driver: %i\n", err);
1816 +
1817 + if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
1818 + err = bcma_chipco_watchdog_register(&bus->drv_cc);
1819 + if (err)
1820 + bcma_err(bus, "Error registering watchdog driver\n");
1821 + }
1822
1823 return 0;
1824 }
1825 @@ -165,6 +220,8 @@ static void bcma_unregister_cores(struct
1826 if (core->dev_registered)
1827 device_unregister(&core->dev);
1828 }
1829 + if (bus->hosttype == BCMA_HOSTTYPE_SOC)
1830 + platform_device_unregister(bus->drv_cc.watchdog);
1831 }
1832
1833 int __devinit bcma_bus_register(struct bcma_bus *bus)
1834 @@ -183,6 +240,20 @@ int __devinit bcma_bus_register(struct b
1835 return -1;
1836 }
1837
1838 + /* Early init CC core */
1839 + core = bcma_find_core(bus, bcma_cc_core_id(bus));
1840 + if (core) {
1841 + bus->drv_cc.core = core;
1842 + bcma_core_chipcommon_early_init(&bus->drv_cc);
1843 + }
1844 +
1845 + /* Try to get SPROM */
1846 + err = bcma_sprom_get(bus);
1847 + if (err == -ENOENT) {
1848 + bcma_err(bus, "No SPROM available\n");
1849 + } else if (err)
1850 + bcma_err(bus, "Failed to get SPROM: %d\n", err);
1851 +
1852 /* Init CC core */
1853 core = bcma_find_core(bus, bcma_cc_core_id(bus));
1854 if (core) {
1855 @@ -198,10 +269,17 @@ int __devinit bcma_bus_register(struct b
1856 }
1857
1858 /* Init PCIE core */
1859 - core = bcma_find_core(bus, BCMA_CORE_PCIE);
1860 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 0);
1861 + if (core) {
1862 + bus->drv_pci[0].core = core;
1863 + bcma_core_pci_init(&bus->drv_pci[0]);
1864 + }
1865 +
1866 + /* Init PCIE core */
1867 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 1);
1868 if (core) {
1869 - bus->drv_pci.core = core;
1870 - bcma_core_pci_init(&bus->drv_pci);
1871 + bus->drv_pci[1].core = core;
1872 + bcma_core_pci_init(&bus->drv_pci[1]);
1873 }
1874
1875 /* Init GBIT MAC COMMON core */
1876 @@ -211,13 +289,6 @@ int __devinit bcma_bus_register(struct b
1877 bcma_core_gmac_cmn_init(&bus->drv_gmac_cmn);
1878 }
1879
1880 - /* Try to get SPROM */
1881 - err = bcma_sprom_get(bus);
1882 - if (err == -ENOENT) {
1883 - bcma_err(bus, "No SPROM available\n");
1884 - } else if (err)
1885 - bcma_err(bus, "Failed to get SPROM: %d\n", err);
1886 -
1887 /* Register found cores */
1888 bcma_register_cores(bus);
1889
1890 @@ -229,6 +300,13 @@ int __devinit bcma_bus_register(struct b
1891 void bcma_bus_unregister(struct bcma_bus *bus)
1892 {
1893 struct bcma_device *cores[3];
1894 + int err;
1895 +
1896 + err = bcma_gpio_unregister(&bus->drv_cc);
1897 + if (err == -EBUSY)
1898 + bcma_err(bus, "Some GPIOs are still in use.\n");
1899 + else if (err)
1900 + bcma_err(bus, "Can not unregister GPIO driver: %i\n", err);
1901
1902 cores[0] = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
1903 cores[1] = bcma_find_core(bus, BCMA_CORE_PCIE);
1904 @@ -275,18 +353,18 @@ int __init bcma_bus_early_register(struc
1905 return -1;
1906 }
1907
1908 - /* Init CC core */
1909 + /* Early init CC core */
1910 core = bcma_find_core(bus, bcma_cc_core_id(bus));
1911 if (core) {
1912 bus->drv_cc.core = core;
1913 - bcma_core_chipcommon_init(&bus->drv_cc);
1914 + bcma_core_chipcommon_early_init(&bus->drv_cc);
1915 }
1916
1917 - /* Init MIPS core */
1918 + /* Early init MIPS core */
1919 core = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
1920 if (core) {
1921 bus->drv_mips.core = core;
1922 - bcma_core_mips_init(&bus->drv_mips);
1923 + bcma_core_mips_early_init(&bus->drv_mips);
1924 }
1925
1926 bcma_info(bus, "Early bus registered\n");
1927 --- a/drivers/bcma/scan.c
1928 +++ b/drivers/bcma/scan.c
1929 @@ -84,6 +84,8 @@ static const struct bcma_device_id_name
1930 { BCMA_CORE_I2S, "I2S" },
1931 { BCMA_CORE_SDR_DDR1_MEM_CTL, "SDR/DDR1 Memory Controller" },
1932 { BCMA_CORE_SHIM, "SHIM" },
1933 + { BCMA_CORE_PCIE2, "PCIe Gen2" },
1934 + { BCMA_CORE_ARM_CR4, "ARM CR4" },
1935 { BCMA_CORE_DEFAULT, "Default" },
1936 };
1937
1938 @@ -137,19 +139,19 @@ static void bcma_scan_switch_core(struct
1939 addr);
1940 }
1941
1942 -static u32 bcma_erom_get_ent(struct bcma_bus *bus, u32 **eromptr)
1943 +static u32 bcma_erom_get_ent(struct bcma_bus *bus, u32 __iomem **eromptr)
1944 {
1945 u32 ent = readl(*eromptr);
1946 (*eromptr)++;
1947 return ent;
1948 }
1949
1950 -static void bcma_erom_push_ent(u32 **eromptr)
1951 +static void bcma_erom_push_ent(u32 __iomem **eromptr)
1952 {
1953 (*eromptr)--;
1954 }
1955
1956 -static s32 bcma_erom_get_ci(struct bcma_bus *bus, u32 **eromptr)
1957 +static s32 bcma_erom_get_ci(struct bcma_bus *bus, u32 __iomem **eromptr)
1958 {
1959 u32 ent = bcma_erom_get_ent(bus, eromptr);
1960 if (!(ent & SCAN_ER_VALID))
1961 @@ -159,14 +161,14 @@ static s32 bcma_erom_get_ci(struct bcma_
1962 return ent;
1963 }
1964
1965 -static bool bcma_erom_is_end(struct bcma_bus *bus, u32 **eromptr)
1966 +static bool bcma_erom_is_end(struct bcma_bus *bus, u32 __iomem **eromptr)
1967 {
1968 u32 ent = bcma_erom_get_ent(bus, eromptr);
1969 bcma_erom_push_ent(eromptr);
1970 return (ent == (SCAN_ER_TAG_END | SCAN_ER_VALID));
1971 }
1972
1973 -static bool bcma_erom_is_bridge(struct bcma_bus *bus, u32 **eromptr)
1974 +static bool bcma_erom_is_bridge(struct bcma_bus *bus, u32 __iomem **eromptr)
1975 {
1976 u32 ent = bcma_erom_get_ent(bus, eromptr);
1977 bcma_erom_push_ent(eromptr);
1978 @@ -175,7 +177,7 @@ static bool bcma_erom_is_bridge(struct b
1979 ((ent & SCAN_ADDR_TYPE) == SCAN_ADDR_TYPE_BRIDGE));
1980 }
1981
1982 -static void bcma_erom_skip_component(struct bcma_bus *bus, u32 **eromptr)
1983 +static void bcma_erom_skip_component(struct bcma_bus *bus, u32 __iomem **eromptr)
1984 {
1985 u32 ent;
1986 while (1) {
1987 @@ -189,7 +191,7 @@ static void bcma_erom_skip_component(str
1988 bcma_erom_push_ent(eromptr);
1989 }
1990
1991 -static s32 bcma_erom_get_mst_port(struct bcma_bus *bus, u32 **eromptr)
1992 +static s32 bcma_erom_get_mst_port(struct bcma_bus *bus, u32 __iomem **eromptr)
1993 {
1994 u32 ent = bcma_erom_get_ent(bus, eromptr);
1995 if (!(ent & SCAN_ER_VALID))
1996 @@ -199,7 +201,7 @@ static s32 bcma_erom_get_mst_port(struct
1997 return ent;
1998 }
1999
2000 -static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 **eromptr,
2001 +static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 __iomem **eromptr,
2002 u32 type, u8 port)
2003 {
2004 u32 addrl, addrh, sizel, sizeh = 0;
2005 --- a/drivers/bcma/sprom.c
2006 +++ b/drivers/bcma/sprom.c
2007 @@ -72,12 +72,12 @@ fail:
2008 * R/W ops.
2009 **************************************************/
2010
2011 -static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom)
2012 +static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom,
2013 + size_t words)
2014 {
2015 int i;
2016 - for (i = 0; i < SSB_SPROMSIZE_WORDS_R4; i++)
2017 - sprom[i] = bcma_read16(bus->drv_cc.core,
2018 - offset + (i * 2));
2019 + for (i = 0; i < words; i++)
2020 + sprom[i] = bcma_read16(bus->drv_cc.core, offset + (i * 2));
2021 }
2022
2023 /**************************************************
2024 @@ -124,29 +124,29 @@ static inline u8 bcma_crc8(u8 crc, u8 da
2025 return t[crc ^ data];
2026 }
2027
2028 -static u8 bcma_sprom_crc(const u16 *sprom)
2029 +static u8 bcma_sprom_crc(const u16 *sprom, size_t words)
2030 {
2031 int word;
2032 u8 crc = 0xFF;
2033
2034 - for (word = 0; word < SSB_SPROMSIZE_WORDS_R4 - 1; word++) {
2035 + for (word = 0; word < words - 1; word++) {
2036 crc = bcma_crc8(crc, sprom[word] & 0x00FF);
2037 crc = bcma_crc8(crc, (sprom[word] & 0xFF00) >> 8);
2038 }
2039 - crc = bcma_crc8(crc, sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & 0x00FF);
2040 + crc = bcma_crc8(crc, sprom[words - 1] & 0x00FF);
2041 crc ^= 0xFF;
2042
2043 return crc;
2044 }
2045
2046 -static int bcma_sprom_check_crc(const u16 *sprom)
2047 +static int bcma_sprom_check_crc(const u16 *sprom, size_t words)
2048 {
2049 u8 crc;
2050 u8 expected_crc;
2051 u16 tmp;
2052
2053 - crc = bcma_sprom_crc(sprom);
2054 - tmp = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_CRC;
2055 + crc = bcma_sprom_crc(sprom, words);
2056 + tmp = sprom[words - 1] & SSB_SPROM_REVISION_CRC;
2057 expected_crc = tmp >> SSB_SPROM_REVISION_CRC_SHIFT;
2058 if (crc != expected_crc)
2059 return -EPROTO;
2060 @@ -154,21 +154,25 @@ static int bcma_sprom_check_crc(const u1
2061 return 0;
2062 }
2063
2064 -static int bcma_sprom_valid(const u16 *sprom)
2065 +static int bcma_sprom_valid(struct bcma_bus *bus, const u16 *sprom,
2066 + size_t words)
2067 {
2068 u16 revision;
2069 int err;
2070
2071 - err = bcma_sprom_check_crc(sprom);
2072 + err = bcma_sprom_check_crc(sprom, words);
2073 if (err)
2074 return err;
2075
2076 - revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_REV;
2077 - if (revision != 8 && revision != 9) {
2078 + revision = sprom[words - 1] & SSB_SPROM_REVISION_REV;
2079 + if (revision != 8 && revision != 9 && revision != 10) {
2080 pr_err("Unsupported SPROM revision: %d\n", revision);
2081 return -ENOENT;
2082 }
2083
2084 + bus->sprom.revision = revision;
2085 + bcma_debug(bus, "Found SPROM revision %d\n", revision);
2086 +
2087 return 0;
2088 }
2089
2090 @@ -208,15 +212,13 @@ static void bcma_sprom_extract_r8(struct
2091 BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
2092 ARRAY_SIZE(bus->sprom.core_pwr_info));
2093
2094 - bus->sprom.revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] &
2095 - SSB_SPROM_REVISION_REV;
2096 -
2097 for (i = 0; i < 3; i++) {
2098 v = sprom[SPOFF(SSB_SPROM8_IL0MAC) + i];
2099 *(((__be16 *)bus->sprom.il0mac) + i) = cpu_to_be16(v);
2100 }
2101
2102 SPEX(board_rev, SSB_SPROM8_BOARDREV, ~0, 0);
2103 + SPEX(board_type, SSB_SPROM1_SPID, ~0, 0);
2104
2105 SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01, SSB_SPROM4_TXPID2G0,
2106 SSB_SPROM4_TXPID2G0_SHIFT);
2107 @@ -501,7 +503,7 @@ static bool bcma_sprom_onchip_available(
2108 case BCMA_CHIP_ID_BCM4331:
2109 present = chip_status & BCMA_CC_CHIPST_4331_OTP_PRESENT;
2110 break;
2111 -
2112 + case BCMA_CHIP_ID_BCM43142:
2113 case BCMA_CHIP_ID_BCM43224:
2114 case BCMA_CHIP_ID_BCM43225:
2115 /* for these chips OTP is always available */
2116 @@ -549,7 +551,9 @@ int bcma_sprom_get(struct bcma_bus *bus)
2117 {
2118 u16 offset = BCMA_CC_SPROM;
2119 u16 *sprom;
2120 - int err = 0;
2121 + size_t sprom_sizes[] = { SSB_SPROMSIZE_WORDS_R4,
2122 + SSB_SPROMSIZE_WORDS_R10, };
2123 + int i, err = 0;
2124
2125 if (!bus->drv_cc.core)
2126 return -EOPNOTSUPP;
2127 @@ -578,29 +582,37 @@ int bcma_sprom_get(struct bcma_bus *bus)
2128 }
2129 }
2130
2131 - sprom = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
2132 - GFP_KERNEL);
2133 - if (!sprom)
2134 - return -ENOMEM;
2135 -
2136 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
2137 bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
2138 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, false);
2139
2140 bcma_debug(bus, "SPROM offset 0x%x\n", offset);
2141 - bcma_sprom_read(bus, offset, sprom);
2142 + for (i = 0; i < ARRAY_SIZE(sprom_sizes); i++) {
2143 + size_t words = sprom_sizes[i];
2144 +
2145 + sprom = kcalloc(words, sizeof(u16), GFP_KERNEL);
2146 + if (!sprom)
2147 + return -ENOMEM;
2148 +
2149 + bcma_sprom_read(bus, offset, sprom, words);
2150 + err = bcma_sprom_valid(bus, sprom, words);
2151 + if (!err)
2152 + break;
2153 +
2154 + kfree(sprom);
2155 + }
2156
2157 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
2158 bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
2159 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
2160
2161 - err = bcma_sprom_valid(sprom);
2162 - if (err)
2163 - goto out;
2164 -
2165 - bcma_sprom_extract_r8(bus, sprom);
2166 + if (err) {
2167 + bcma_warn(bus, "Invalid SPROM read from the PCIe card, trying to use fallback SPROM\n");
2168 + err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
2169 + } else {
2170 + bcma_sprom_extract_r8(bus, sprom);
2171 + kfree(sprom);
2172 + }
2173
2174 -out:
2175 - kfree(sprom);
2176 return err;
2177 }
2178 --- a/include/linux/bcma/bcma.h
2179 +++ b/include/linux/bcma/bcma.h
2180 @@ -134,12 +134,17 @@ struct bcma_host_ops {
2181 #define BCMA_CORE_I2S 0x834
2182 #define BCMA_CORE_SDR_DDR1_MEM_CTL 0x835 /* SDR/DDR1 memory controller core */
2183 #define BCMA_CORE_SHIM 0x837 /* SHIM component in ubus/6362 */
2184 +#define BCMA_CORE_PHY_AC 0x83B
2185 +#define BCMA_CORE_PCIE2 0x83C /* PCI Express Gen2 */
2186 +#define BCMA_CORE_USB30_DEV 0x83D
2187 +#define BCMA_CORE_ARM_CR4 0x83E
2188 #define BCMA_CORE_DEFAULT 0xFFF
2189
2190 #define BCMA_MAX_NR_CORES 16
2191
2192 /* Chip IDs of PCIe devices */
2193 #define BCMA_CHIP_ID_BCM4313 0x4313
2194 +#define BCMA_CHIP_ID_BCM43142 43142
2195 #define BCMA_CHIP_ID_BCM43224 43224
2196 #define BCMA_PKG_ID_BCM43224_FAB_CSM 0x8
2197 #define BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa
2198 @@ -157,6 +162,7 @@ struct bcma_host_ops {
2199
2200 /* Chip IDs of SoCs */
2201 #define BCMA_CHIP_ID_BCM4706 0x5300
2202 +#define BCMA_PKG_ID_BCM4706L 1
2203 #define BCMA_CHIP_ID_BCM4716 0x4716
2204 #define BCMA_PKG_ID_BCM4716 8
2205 #define BCMA_PKG_ID_BCM4717 9
2206 @@ -166,7 +172,65 @@ struct bcma_host_ops {
2207 #define BCMA_CHIP_ID_BCM4749 0x4749
2208 #define BCMA_CHIP_ID_BCM5356 0x5356
2209 #define BCMA_CHIP_ID_BCM5357 0x5357
2210 +#define BCMA_PKG_ID_BCM5358 9
2211 +#define BCMA_PKG_ID_BCM47186 10
2212 +#define BCMA_PKG_ID_BCM5357 11
2213 #define BCMA_CHIP_ID_BCM53572 53572
2214 +#define BCMA_PKG_ID_BCM47188 9
2215 +
2216 +/* Board types (on PCI usually equals to the subsystem dev id) */
2217 +/* BCM4313 */
2218 +#define BCMA_BOARD_TYPE_BCM94313BU 0X050F
2219 +#define BCMA_BOARD_TYPE_BCM94313HM 0X0510
2220 +#define BCMA_BOARD_TYPE_BCM94313EPA 0X0511
2221 +#define BCMA_BOARD_TYPE_BCM94313HMG 0X051C
2222 +/* BCM4716 */
2223 +#define BCMA_BOARD_TYPE_BCM94716NR2 0X04CD
2224 +/* BCM43224 */
2225 +#define BCMA_BOARD_TYPE_BCM943224X21 0X056E
2226 +#define BCMA_BOARD_TYPE_BCM943224X21_FCC 0X00D1
2227 +#define BCMA_BOARD_TYPE_BCM943224X21B 0X00E9
2228 +#define BCMA_BOARD_TYPE_BCM943224M93 0X008B
2229 +#define BCMA_BOARD_TYPE_BCM943224M93A 0X0090
2230 +#define BCMA_BOARD_TYPE_BCM943224X16 0X0093
2231 +#define BCMA_BOARD_TYPE_BCM94322X9 0X008D
2232 +#define BCMA_BOARD_TYPE_BCM94322M35E 0X008E
2233 +/* BCM43228 */
2234 +#define BCMA_BOARD_TYPE_BCM943228BU8 0X0540
2235 +#define BCMA_BOARD_TYPE_BCM943228BU9 0X0541
2236 +#define BCMA_BOARD_TYPE_BCM943228BU 0X0542
2237 +#define BCMA_BOARD_TYPE_BCM943227HM4L 0X0543
2238 +#define BCMA_BOARD_TYPE_BCM943227HMB 0X0544
2239 +#define BCMA_BOARD_TYPE_BCM943228HM4L 0X0545
2240 +#define BCMA_BOARD_TYPE_BCM943228SD 0X0573
2241 +/* BCM4331 */
2242 +#define BCMA_BOARD_TYPE_BCM94331X19 0X00D6
2243 +#define BCMA_BOARD_TYPE_BCM94331X28 0X00E4
2244 +#define BCMA_BOARD_TYPE_BCM94331X28B 0X010E
2245 +#define BCMA_BOARD_TYPE_BCM94331PCIEBT3AX 0X00E4
2246 +#define BCMA_BOARD_TYPE_BCM94331X12_2G 0X00EC
2247 +#define BCMA_BOARD_TYPE_BCM94331X12_5G 0X00ED
2248 +#define BCMA_BOARD_TYPE_BCM94331X29B 0X00EF
2249 +#define BCMA_BOARD_TYPE_BCM94331CSAX 0X00EF
2250 +#define BCMA_BOARD_TYPE_BCM94331X19C 0X00F5
2251 +#define BCMA_BOARD_TYPE_BCM94331X33 0X00F4
2252 +#define BCMA_BOARD_TYPE_BCM94331BU 0X0523
2253 +#define BCMA_BOARD_TYPE_BCM94331S9BU 0X0524
2254 +#define BCMA_BOARD_TYPE_BCM94331MC 0X0525
2255 +#define BCMA_BOARD_TYPE_BCM94331MCI 0X0526
2256 +#define BCMA_BOARD_TYPE_BCM94331PCIEBT4 0X0527
2257 +#define BCMA_BOARD_TYPE_BCM94331HM 0X0574
2258 +#define BCMA_BOARD_TYPE_BCM94331PCIEDUAL 0X059B
2259 +#define BCMA_BOARD_TYPE_BCM94331MCH5 0X05A9
2260 +#define BCMA_BOARD_TYPE_BCM94331CS 0X05C6
2261 +#define BCMA_BOARD_TYPE_BCM94331CD 0X05DA
2262 +/* BCM53572 */
2263 +#define BCMA_BOARD_TYPE_BCM953572BU 0X058D
2264 +#define BCMA_BOARD_TYPE_BCM953572NR2 0X058E
2265 +#define BCMA_BOARD_TYPE_BCM947188NR2 0X058F
2266 +#define BCMA_BOARD_TYPE_BCM953572SDRNR2 0X0590
2267 +/* BCM43142 */
2268 +#define BCMA_BOARD_TYPE_BCM943142HM 0X05E0
2269
2270 struct bcma_device {
2271 struct bcma_bus *bus;
2272 @@ -251,7 +315,7 @@ struct bcma_bus {
2273 u8 num;
2274
2275 struct bcma_drv_cc drv_cc;
2276 - struct bcma_drv_pci drv_pci;
2277 + struct bcma_drv_pci drv_pci[2];
2278 struct bcma_drv_mips drv_mips;
2279 struct bcma_drv_gmac_cmn drv_gmac_cmn;
2280
2281 @@ -345,6 +409,7 @@ extern void bcma_core_set_clockmode(stru
2282 enum bcma_clkmode clkmode);
2283 extern void bcma_core_pll_ctl(struct bcma_device *core, u32 req, u32 status,
2284 bool on);
2285 +extern u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset);
2286 #define BCMA_DMA_TRANSLATION_MASK 0xC0000000
2287 #define BCMA_DMA_TRANSLATION_NONE 0x00000000
2288 #define BCMA_DMA_TRANSLATION_DMA32_CMT 0x40000000 /* Client Mode Translation for 32-bit DMA */
2289 --- a/include/linux/bcma/bcma_driver_chipcommon.h
2290 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
2291 @@ -1,6 +1,9 @@
2292 #ifndef LINUX_BCMA_DRIVER_CC_H_
2293 #define LINUX_BCMA_DRIVER_CC_H_
2294
2295 +#include <linux/platform_device.h>
2296 +#include <linux/gpio.h>
2297 +
2298 /** ChipCommon core registers. **/
2299 #define BCMA_CC_ID 0x0000
2300 #define BCMA_CC_ID_ID 0x0000FFFF
2301 @@ -24,7 +27,7 @@
2302 #define BCMA_CC_FLASHT_NONE 0x00000000 /* No flash */
2303 #define BCMA_CC_FLASHT_STSER 0x00000100 /* ST serial flash */
2304 #define BCMA_CC_FLASHT_ATSER 0x00000200 /* Atmel serial flash */
2305 -#define BCMA_CC_FLASHT_NFLASH 0x00000200 /* NAND flash */
2306 +#define BCMA_CC_FLASHT_NAND 0x00000300 /* NAND flash */
2307 #define BCMA_CC_FLASHT_PARA 0x00000700 /* Parallel flash */
2308 #define BCMA_CC_CAP_PLLT 0x00038000 /* PLL Type */
2309 #define BCMA_PLLTYPE_NONE 0x00000000
2310 @@ -101,6 +104,7 @@
2311 #define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */
2312 #define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */
2313 #define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */
2314 +#define BCMA_CC_CHIPST_4360_XTAL_40MZ 0x00000001
2315 #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
2316 #define BCMA_CC_JCMD_START 0x80000000
2317 #define BCMA_CC_JCMD_BUSY 0x80000000
2318 @@ -312,6 +316,9 @@
2319 #define BCMA_CC_PMU_CTL 0x0600 /* PMU control */
2320 #define BCMA_CC_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
2321 #define BCMA_CC_PMU_CTL_ILP_DIV_SHIFT 16
2322 +#define BCMA_CC_PMU_CTL_RES 0x00006000 /* reset control mask */
2323 +#define BCMA_CC_PMU_CTL_RES_SHIFT 13
2324 +#define BCMA_CC_PMU_CTL_RES_RELOAD 0x2 /* reload POR values */
2325 #define BCMA_CC_PMU_CTL_PLL_UPD 0x00000400
2326 #define BCMA_CC_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
2327 #define BCMA_CC_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
2328 @@ -323,6 +330,8 @@
2329 #define BCMA_CC_PMU_CAP 0x0604 /* PMU capabilities */
2330 #define BCMA_CC_PMU_CAP_REVISION 0x000000FF /* Revision mask */
2331 #define BCMA_CC_PMU_STAT 0x0608 /* PMU status */
2332 +#define BCMA_CC_PMU_STAT_EXT_LPO_AVAIL 0x00000100
2333 +#define BCMA_CC_PMU_STAT_WDRESET 0x00000080
2334 #define BCMA_CC_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */
2335 #define BCMA_CC_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */
2336 #define BCMA_CC_PMU_STAT_HAVEALP 0x00000008 /* ALP available */
2337 @@ -348,6 +357,11 @@
2338 #define BCMA_CC_REGCTL_DATA 0x065C
2339 #define BCMA_CC_PLLCTL_ADDR 0x0660
2340 #define BCMA_CC_PLLCTL_DATA 0x0664
2341 +#define BCMA_CC_PMU_STRAPOPT 0x0668 /* (corerev >= 28) */
2342 +#define BCMA_CC_PMU_XTAL_FREQ 0x066C /* (pmurev >= 10) */
2343 +#define BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK 0x00001FFF
2344 +#define BCMA_CC_PMU_XTAL_FREQ_MEASURE_MASK 0x80000000
2345 +#define BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT 31
2346 #define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
2347 /* NAND flash MLC controller registers (corerev >= 38) */
2348 #define BCMA_CC_NAND_REVISION 0x0C00
2349 @@ -428,6 +442,23 @@
2350 #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_MASK 0x00000007
2351 #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_SHIFT 0
2352
2353 +/* PMU rev 15 */
2354 +#define BCMA_CC_PMU15_PLL_PLLCTL0 0
2355 +#define BCMA_CC_PMU15_PLL_PC0_CLKSEL_MASK 0x00000003
2356 +#define BCMA_CC_PMU15_PLL_PC0_CLKSEL_SHIFT 0
2357 +#define BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK 0x003FFFFC
2358 +#define BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT 2
2359 +#define BCMA_CC_PMU15_PLL_PC0_PRESCALE_MASK 0x00C00000
2360 +#define BCMA_CC_PMU15_PLL_PC0_PRESCALE_SHIFT 22
2361 +#define BCMA_CC_PMU15_PLL_PC0_KPCTRL_MASK 0x07000000
2362 +#define BCMA_CC_PMU15_PLL_PC0_KPCTRL_SHIFT 24
2363 +#define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_MASK 0x38000000
2364 +#define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_SHIFT 27
2365 +#define BCMA_CC_PMU15_PLL_PC0_FDCMODE_MASK 0x40000000
2366 +#define BCMA_CC_PMU15_PLL_PC0_FDCMODE_SHIFT 30
2367 +#define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_MASK 0x80000000
2368 +#define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_SHIFT 31
2369 +
2370 /* ALP clock on pre-PMU chips */
2371 #define BCMA_CC_PMU_ALP_CLOCK 20000000
2372 /* HT clock for systems with PMU-enabled chipcommon */
2373 @@ -500,6 +531,37 @@
2374 #define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE BIT(18)
2375 #define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE BIT(19)
2376
2377 +#define BCMA_RES_4314_LPLDO_PU BIT(0)
2378 +#define BCMA_RES_4314_PMU_SLEEP_DIS BIT(1)
2379 +#define BCMA_RES_4314_PMU_BG_PU BIT(2)
2380 +#define BCMA_RES_4314_CBUCK_LPOM_PU BIT(3)
2381 +#define BCMA_RES_4314_CBUCK_PFM_PU BIT(4)
2382 +#define BCMA_RES_4314_CLDO_PU BIT(5)
2383 +#define BCMA_RES_4314_LPLDO2_LVM BIT(6)
2384 +#define BCMA_RES_4314_WL_PMU_PU BIT(7)
2385 +#define BCMA_RES_4314_LNLDO_PU BIT(8)
2386 +#define BCMA_RES_4314_LDO3P3_PU BIT(9)
2387 +#define BCMA_RES_4314_OTP_PU BIT(10)
2388 +#define BCMA_RES_4314_XTAL_PU BIT(11)
2389 +#define BCMA_RES_4314_WL_PWRSW_PU BIT(12)
2390 +#define BCMA_RES_4314_LQ_AVAIL BIT(13)
2391 +#define BCMA_RES_4314_LOGIC_RET BIT(14)
2392 +#define BCMA_RES_4314_MEM_SLEEP BIT(15)
2393 +#define BCMA_RES_4314_MACPHY_RET BIT(16)
2394 +#define BCMA_RES_4314_WL_CORE_READY BIT(17)
2395 +#define BCMA_RES_4314_ILP_REQ BIT(18)
2396 +#define BCMA_RES_4314_ALP_AVAIL BIT(19)
2397 +#define BCMA_RES_4314_MISC_PWRSW_PU BIT(20)
2398 +#define BCMA_RES_4314_SYNTH_PWRSW_PU BIT(21)
2399 +#define BCMA_RES_4314_RX_PWRSW_PU BIT(22)
2400 +#define BCMA_RES_4314_RADIO_PU BIT(23)
2401 +#define BCMA_RES_4314_VCO_LDO_PU BIT(24)
2402 +#define BCMA_RES_4314_AFE_LDO_PU BIT(25)
2403 +#define BCMA_RES_4314_RX_LDO_PU BIT(26)
2404 +#define BCMA_RES_4314_TX_LDO_PU BIT(27)
2405 +#define BCMA_RES_4314_HT_AVAIL BIT(28)
2406 +#define BCMA_RES_4314_MACPHY_CLK_AVAIL BIT(29)
2407 +
2408 /* Data for the PMU, if available.
2409 * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
2410 */
2411 @@ -510,6 +572,7 @@ struct bcma_chipcommon_pmu {
2412
2413 #ifdef CONFIG_BCMA_DRIVER_MIPS
2414 struct bcma_pflash {
2415 + bool present;
2416 u8 buswidth;
2417 u32 window;
2418 u32 window_size;
2419 @@ -524,6 +587,7 @@ struct bcma_sflash {
2420 u32 size;
2421
2422 struct mtd_info *mtd;
2423 + void *priv;
2424 };
2425 #endif
2426
2427 @@ -532,6 +596,7 @@ struct mtd_info;
2428
2429 struct bcma_nflash {
2430 bool present;
2431 + bool boot; /* This is the flash the SoC boots from */
2432
2433 struct mtd_info *mtd;
2434 };
2435 @@ -552,6 +617,7 @@ struct bcma_drv_cc {
2436 u32 capabilities;
2437 u32 capabilities_ext;
2438 u8 setup_done:1;
2439 + u8 early_setup_done:1;
2440 /* Fast Powerup Delay constant */
2441 u16 fast_pwrup_delay;
2442 struct bcma_chipcommon_pmu pmu;
2443 @@ -567,6 +633,14 @@ struct bcma_drv_cc {
2444 int nr_serial_ports;
2445 struct bcma_serial_port serial_ports[4];
2446 #endif /* CONFIG_BCMA_DRIVER_MIPS */
2447 + u32 ticks_per_ms;
2448 + struct platform_device *watchdog;
2449 +
2450 + /* Lock for GPIO register access. */
2451 + spinlock_t gpio_lock;
2452 +#ifdef CONFIG_BCMA_DRIVER_GPIO
2453 + struct gpio_chip gpio;
2454 +#endif
2455 };
2456
2457 /* Register access */
2458 @@ -583,14 +657,16 @@ struct bcma_drv_cc {
2459 bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
2460
2461 extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
2462 +extern void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc);
2463
2464 extern void bcma_chipco_suspend(struct bcma_drv_cc *cc);
2465 extern void bcma_chipco_resume(struct bcma_drv_cc *cc);
2466
2467 void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable);
2468
2469 -extern void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc,
2470 - u32 ticks);
2471 +extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks);
2472 +
2473 +extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc);
2474
2475 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
2476
2477 @@ -603,9 +679,12 @@ u32 bcma_chipco_gpio_outen(struct bcma_d
2478 u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value);
2479 u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value);
2480 u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value);
2481 +u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value);
2482 +u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value);
2483
2484 /* PMU support */
2485 extern void bcma_pmu_init(struct bcma_drv_cc *cc);
2486 +extern void bcma_pmu_early_init(struct bcma_drv_cc *cc);
2487
2488 extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset,
2489 u32 value);
2490 @@ -617,4 +696,6 @@ extern void bcma_chipco_regctl_maskset(s
2491 u32 offset, u32 mask, u32 set);
2492 extern void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid);
2493
2494 +extern u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc);
2495 +
2496 #endif /* LINUX_BCMA_DRIVER_CC_H_ */
2497 --- a/include/linux/bcma/bcma_driver_mips.h
2498 +++ b/include/linux/bcma/bcma_driver_mips.h
2499 @@ -28,6 +28,7 @@
2500 #define BCMA_MIPS_MIPS74K_GPIOEN 0x0048
2501 #define BCMA_MIPS_MIPS74K_CLKCTLST 0x01E0
2502
2503 +#define BCMA_MIPS_OOBSELINA74 0x004
2504 #define BCMA_MIPS_OOBSELOUTA30 0x100
2505
2506 struct bcma_device;
2507 @@ -35,17 +36,24 @@ struct bcma_device;
2508 struct bcma_drv_mips {
2509 struct bcma_device *core;
2510 u8 setup_done:1;
2511 - unsigned int assigned_irqs;
2512 + u8 early_setup_done:1;
2513 };
2514
2515 #ifdef CONFIG_BCMA_DRIVER_MIPS
2516 extern void bcma_core_mips_init(struct bcma_drv_mips *mcore);
2517 +extern void bcma_core_mips_early_init(struct bcma_drv_mips *mcore);
2518 +
2519 +extern unsigned int bcma_core_irq(struct bcma_device *core);
2520 #else
2521 static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { }
2522 +static inline void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) { }
2523 +
2524 +static inline unsigned int bcma_core_irq(struct bcma_device *core)
2525 +{
2526 + return 0;
2527 +}
2528 #endif
2529
2530 extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore);
2531
2532 -extern unsigned int bcma_core_mips_irq(struct bcma_device *dev);
2533 -
2534 #endif /* LINUX_BCMA_DRIVER_MIPS_H_ */
2535 --- a/include/linux/bcma/bcma_driver_pci.h
2536 +++ b/include/linux/bcma/bcma_driver_pci.h
2537 @@ -179,6 +179,8 @@ struct pci_dev;
2538 #define BCMA_CORE_PCI_CFG_FUN_MASK 7 /* Function mask */
2539 #define BCMA_CORE_PCI_CFG_OFF_MASK 0xfff /* Register mask */
2540
2541 +#define BCMA_CORE_PCI_CFG_DEVCTRL 0xd8
2542 +
2543 /* PCIE Root Capability Register bits (Host mode only) */
2544 #define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001
2545
2546 --- a/include/linux/bcma/bcma_regs.h
2547 +++ b/include/linux/bcma/bcma_regs.h
2548 @@ -37,6 +37,7 @@
2549 #define BCMA_IOST_BIST_DONE 0x8000
2550 #define BCMA_RESET_CTL 0x0800
2551 #define BCMA_RESET_CTL_RESET 0x0001
2552 +#define BCMA_RESET_ST 0x0804
2553
2554 /* BCMA PCI config space registers. */
2555 #define BCMA_PCI_PMCSR 0x44
2556 @@ -85,6 +86,9 @@
2557 * (2 ZettaBytes), high 32 bits
2558 */
2559
2560 -#define BCMA_SFLASH 0x1c000000
2561 +#define BCMA_SOC_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
2562 +#define BCMA_SOC_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
2563 +#define BCMA_SOC_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
2564 +#define BCMA_SOC_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
2565
2566 #endif /* LINUX_BCMA_REGS_H_ */
2567 --- a/drivers/net/wireless/b43/main.c
2568 +++ b/drivers/net/wireless/b43/main.c
2569 @@ -4684,7 +4684,7 @@ static int b43_wireless_core_init(struct
2570 switch (dev->dev->bus_type) {
2571 #ifdef CONFIG_B43_BCMA
2572 case B43_BUS_BCMA:
2573 - bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci,
2574 + bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci[0],
2575 dev->dev->bdev, true);
2576 break;
2577 #endif
2578 --- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
2579 +++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
2580 @@ -692,7 +692,7 @@ void ai_pci_up(struct si_pub *sih)
2581 sii = container_of(sih, struct si_info, pub);
2582
2583 if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
2584 - bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, true);
2585 + bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], true);
2586 }
2587
2588 /* Unconfigure and/or apply various WARs when going down */
2589 @@ -703,7 +703,7 @@ void ai_pci_down(struct si_pub *sih)
2590 sii = container_of(sih, struct si_info, pub);
2591
2592 if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
2593 - bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, false);
2594 + bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], false);
2595 }
2596
2597 /* Enable BT-COEX & Ex-PA for 4313 */
2598 --- a/drivers/net/wireless/brcm80211/brcmsmac/main.c
2599 +++ b/drivers/net/wireless/brcm80211/brcmsmac/main.c
2600 @@ -5077,7 +5077,7 @@ static int brcms_b_up_prep(struct brcms_
2601 * Configure pci/pcmcia here instead of in brcms_c_attach()
2602 * to allow mfg hotswap: down, hotswap (chip power cycle), up.
2603 */
2604 - bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci, wlc_hw->d11core,
2605 + bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci[0], wlc_hw->d11core,
2606 true);
2607
2608 /*
Staging tree of Zoltan Herpai