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kernel: update bcma and ssb to version from wireless-testing/master tag master-2013...
[openwrt/staging/chunkeey.git] / target / linux / generic / patches-3.8 / 025-bcma_backport.patch
1 --- a/arch/mips/bcm47xx/serial.c
2 +++ b/arch/mips/bcm47xx/serial.c
3 @@ -62,7 +62,7 @@ static int __init uart8250_init_bcma(voi
4
5 p->mapbase = (unsigned int) bcma_port->regs;
6 p->membase = (void *) bcma_port->regs;
7 - p->irq = bcma_port->irq + 2;
8 + p->irq = bcma_port->irq;
9 p->uartclk = bcma_port->baud_base;
10 p->regshift = bcma_port->reg_shift;
11 p->iotype = UPIO_MEM;
12 --- a/drivers/bcma/Kconfig
13 +++ b/drivers/bcma/Kconfig
14 @@ -26,6 +26,7 @@ config BCMA_HOST_PCI_POSSIBLE
15 config BCMA_HOST_PCI
16 bool "Support for BCMA on PCI-host bus"
17 depends on BCMA_HOST_PCI_POSSIBLE
18 + default y
19
20 config BCMA_DRIVER_PCI_HOSTMODE
21 bool "Driver for PCI core working in hostmode"
22 --- a/drivers/bcma/bcma_private.h
23 +++ b/drivers/bcma/bcma_private.h
24 @@ -22,6 +22,8 @@
25 struct bcma_bus;
26
27 /* main.c */
28 +bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
29 + int timeout);
30 int bcma_bus_register(struct bcma_bus *bus);
31 void bcma_bus_unregister(struct bcma_bus *bus);
32 int __init bcma_bus_early_register(struct bcma_bus *bus,
33 @@ -31,6 +33,8 @@ int __init bcma_bus_early_register(struc
34 int bcma_bus_suspend(struct bcma_bus *bus);
35 int bcma_bus_resume(struct bcma_bus *bus);
36 #endif
37 +struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
38 + u8 unit);
39
40 /* scan.c */
41 int bcma_bus_scan(struct bcma_bus *bus);
42 @@ -45,6 +49,7 @@ int bcma_sprom_get(struct bcma_bus *bus)
43 /* driver_chipcommon.c */
44 #ifdef CONFIG_BCMA_DRIVER_MIPS
45 void bcma_chipco_serial_init(struct bcma_drv_cc *cc);
46 +extern struct platform_device bcma_pflash_dev;
47 #endif /* CONFIG_BCMA_DRIVER_MIPS */
48
49 /* driver_chipcommon_pmu.c */
50 --- a/drivers/bcma/core.c
51 +++ b/drivers/bcma/core.c
52 @@ -9,6 +9,25 @@
53 #include <linux/export.h>
54 #include <linux/bcma/bcma.h>
55
56 +static bool bcma_core_wait_value(struct bcma_device *core, u16 reg, u32 mask,
57 + u32 value, int timeout)
58 +{
59 + unsigned long deadline = jiffies + timeout;
60 + u32 val;
61 +
62 + do {
63 + val = bcma_aread32(core, reg);
64 + if ((val & mask) == value)
65 + return true;
66 + cpu_relax();
67 + udelay(10);
68 + } while (!time_after_eq(jiffies, deadline));
69 +
70 + bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg);
71 +
72 + return false;
73 +}
74 +
75 bool bcma_core_is_enabled(struct bcma_device *core)
76 {
77 if ((bcma_aread32(core, BCMA_IOCTL) & (BCMA_IOCTL_CLK | BCMA_IOCTL_FGC))
78 @@ -25,13 +44,15 @@ void bcma_core_disable(struct bcma_devic
79 if (bcma_aread32(core, BCMA_RESET_CTL) & BCMA_RESET_CTL_RESET)
80 return;
81
82 - bcma_awrite32(core, BCMA_IOCTL, flags);
83 - bcma_aread32(core, BCMA_IOCTL);
84 - udelay(10);
85 + bcma_core_wait_value(core, BCMA_RESET_ST, ~0, 0, 300);
86
87 bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
88 bcma_aread32(core, BCMA_RESET_CTL);
89 udelay(1);
90 +
91 + bcma_awrite32(core, BCMA_IOCTL, flags);
92 + bcma_aread32(core, BCMA_IOCTL);
93 + udelay(10);
94 }
95 EXPORT_SYMBOL_GPL(bcma_core_disable);
96
97 @@ -43,6 +64,7 @@ int bcma_core_enable(struct bcma_device
98 bcma_aread32(core, BCMA_IOCTL);
99
100 bcma_awrite32(core, BCMA_RESET_CTL, 0);
101 + bcma_aread32(core, BCMA_RESET_CTL);
102 udelay(1);
103
104 bcma_awrite32(core, BCMA_IOCTL, (BCMA_IOCTL_CLK | flags));
105 @@ -104,7 +126,13 @@ void bcma_core_pll_ctl(struct bcma_devic
106 if (i)
107 bcma_err(core->bus, "PLL enable timeout\n");
108 } else {
109 - bcma_warn(core->bus, "Disabling PLL not supported yet!\n");
110 + /*
111 + * Mask the PLL but don't wait for it to be disabled. PLL may be
112 + * shared between cores and will be still up if there is another
113 + * core using it.
114 + */
115 + bcma_mask32(core, BCMA_CLKCTLST, ~req);
116 + bcma_read32(core, BCMA_CLKCTLST);
117 }
118 }
119 EXPORT_SYMBOL_GPL(bcma_core_pll_ctl);
120 --- a/drivers/bcma/driver_chipcommon.c
121 +++ b/drivers/bcma/driver_chipcommon.c
122 @@ -25,13 +25,14 @@ static inline u32 bcma_cc_write32_masked
123 return value;
124 }
125
126 -static u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
127 +u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
128 {
129 if (cc->capabilities & BCMA_CC_CAP_PMU)
130 return bcma_pmu_get_alp_clock(cc);
131
132 return 20000000;
133 }
134 +EXPORT_SYMBOL_GPL(bcma_chipco_get_alp_clock);
135
136 static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc)
137 {
138 @@ -139,8 +140,15 @@ void bcma_core_chipcommon_init(struct bc
139 bcma_core_chipcommon_early_init(cc);
140
141 if (cc->core->id.rev >= 20) {
142 - bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
143 - bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
144 + u32 pullup = 0, pulldown = 0;
145 +
146 + if (cc->core->bus->chipinfo.id == BCMA_CHIP_ID_BCM43142) {
147 + pullup = 0x402e0;
148 + pulldown = 0x20500;
149 + }
150 +
151 + bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, pullup);
152 + bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, pulldown);
153 }
154
155 if (cc->capabilities & BCMA_CC_CAP_PMU)
156 @@ -213,6 +221,7 @@ u32 bcma_chipco_gpio_out(struct bcma_drv
157
158 return res;
159 }
160 +EXPORT_SYMBOL_GPL(bcma_chipco_gpio_out);
161
162 u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
163 {
164 @@ -225,6 +234,7 @@ u32 bcma_chipco_gpio_outen(struct bcma_d
165
166 return res;
167 }
168 +EXPORT_SYMBOL_GPL(bcma_chipco_gpio_outen);
169
170 /*
171 * If the bit is set to 0, chipcommon controlls this GPIO,
172 @@ -329,7 +339,7 @@ void bcma_chipco_serial_init(struct bcma
173 return;
174 }
175
176 - irq = bcma_core_mips_irq(cc->core);
177 + irq = bcma_core_irq(cc->core);
178
179 /* Determine the registers of the UARTs */
180 cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART);
181 --- a/drivers/bcma/driver_chipcommon_nflash.c
182 +++ b/drivers/bcma/driver_chipcommon_nflash.c
183 @@ -5,11 +5,11 @@
184 * Licensed under the GNU/GPL. See COPYING for details.
185 */
186
187 +#include "bcma_private.h"
188 +
189 #include <linux/platform_device.h>
190 #include <linux/bcma/bcma.h>
191
192 -#include "bcma_private.h"
193 -
194 struct platform_device bcma_nflash_dev = {
195 .name = "bcma_nflash",
196 .num_resources = 0,
197 --- a/drivers/bcma/driver_chipcommon_pmu.c
198 +++ b/drivers/bcma/driver_chipcommon_pmu.c
199 @@ -56,6 +56,109 @@ void bcma_chipco_regctl_maskset(struct b
200 }
201 EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
202
203 +static u32 bcma_pmu_xtalfreq(struct bcma_drv_cc *cc)
204 +{
205 + u32 ilp_ctl, alp_hz;
206 +
207 + if (!(bcma_cc_read32(cc, BCMA_CC_PMU_STAT) &
208 + BCMA_CC_PMU_STAT_EXT_LPO_AVAIL))
209 + return 0;
210 +
211 + bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ,
212 + BIT(BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT));
213 + usleep_range(1000, 2000);
214 +
215 + ilp_ctl = bcma_cc_read32(cc, BCMA_CC_PMU_XTAL_FREQ);
216 + ilp_ctl &= BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK;
217 +
218 + bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ, 0);
219 +
220 + alp_hz = ilp_ctl * 32768 / 4;
221 + return (alp_hz + 50000) / 100000 * 100;
222 +}
223 +
224 +static void bcma_pmu2_pll_init0(struct bcma_drv_cc *cc, u32 xtalfreq)
225 +{
226 + struct bcma_bus *bus = cc->core->bus;
227 + u32 freq_tgt_target = 0, freq_tgt_current;
228 + u32 pll0, mask;
229 +
230 + switch (bus->chipinfo.id) {
231 + case BCMA_CHIP_ID_BCM43142:
232 + /* pmu2_xtaltab0_adfll_485 */
233 + switch (xtalfreq) {
234 + case 12000:
235 + freq_tgt_target = 0x50D52;
236 + break;
237 + case 20000:
238 + freq_tgt_target = 0x307FE;
239 + break;
240 + case 26000:
241 + freq_tgt_target = 0x254EA;
242 + break;
243 + case 37400:
244 + freq_tgt_target = 0x19EF8;
245 + break;
246 + case 52000:
247 + freq_tgt_target = 0x12A75;
248 + break;
249 + }
250 + break;
251 + }
252 +
253 + if (!freq_tgt_target) {
254 + bcma_err(bus, "Unknown TGT frequency for xtalfreq %d\n",
255 + xtalfreq);
256 + return;
257 + }
258 +
259 + pll0 = bcma_chipco_pll_read(cc, BCMA_CC_PMU15_PLL_PLLCTL0);
260 + freq_tgt_current = (pll0 & BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK) >>
261 + BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
262 +
263 + if (freq_tgt_current == freq_tgt_target) {
264 + bcma_debug(bus, "Target TGT frequency already set\n");
265 + return;
266 + }
267 +
268 + /* Turn off PLL */
269 + switch (bus->chipinfo.id) {
270 + case BCMA_CHIP_ID_BCM43142:
271 + mask = (u32)~(BCMA_RES_4314_HT_AVAIL |
272 + BCMA_RES_4314_MACPHY_CLK_AVAIL);
273 +
274 + bcma_cc_mask32(cc, BCMA_CC_PMU_MINRES_MSK, mask);
275 + bcma_cc_mask32(cc, BCMA_CC_PMU_MAXRES_MSK, mask);
276 + bcma_wait_value(cc->core, BCMA_CLKCTLST,
277 + BCMA_CLKCTLST_HAVEHT, 0, 20000);
278 + break;
279 + }
280 +
281 + pll0 &= ~BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK;
282 + pll0 |= freq_tgt_target << BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
283 + bcma_chipco_pll_write(cc, BCMA_CC_PMU15_PLL_PLLCTL0, pll0);
284 +
285 + /* Flush */
286 + if (cc->pmu.rev >= 2)
287 + bcma_cc_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD);
288 +
289 + /* TODO: Do we need to update OTP? */
290 +}
291 +
292 +static void bcma_pmu_pll_init(struct bcma_drv_cc *cc)
293 +{
294 + struct bcma_bus *bus = cc->core->bus;
295 + u32 xtalfreq = bcma_pmu_xtalfreq(cc);
296 +
297 + switch (bus->chipinfo.id) {
298 + case BCMA_CHIP_ID_BCM43142:
299 + if (xtalfreq == 0)
300 + xtalfreq = 20000;
301 + bcma_pmu2_pll_init0(cc, xtalfreq);
302 + break;
303 + }
304 +}
305 +
306 static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
307 {
308 struct bcma_bus *bus = cc->core->bus;
309 @@ -66,6 +169,25 @@ static void bcma_pmu_resources_init(stru
310 min_msk = 0x200D;
311 max_msk = 0xFFFF;
312 break;
313 + case BCMA_CHIP_ID_BCM43142:
314 + min_msk = BCMA_RES_4314_LPLDO_PU |
315 + BCMA_RES_4314_PMU_SLEEP_DIS |
316 + BCMA_RES_4314_PMU_BG_PU |
317 + BCMA_RES_4314_CBUCK_LPOM_PU |
318 + BCMA_RES_4314_CBUCK_PFM_PU |
319 + BCMA_RES_4314_CLDO_PU |
320 + BCMA_RES_4314_LPLDO2_LVM |
321 + BCMA_RES_4314_WL_PMU_PU |
322 + BCMA_RES_4314_LDO3P3_PU |
323 + BCMA_RES_4314_OTP_PU |
324 + BCMA_RES_4314_WL_PWRSW_PU |
325 + BCMA_RES_4314_LQ_AVAIL |
326 + BCMA_RES_4314_LOGIC_RET |
327 + BCMA_RES_4314_MEM_SLEEP |
328 + BCMA_RES_4314_MACPHY_RET |
329 + BCMA_RES_4314_WL_CORE_READY;
330 + max_msk = 0x3FFFFFFF;
331 + break;
332 default:
333 bcma_debug(bus, "PMU resource config unknown or not needed for device 0x%04X\n",
334 bus->chipinfo.id);
335 @@ -165,6 +287,7 @@ void bcma_pmu_init(struct bcma_drv_cc *c
336 bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
337 BCMA_CC_PMU_CTL_NOILPONW);
338
339 + bcma_pmu_pll_init(cc);
340 bcma_pmu_resources_init(cc);
341 bcma_pmu_workarounds(cc);
342 }
343 @@ -174,19 +297,35 @@ u32 bcma_pmu_get_alp_clock(struct bcma_d
344 struct bcma_bus *bus = cc->core->bus;
345
346 switch (bus->chipinfo.id) {
347 + case BCMA_CHIP_ID_BCM4313:
348 + case BCMA_CHIP_ID_BCM43224:
349 + case BCMA_CHIP_ID_BCM43225:
350 + case BCMA_CHIP_ID_BCM43227:
351 + case BCMA_CHIP_ID_BCM43228:
352 + case BCMA_CHIP_ID_BCM4331:
353 + case BCMA_CHIP_ID_BCM43421:
354 + case BCMA_CHIP_ID_BCM43428:
355 + case BCMA_CHIP_ID_BCM43431:
356 case BCMA_CHIP_ID_BCM4716:
357 - case BCMA_CHIP_ID_BCM4748:
358 case BCMA_CHIP_ID_BCM47162:
359 - case BCMA_CHIP_ID_BCM4313:
360 - case BCMA_CHIP_ID_BCM5357:
361 + case BCMA_CHIP_ID_BCM4748:
362 case BCMA_CHIP_ID_BCM4749:
363 + case BCMA_CHIP_ID_BCM5357:
364 case BCMA_CHIP_ID_BCM53572:
365 + case BCMA_CHIP_ID_BCM6362:
366 /* always 20Mhz */
367 return 20000 * 1000;
368 - case BCMA_CHIP_ID_BCM5356:
369 case BCMA_CHIP_ID_BCM4706:
370 + case BCMA_CHIP_ID_BCM5356:
371 /* always 25Mhz */
372 return 25000 * 1000;
373 + case BCMA_CHIP_ID_BCM43460:
374 + case BCMA_CHIP_ID_BCM4352:
375 + case BCMA_CHIP_ID_BCM4360:
376 + if (cc->status & BCMA_CC_CHIPST_4360_XTAL_40MZ)
377 + return 40000 * 1000;
378 + else
379 + return 20000 * 1000;
380 default:
381 bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
382 bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
383 @@ -264,7 +403,7 @@ static u32 bcma_pmu_pll_clock_bcm4706(st
384 }
385
386 /* query bus clock frequency for PMU-enabled chipcommon */
387 -static u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc)
388 +u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc)
389 {
390 struct bcma_bus *bus = cc->core->bus;
391
392 @@ -293,6 +432,7 @@ static u32 bcma_pmu_get_bus_clock(struct
393 }
394 return BCMA_CC_PMU_HT_CLOCK;
395 }
396 +EXPORT_SYMBOL_GPL(bcma_pmu_get_bus_clock);
397
398 /* query cpu clock frequency for PMU-enabled chipcommon */
399 u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc)
400 @@ -372,7 +512,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
401 tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
402 bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
403
404 - tmp = 1 << 10;
405 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
406 break;
407
408 case BCMA_CHIP_ID_BCM4331:
409 @@ -393,7 +533,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
410 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
411 0x03000a08);
412 }
413 - tmp = 1 << 10;
414 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
415 break;
416
417 case BCMA_CHIP_ID_BCM43224:
418 @@ -426,7 +566,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
419 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
420 0x88888815);
421 }
422 - tmp = 1 << 10;
423 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
424 break;
425
426 case BCMA_CHIP_ID_BCM4716:
427 @@ -460,7 +600,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
428 0x88888815);
429 }
430
431 - tmp = 3 << 9;
432 + tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
433 break;
434
435 case BCMA_CHIP_ID_BCM43227:
436 @@ -496,7 +636,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
437 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
438 0x88888815);
439 }
440 - tmp = 1 << 10;
441 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
442 break;
443 default:
444 bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
445 --- a/drivers/bcma/driver_chipcommon_sflash.c
446 +++ b/drivers/bcma/driver_chipcommon_sflash.c
447 @@ -5,11 +5,11 @@
448 * Licensed under the GNU/GPL. See COPYING for details.
449 */
450
451 +#include "bcma_private.h"
452 +
453 #include <linux/platform_device.h>
454 #include <linux/bcma/bcma.h>
455
456 -#include "bcma_private.h"
457 -
458 static struct resource bcma_sflash_resource = {
459 .name = "bcma_sflash",
460 .start = BCMA_SOC_FLASH2,
461 @@ -30,7 +30,7 @@ struct bcma_sflash_tbl_e {
462 u16 numblocks;
463 };
464
465 -static struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
466 +static const struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
467 { "M25P20", 0x11, 0x10000, 4, },
468 { "M25P40", 0x12, 0x10000, 8, },
469
470 @@ -41,7 +41,7 @@ static struct bcma_sflash_tbl_e bcma_sfl
471 { 0 },
472 };
473
474 -static struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
475 +static const struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
476 { "SST25WF512", 1, 0x1000, 16, },
477 { "SST25VF512", 0x48, 0x1000, 16, },
478 { "SST25WF010", 2, 0x1000, 32, },
479 @@ -59,7 +59,7 @@ static struct bcma_sflash_tbl_e bcma_sfl
480 { 0 },
481 };
482
483 -static struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
484 +static const struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
485 { "AT45DB011", 0xc, 256, 512, },
486 { "AT45DB021", 0x14, 256, 1024, },
487 { "AT45DB041", 0x1c, 256, 2048, },
488 @@ -89,7 +89,7 @@ int bcma_sflash_init(struct bcma_drv_cc
489 {
490 struct bcma_bus *bus = cc->core->bus;
491 struct bcma_sflash *sflash = &cc->sflash;
492 - struct bcma_sflash_tbl_e *e;
493 + const struct bcma_sflash_tbl_e *e;
494 u32 id, id2;
495
496 switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
497 --- a/drivers/bcma/driver_gpio.c
498 +++ b/drivers/bcma/driver_gpio.c
499 @@ -73,6 +73,16 @@ static void bcma_gpio_free(struct gpio_c
500 bcma_chipco_gpio_pullup(cc, 1 << gpio, 0);
501 }
502
503 +static int bcma_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
504 +{
505 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
506 +
507 + if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
508 + return bcma_core_irq(cc->core);
509 + else
510 + return -EINVAL;
511 +}
512 +
513 int bcma_gpio_init(struct bcma_drv_cc *cc)
514 {
515 struct gpio_chip *chip = &cc->gpio;
516 @@ -85,6 +95,7 @@ int bcma_gpio_init(struct bcma_drv_cc *c
517 chip->set = bcma_gpio_set_value;
518 chip->direction_input = bcma_gpio_direction_input;
519 chip->direction_output = bcma_gpio_direction_output;
520 + chip->to_irq = bcma_gpio_to_irq;
521 chip->ngpio = 16;
522 /* There is just one SoC in one device and its GPIO addresses should be
523 * deterministic to address them more easily. The other buses could get
524 --- a/drivers/bcma/driver_mips.c
525 +++ b/drivers/bcma/driver_mips.c
526 @@ -14,11 +14,33 @@
527
528 #include <linux/bcma/bcma.h>
529
530 +#include <linux/mtd/physmap.h>
531 +#include <linux/platform_device.h>
532 #include <linux/serial.h>
533 #include <linux/serial_core.h>
534 #include <linux/serial_reg.h>
535 #include <linux/time.h>
536
537 +static const char *part_probes[] = { "bcm47xxpart", NULL };
538 +
539 +static struct physmap_flash_data bcma_pflash_data = {
540 + .part_probe_types = part_probes,
541 +};
542 +
543 +static struct resource bcma_pflash_resource = {
544 + .name = "bcma_pflash",
545 + .flags = IORESOURCE_MEM,
546 +};
547 +
548 +struct platform_device bcma_pflash_dev = {
549 + .name = "physmap-flash",
550 + .dev = {
551 + .platform_data = &bcma_pflash_data,
552 + },
553 + .resource = &bcma_pflash_resource,
554 + .num_resources = 1,
555 +};
556 +
557 /* The 47162a0 hangs when reading MIPS DMP registers registers */
558 static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev)
559 {
560 @@ -74,28 +96,41 @@ static u32 bcma_core_mips_irqflag(struct
561 return dev->core_index;
562 flag = bcma_aread32(dev, BCMA_MIPS_OOBSELOUTA30);
563
564 - return flag & 0x1F;
565 + if (flag)
566 + return flag & 0x1F;
567 + else
568 + return 0x3f;
569 }
570
571 /* Get the MIPS IRQ assignment for a specified device.
572 * If unassigned, 0 is returned.
573 + * If disabled, 5 is returned.
574 + * If not supported, 6 is returned.
575 */
576 -unsigned int bcma_core_mips_irq(struct bcma_device *dev)
577 +static unsigned int bcma_core_mips_irq(struct bcma_device *dev)
578 {
579 struct bcma_device *mdev = dev->bus->drv_mips.core;
580 u32 irqflag;
581 unsigned int irq;
582
583 irqflag = bcma_core_mips_irqflag(dev);
584 + if (irqflag == 0x3f)
585 + return 6;
586
587 - for (irq = 1; irq <= 4; irq++)
588 + for (irq = 0; irq <= 4; irq++)
589 if (bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq)) &
590 (1 << irqflag))
591 return irq;
592
593 - return 0;
594 + return 5;
595 }
596 -EXPORT_SYMBOL(bcma_core_mips_irq);
597 +
598 +unsigned int bcma_core_irq(struct bcma_device *dev)
599 +{
600 + unsigned int mips_irq = bcma_core_mips_irq(dev);
601 + return mips_irq <= 4 ? mips_irq + 2 : 0;
602 +}
603 +EXPORT_SYMBOL(bcma_core_irq);
604
605 static void bcma_core_mips_set_irq(struct bcma_device *dev, unsigned int irq)
606 {
607 @@ -114,7 +149,7 @@ static void bcma_core_mips_set_irq(struc
608 bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0),
609 bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) &
610 ~(1 << irqflag));
611 - else
612 + else if (oldirq != 5)
613 bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(oldirq), 0);
614
615 /* assign the new one */
616 @@ -123,9 +158,9 @@ static void bcma_core_mips_set_irq(struc
617 bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) |
618 (1 << irqflag));
619 } else {
620 - u32 oldirqflag = bcma_read32(mdev,
621 - BCMA_MIPS_MIPS74K_INTMASK(irq));
622 - if (oldirqflag) {
623 + u32 irqinitmask = bcma_read32(mdev,
624 + BCMA_MIPS_MIPS74K_INTMASK(irq));
625 + if (irqinitmask) {
626 struct bcma_device *core;
627
628 /* backplane irq line is in use, find out who uses
629 @@ -133,7 +168,7 @@ static void bcma_core_mips_set_irq(struc
630 */
631 list_for_each_entry(core, &bus->cores, list) {
632 if ((1 << bcma_core_mips_irqflag(core)) ==
633 - oldirqflag) {
634 + irqinitmask) {
635 bcma_core_mips_set_irq(core, 0);
636 break;
637 }
638 @@ -143,15 +178,31 @@ static void bcma_core_mips_set_irq(struc
639 1 << irqflag);
640 }
641
642 - bcma_info(bus, "set_irq: core 0x%04x, irq %d => %d\n",
643 - dev->id.id, oldirq + 2, irq + 2);
644 + bcma_debug(bus, "set_irq: core 0x%04x, irq %d => %d\n",
645 + dev->id.id, oldirq <= 4 ? oldirq + 2 : 0, irq + 2);
646 +}
647 +
648 +static void bcma_core_mips_set_irq_name(struct bcma_bus *bus, unsigned int irq,
649 + u16 coreid, u8 unit)
650 +{
651 + struct bcma_device *core;
652 +
653 + core = bcma_find_core_unit(bus, coreid, unit);
654 + if (!core) {
655 + bcma_warn(bus,
656 + "Can not find core (id: 0x%x, unit %i) for IRQ configuration.\n",
657 + coreid, unit);
658 + return;
659 + }
660 +
661 + bcma_core_mips_set_irq(core, irq);
662 }
663
664 static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq)
665 {
666 int i;
667 static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
668 - printk(KERN_INFO KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
669 + printk(KERN_DEBUG KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
670 for (i = 0; i <= 6; i++)
671 printk(" %s%s", irq_name[i], i == irq ? "*" : " ");
672 printk("\n");
673 @@ -182,6 +233,7 @@ static void bcma_core_mips_flash_detect(
674 {
675 struct bcma_bus *bus = mcore->core->bus;
676 struct bcma_drv_cc *cc = &bus->drv_cc;
677 + struct bcma_pflash *pflash = &cc->pflash;
678
679 switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
680 case BCMA_CC_FLASHT_STSER:
681 @@ -191,15 +243,20 @@ static void bcma_core_mips_flash_detect(
682 break;
683 case BCMA_CC_FLASHT_PARA:
684 bcma_debug(bus, "Found parallel flash\n");
685 - cc->pflash.present = true;
686 - cc->pflash.window = BCMA_SOC_FLASH2;
687 - cc->pflash.window_size = BCMA_SOC_FLASH2_SZ;
688 + pflash->present = true;
689 + pflash->window = BCMA_SOC_FLASH2;
690 + pflash->window_size = BCMA_SOC_FLASH2_SZ;
691
692 if ((bcma_read32(cc->core, BCMA_CC_FLASH_CFG) &
693 BCMA_CC_FLASH_CFG_DS) == 0)
694 - cc->pflash.buswidth = 1;
695 + pflash->buswidth = 1;
696 else
697 - cc->pflash.buswidth = 2;
698 + pflash->buswidth = 2;
699 +
700 + bcma_pflash_data.width = pflash->buswidth;
701 + bcma_pflash_resource.start = pflash->window;
702 + bcma_pflash_resource.end = pflash->window + pflash->window_size;
703 +
704 break;
705 default:
706 bcma_err(bus, "Flash type not supported\n");
707 @@ -227,6 +284,32 @@ void bcma_core_mips_early_init(struct bc
708 mcore->early_setup_done = true;
709 }
710
711 +static void bcma_fix_i2s_irqflag(struct bcma_bus *bus)
712 +{
713 + struct bcma_device *cpu, *pcie, *i2s;
714 +
715 + /* Fixup the interrupts in 4716/4748 for i2s core (2010 Broadcom SDK)
716 + * (IRQ flags > 7 are ignored when setting the interrupt masks)
717 + */
718 + if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4716 &&
719 + bus->chipinfo.id != BCMA_CHIP_ID_BCM4748)
720 + return;
721 +
722 + cpu = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
723 + pcie = bcma_find_core(bus, BCMA_CORE_PCIE);
724 + i2s = bcma_find_core(bus, BCMA_CORE_I2S);
725 + if (cpu && pcie && i2s &&
726 + bcma_aread32(cpu, BCMA_MIPS_OOBSELINA74) == 0x08060504 &&
727 + bcma_aread32(pcie, BCMA_MIPS_OOBSELINA74) == 0x08060504 &&
728 + bcma_aread32(i2s, BCMA_MIPS_OOBSELOUTA30) == 0x88) {
729 + bcma_awrite32(cpu, BCMA_MIPS_OOBSELINA74, 0x07060504);
730 + bcma_awrite32(pcie, BCMA_MIPS_OOBSELINA74, 0x07060504);
731 + bcma_awrite32(i2s, BCMA_MIPS_OOBSELOUTA30, 0x87);
732 + bcma_debug(bus,
733 + "Moved i2s interrupt to oob line 7 instead of 8\n");
734 + }
735 +}
736 +
737 void bcma_core_mips_init(struct bcma_drv_mips *mcore)
738 {
739 struct bcma_bus *bus;
740 @@ -236,43 +319,55 @@ void bcma_core_mips_init(struct bcma_drv
741 if (mcore->setup_done)
742 return;
743
744 - bcma_info(bus, "Initializing MIPS core...\n");
745 + bcma_debug(bus, "Initializing MIPS core...\n");
746
747 bcma_core_mips_early_init(mcore);
748
749 - mcore->assigned_irqs = 1;
750 + bcma_fix_i2s_irqflag(bus);
751
752 - /* Assign IRQs to all cores on the bus */
753 - list_for_each_entry(core, &bus->cores, list) {
754 - int mips_irq;
755 - if (core->irq)
756 - continue;
757 -
758 - mips_irq = bcma_core_mips_irq(core);
759 - if (mips_irq > 4)
760 - core->irq = 0;
761 - else
762 - core->irq = mips_irq + 2;
763 - if (core->irq > 5)
764 - continue;
765 - switch (core->id.id) {
766 - case BCMA_CORE_PCI:
767 - case BCMA_CORE_PCIE:
768 - case BCMA_CORE_ETHERNET:
769 - case BCMA_CORE_ETHERNET_GBIT:
770 - case BCMA_CORE_MAC_GBIT:
771 - case BCMA_CORE_80211:
772 - case BCMA_CORE_USB20_HOST:
773 - /* These devices get their own IRQ line if available,
774 - * the rest goes on IRQ0
775 - */
776 - if (mcore->assigned_irqs <= 4)
777 - bcma_core_mips_set_irq(core,
778 - mcore->assigned_irqs++);
779 - break;
780 + switch (bus->chipinfo.id) {
781 + case BCMA_CHIP_ID_BCM4716:
782 + case BCMA_CHIP_ID_BCM4748:
783 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
784 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
785 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
786 + bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_PCIE, 0);
787 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
788 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
789 + break;
790 + case BCMA_CHIP_ID_BCM5356:
791 + case BCMA_CHIP_ID_BCM47162:
792 + case BCMA_CHIP_ID_BCM53572:
793 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
794 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
795 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
796 + break;
797 + case BCMA_CHIP_ID_BCM5357:
798 + case BCMA_CHIP_ID_BCM4749:
799 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
800 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
801 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
802 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
803 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
804 + break;
805 + case BCMA_CHIP_ID_BCM4706:
806 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_PCIE, 0);
807 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_4706_MAC_GBIT,
808 + 0);
809 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_PCIE, 1);
810 + bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_USB20_HOST, 0);
811 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_4706_CHIPCOMMON,
812 + 0);
813 + break;
814 + default:
815 + list_for_each_entry(core, &bus->cores, list) {
816 + core->irq = bcma_core_irq(core);
817 }
818 + bcma_err(bus,
819 + "Unknown device (0x%x) found, can not configure IRQs\n",
820 + bus->chipinfo.id);
821 }
822 - bcma_info(bus, "IRQ reconfiguration done\n");
823 + bcma_debug(bus, "IRQ reconfiguration done\n");
824 bcma_core_mips_dump_irq(bus);
825
826 mcore->setup_done = true;
827 --- a/drivers/bcma/driver_pci_host.c
828 +++ b/drivers/bcma/driver_pci_host.c
829 @@ -94,19 +94,19 @@ static int bcma_extpci_read_config(struc
830 if (dev == 0) {
831 /* we support only two functions on device 0 */
832 if (func > 1)
833 - return -EINVAL;
834 + goto out;
835
836 /* accesses to config registers with offsets >= 256
837 * requires indirect access.
838 */
839 if (off >= PCI_CONFIG_SPACE_SIZE) {
840 addr = (func << 12);
841 - addr |= (off & 0x0FFF);
842 + addr |= (off & 0x0FFC);
843 val = bcma_pcie_read_config(pc, addr);
844 } else {
845 addr = BCMA_CORE_PCI_PCICFG0;
846 addr |= (func << 8);
847 - addr |= (off & 0xfc);
848 + addr |= (off & 0xFC);
849 val = pcicore_read32(pc, addr);
850 }
851 } else {
852 @@ -119,11 +119,9 @@ static int bcma_extpci_read_config(struc
853 goto out;
854
855 if (mips_busprobe32(val, mmio)) {
856 - val = 0xffffffff;
857 + val = 0xFFFFFFFF;
858 goto unmap;
859 }
860 -
861 - val = readl(mmio);
862 }
863 val >>= (8 * (off & 3));
864
865 @@ -151,7 +149,7 @@ static int bcma_extpci_write_config(stru
866 const void *buf, int len)
867 {
868 int err = -EINVAL;
869 - u32 addr = 0, val = 0;
870 + u32 addr, val;
871 void __iomem *mmio = 0;
872 u16 chipid = pc->core->bus->chipinfo.id;
873
874 @@ -159,16 +157,22 @@ static int bcma_extpci_write_config(stru
875 if (unlikely(len != 1 && len != 2 && len != 4))
876 goto out;
877 if (dev == 0) {
878 + /* we support only two functions on device 0 */
879 + if (func > 1)
880 + goto out;
881 +
882 /* accesses to config registers with offsets >= 256
883 * requires indirect access.
884 */
885 - if (off < PCI_CONFIG_SPACE_SIZE) {
886 - addr = pc->core->addr + BCMA_CORE_PCI_PCICFG0;
887 + if (off >= PCI_CONFIG_SPACE_SIZE) {
888 + addr = (func << 12);
889 + addr |= (off & 0x0FFC);
890 + val = bcma_pcie_read_config(pc, addr);
891 + } else {
892 + addr = BCMA_CORE_PCI_PCICFG0;
893 addr |= (func << 8);
894 - addr |= (off & 0xfc);
895 - mmio = ioremap_nocache(addr, sizeof(val));
896 - if (!mmio)
897 - goto out;
898 + addr |= (off & 0xFC);
899 + val = pcicore_read32(pc, addr);
900 }
901 } else {
902 addr = bcma_get_cfgspace_addr(pc, dev, func, off);
903 @@ -180,19 +184,17 @@ static int bcma_extpci_write_config(stru
904 goto out;
905
906 if (mips_busprobe32(val, mmio)) {
907 - val = 0xffffffff;
908 + val = 0xFFFFFFFF;
909 goto unmap;
910 }
911 }
912
913 switch (len) {
914 case 1:
915 - val = readl(mmio);
916 val &= ~(0xFF << (8 * (off & 3)));
917 val |= *((const u8 *)buf) << (8 * (off & 3));
918 break;
919 case 2:
920 - val = readl(mmio);
921 val &= ~(0xFFFF << (8 * (off & 3)));
922 val |= *((const u16 *)buf) << (8 * (off & 3));
923 break;
924 @@ -200,13 +202,14 @@ static int bcma_extpci_write_config(stru
925 val = *((const u32 *)buf);
926 break;
927 }
928 - if (dev == 0 && !addr) {
929 + if (dev == 0) {
930 /* accesses to config registers with offsets >= 256
931 * requires indirect access.
932 */
933 - addr = (func << 12);
934 - addr |= (off & 0x0FFF);
935 - bcma_pcie_write_config(pc, addr, val);
936 + if (off >= PCI_CONFIG_SPACE_SIZE)
937 + bcma_pcie_write_config(pc, addr, val);
938 + else
939 + pcicore_write32(pc, addr, val);
940 } else {
941 writel(val, mmio);
942
943 @@ -276,7 +279,7 @@ static u8 bcma_find_pci_capability(struc
944 /* check for Header type 0 */
945 bcma_extpci_read_config(pc, dev, func, PCI_HEADER_TYPE, &byte_val,
946 sizeof(u8));
947 - if ((byte_val & 0x7f) != PCI_HEADER_TYPE_NORMAL)
948 + if ((byte_val & 0x7F) != PCI_HEADER_TYPE_NORMAL)
949 return cap_ptr;
950
951 /* check if the capability pointer field exists */
952 @@ -401,6 +404,8 @@ void bcma_core_pci_hostmode_init(struct
953 return;
954 }
955
956 + spin_lock_init(&pc_host->cfgspace_lock);
957 +
958 pc->host_controller = pc_host;
959 pc_host->pci_controller.io_resource = &pc_host->io_resource;
960 pc_host->pci_controller.mem_resource = &pc_host->mem_resource;
961 @@ -426,7 +431,7 @@ void bcma_core_pci_hostmode_init(struct
962 /* Reset RC */
963 usleep_range(3000, 5000);
964 pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE);
965 - usleep_range(1000, 2000);
966 + msleep(50);
967 pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST |
968 BCMA_CORE_PCI_CTL_RST_OE);
969
970 @@ -488,6 +493,17 @@ void bcma_core_pci_hostmode_init(struct
971
972 bcma_core_pci_enable_crs(pc);
973
974 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706 ||
975 + bus->chipinfo.id == BCMA_CHIP_ID_BCM4716) {
976 + u16 val16;
977 + bcma_extpci_read_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL,
978 + &val16, sizeof(val16));
979 + val16 |= (2 << 5); /* Max payload size of 512 */
980 + val16 |= (2 << 12); /* MRRS 512 */
981 + bcma_extpci_write_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL,
982 + &val16, sizeof(val16));
983 + }
984 +
985 /* Enable PCI bridge BAR0 memory & master access */
986 tmp = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
987 bcma_extpci_write_config(pc, 0, 0, PCI_COMMAND, &tmp, sizeof(tmp));
988 @@ -576,7 +592,7 @@ int bcma_core_pci_plat_dev_init(struct p
989 pr_info("PCI: Fixing up device %s\n", pci_name(dev));
990
991 /* Fix up interrupt lines */
992 - dev->irq = bcma_core_mips_irq(pc_host->pdev->core) + 2;
993 + dev->irq = bcma_core_irq(pc_host->pdev->core);
994 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
995
996 return 0;
997 @@ -595,6 +611,6 @@ int bcma_core_pci_pcibios_map_irq(const
998
999 pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
1000 pci_ops);
1001 - return bcma_core_mips_irq(pc_host->pdev->core) + 2;
1002 + return bcma_core_irq(pc_host->pdev->core);
1003 }
1004 EXPORT_SYMBOL(bcma_core_pci_pcibios_map_irq);
1005 --- a/drivers/bcma/host_pci.c
1006 +++ b/drivers/bcma/host_pci.c
1007 @@ -275,6 +275,7 @@ static DEFINE_PCI_DEVICE_TABLE(bcma_pci_
1008 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
1009 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
1010 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
1011 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) },
1012 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
1013 { 0, },
1014 };
1015 --- a/drivers/bcma/main.c
1016 +++ b/drivers/bcma/main.c
1017 @@ -81,8 +81,8 @@ struct bcma_device *bcma_find_core(struc
1018 }
1019 EXPORT_SYMBOL_GPL(bcma_find_core);
1020
1021 -static struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
1022 - u8 unit)
1023 +struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
1024 + u8 unit)
1025 {
1026 struct bcma_device *core;
1027
1028 @@ -93,6 +93,25 @@ static struct bcma_device *bcma_find_cor
1029 return NULL;
1030 }
1031
1032 +bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
1033 + int timeout)
1034 +{
1035 + unsigned long deadline = jiffies + timeout;
1036 + u32 val;
1037 +
1038 + do {
1039 + val = bcma_read32(core, reg);
1040 + if ((val & mask) == value)
1041 + return true;
1042 + cpu_relax();
1043 + udelay(10);
1044 + } while (!time_after_eq(jiffies, deadline));
1045 +
1046 + bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg);
1047 +
1048 + return false;
1049 +}
1050 +
1051 static void bcma_release_core_dev(struct device *dev)
1052 {
1053 struct bcma_device *core = container_of(dev, struct bcma_device, dev);
1054 @@ -120,6 +139,11 @@ static int bcma_register_cores(struct bc
1055 continue;
1056 }
1057
1058 + /* Only first GMAC core on BCM4706 is connected and working */
1059 + if (core->id.id == BCMA_CORE_4706_MAC_GBIT &&
1060 + core->core_unit > 0)
1061 + continue;
1062 +
1063 core->dev.release = bcma_release_core_dev;
1064 core->dev.bus = &bcma_bus_type;
1065 dev_set_name(&core->dev, "bcma%d:%d", bus->num, dev_id);
1066 @@ -149,6 +173,14 @@ static int bcma_register_cores(struct bc
1067 dev_id++;
1068 }
1069
1070 +#ifdef CONFIG_BCMA_DRIVER_MIPS
1071 + if (bus->drv_cc.pflash.present) {
1072 + err = platform_device_register(&bcma_pflash_dev);
1073 + if (err)
1074 + bcma_err(bus, "Error registering parallel flash\n");
1075 + }
1076 +#endif
1077 +
1078 #ifdef CONFIG_BCMA_SFLASH
1079 if (bus->drv_cc.sflash.present) {
1080 err = platform_device_register(&bcma_sflash_dev);
1081 --- a/drivers/bcma/scan.c
1082 +++ b/drivers/bcma/scan.c
1083 @@ -84,6 +84,8 @@ static const struct bcma_device_id_name
1084 { BCMA_CORE_I2S, "I2S" },
1085 { BCMA_CORE_SDR_DDR1_MEM_CTL, "SDR/DDR1 Memory Controller" },
1086 { BCMA_CORE_SHIM, "SHIM" },
1087 + { BCMA_CORE_PCIE2, "PCIe Gen2" },
1088 + { BCMA_CORE_ARM_CR4, "ARM CR4" },
1089 { BCMA_CORE_DEFAULT, "Default" },
1090 };
1091
1092 @@ -137,19 +139,19 @@ static void bcma_scan_switch_core(struct
1093 addr);
1094 }
1095
1096 -static u32 bcma_erom_get_ent(struct bcma_bus *bus, u32 **eromptr)
1097 +static u32 bcma_erom_get_ent(struct bcma_bus *bus, u32 __iomem **eromptr)
1098 {
1099 u32 ent = readl(*eromptr);
1100 (*eromptr)++;
1101 return ent;
1102 }
1103
1104 -static void bcma_erom_push_ent(u32 **eromptr)
1105 +static void bcma_erom_push_ent(u32 __iomem **eromptr)
1106 {
1107 (*eromptr)--;
1108 }
1109
1110 -static s32 bcma_erom_get_ci(struct bcma_bus *bus, u32 **eromptr)
1111 +static s32 bcma_erom_get_ci(struct bcma_bus *bus, u32 __iomem **eromptr)
1112 {
1113 u32 ent = bcma_erom_get_ent(bus, eromptr);
1114 if (!(ent & SCAN_ER_VALID))
1115 @@ -159,14 +161,14 @@ static s32 bcma_erom_get_ci(struct bcma_
1116 return ent;
1117 }
1118
1119 -static bool bcma_erom_is_end(struct bcma_bus *bus, u32 **eromptr)
1120 +static bool bcma_erom_is_end(struct bcma_bus *bus, u32 __iomem **eromptr)
1121 {
1122 u32 ent = bcma_erom_get_ent(bus, eromptr);
1123 bcma_erom_push_ent(eromptr);
1124 return (ent == (SCAN_ER_TAG_END | SCAN_ER_VALID));
1125 }
1126
1127 -static bool bcma_erom_is_bridge(struct bcma_bus *bus, u32 **eromptr)
1128 +static bool bcma_erom_is_bridge(struct bcma_bus *bus, u32 __iomem **eromptr)
1129 {
1130 u32 ent = bcma_erom_get_ent(bus, eromptr);
1131 bcma_erom_push_ent(eromptr);
1132 @@ -175,7 +177,7 @@ static bool bcma_erom_is_bridge(struct b
1133 ((ent & SCAN_ADDR_TYPE) == SCAN_ADDR_TYPE_BRIDGE));
1134 }
1135
1136 -static void bcma_erom_skip_component(struct bcma_bus *bus, u32 **eromptr)
1137 +static void bcma_erom_skip_component(struct bcma_bus *bus, u32 __iomem **eromptr)
1138 {
1139 u32 ent;
1140 while (1) {
1141 @@ -189,7 +191,7 @@ static void bcma_erom_skip_component(str
1142 bcma_erom_push_ent(eromptr);
1143 }
1144
1145 -static s32 bcma_erom_get_mst_port(struct bcma_bus *bus, u32 **eromptr)
1146 +static s32 bcma_erom_get_mst_port(struct bcma_bus *bus, u32 __iomem **eromptr)
1147 {
1148 u32 ent = bcma_erom_get_ent(bus, eromptr);
1149 if (!(ent & SCAN_ER_VALID))
1150 @@ -199,7 +201,7 @@ static s32 bcma_erom_get_mst_port(struct
1151 return ent;
1152 }
1153
1154 -static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 **eromptr,
1155 +static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 __iomem **eromptr,
1156 u32 type, u8 port)
1157 {
1158 u32 addrl, addrh, sizel, sizeh = 0;
1159 --- a/drivers/bcma/sprom.c
1160 +++ b/drivers/bcma/sprom.c
1161 @@ -72,12 +72,12 @@ fail:
1162 * R/W ops.
1163 **************************************************/
1164
1165 -static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom)
1166 +static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom,
1167 + size_t words)
1168 {
1169 int i;
1170 - for (i = 0; i < SSB_SPROMSIZE_WORDS_R4; i++)
1171 - sprom[i] = bcma_read16(bus->drv_cc.core,
1172 - offset + (i * 2));
1173 + for (i = 0; i < words; i++)
1174 + sprom[i] = bcma_read16(bus->drv_cc.core, offset + (i * 2));
1175 }
1176
1177 /**************************************************
1178 @@ -124,29 +124,29 @@ static inline u8 bcma_crc8(u8 crc, u8 da
1179 return t[crc ^ data];
1180 }
1181
1182 -static u8 bcma_sprom_crc(const u16 *sprom)
1183 +static u8 bcma_sprom_crc(const u16 *sprom, size_t words)
1184 {
1185 int word;
1186 u8 crc = 0xFF;
1187
1188 - for (word = 0; word < SSB_SPROMSIZE_WORDS_R4 - 1; word++) {
1189 + for (word = 0; word < words - 1; word++) {
1190 crc = bcma_crc8(crc, sprom[word] & 0x00FF);
1191 crc = bcma_crc8(crc, (sprom[word] & 0xFF00) >> 8);
1192 }
1193 - crc = bcma_crc8(crc, sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & 0x00FF);
1194 + crc = bcma_crc8(crc, sprom[words - 1] & 0x00FF);
1195 crc ^= 0xFF;
1196
1197 return crc;
1198 }
1199
1200 -static int bcma_sprom_check_crc(const u16 *sprom)
1201 +static int bcma_sprom_check_crc(const u16 *sprom, size_t words)
1202 {
1203 u8 crc;
1204 u8 expected_crc;
1205 u16 tmp;
1206
1207 - crc = bcma_sprom_crc(sprom);
1208 - tmp = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_CRC;
1209 + crc = bcma_sprom_crc(sprom, words);
1210 + tmp = sprom[words - 1] & SSB_SPROM_REVISION_CRC;
1211 expected_crc = tmp >> SSB_SPROM_REVISION_CRC_SHIFT;
1212 if (crc != expected_crc)
1213 return -EPROTO;
1214 @@ -154,21 +154,25 @@ static int bcma_sprom_check_crc(const u1
1215 return 0;
1216 }
1217
1218 -static int bcma_sprom_valid(const u16 *sprom)
1219 +static int bcma_sprom_valid(struct bcma_bus *bus, const u16 *sprom,
1220 + size_t words)
1221 {
1222 u16 revision;
1223 int err;
1224
1225 - err = bcma_sprom_check_crc(sprom);
1226 + err = bcma_sprom_check_crc(sprom, words);
1227 if (err)
1228 return err;
1229
1230 - revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_REV;
1231 - if (revision != 8 && revision != 9) {
1232 + revision = sprom[words - 1] & SSB_SPROM_REVISION_REV;
1233 + if (revision != 8 && revision != 9 && revision != 10) {
1234 pr_err("Unsupported SPROM revision: %d\n", revision);
1235 return -ENOENT;
1236 }
1237
1238 + bus->sprom.revision = revision;
1239 + bcma_debug(bus, "Found SPROM revision %d\n", revision);
1240 +
1241 return 0;
1242 }
1243
1244 @@ -208,15 +212,13 @@ static void bcma_sprom_extract_r8(struct
1245 BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
1246 ARRAY_SIZE(bus->sprom.core_pwr_info));
1247
1248 - bus->sprom.revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] &
1249 - SSB_SPROM_REVISION_REV;
1250 -
1251 for (i = 0; i < 3; i++) {
1252 v = sprom[SPOFF(SSB_SPROM8_IL0MAC) + i];
1253 *(((__be16 *)bus->sprom.il0mac) + i) = cpu_to_be16(v);
1254 }
1255
1256 SPEX(board_rev, SSB_SPROM8_BOARDREV, ~0, 0);
1257 + SPEX(board_type, SSB_SPROM1_SPID, ~0, 0);
1258
1259 SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01, SSB_SPROM4_TXPID2G0,
1260 SSB_SPROM4_TXPID2G0_SHIFT);
1261 @@ -501,7 +503,7 @@ static bool bcma_sprom_onchip_available(
1262 case BCMA_CHIP_ID_BCM4331:
1263 present = chip_status & BCMA_CC_CHIPST_4331_OTP_PRESENT;
1264 break;
1265 -
1266 + case BCMA_CHIP_ID_BCM43142:
1267 case BCMA_CHIP_ID_BCM43224:
1268 case BCMA_CHIP_ID_BCM43225:
1269 /* for these chips OTP is always available */
1270 @@ -549,7 +551,9 @@ int bcma_sprom_get(struct bcma_bus *bus)
1271 {
1272 u16 offset = BCMA_CC_SPROM;
1273 u16 *sprom;
1274 - int err = 0;
1275 + size_t sprom_sizes[] = { SSB_SPROMSIZE_WORDS_R4,
1276 + SSB_SPROMSIZE_WORDS_R10, };
1277 + int i, err = 0;
1278
1279 if (!bus->drv_cc.core)
1280 return -EOPNOTSUPP;
1281 @@ -578,32 +582,37 @@ int bcma_sprom_get(struct bcma_bus *bus)
1282 }
1283 }
1284
1285 - sprom = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
1286 - GFP_KERNEL);
1287 - if (!sprom)
1288 - return -ENOMEM;
1289 -
1290 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
1291 bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
1292 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, false);
1293
1294 bcma_debug(bus, "SPROM offset 0x%x\n", offset);
1295 - bcma_sprom_read(bus, offset, sprom);
1296 + for (i = 0; i < ARRAY_SIZE(sprom_sizes); i++) {
1297 + size_t words = sprom_sizes[i];
1298 +
1299 + sprom = kcalloc(words, sizeof(u16), GFP_KERNEL);
1300 + if (!sprom)
1301 + return -ENOMEM;
1302 +
1303 + bcma_sprom_read(bus, offset, sprom, words);
1304 + err = bcma_sprom_valid(bus, sprom, words);
1305 + if (!err)
1306 + break;
1307 +
1308 + kfree(sprom);
1309 + }
1310
1311 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
1312 bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
1313 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
1314
1315 - err = bcma_sprom_valid(sprom);
1316 if (err) {
1317 - bcma_warn(bus, "invalid sprom read from the PCIe card, try to use fallback sprom\n");
1318 + bcma_warn(bus, "Invalid SPROM read from the PCIe card, trying to use fallback SPROM\n");
1319 err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
1320 - goto out;
1321 + } else {
1322 + bcma_sprom_extract_r8(bus, sprom);
1323 + kfree(sprom);
1324 }
1325
1326 - bcma_sprom_extract_r8(bus, sprom);
1327 -
1328 -out:
1329 - kfree(sprom);
1330 return err;
1331 }
1332 --- a/include/linux/bcma/bcma.h
1333 +++ b/include/linux/bcma/bcma.h
1334 @@ -134,12 +134,17 @@ struct bcma_host_ops {
1335 #define BCMA_CORE_I2S 0x834
1336 #define BCMA_CORE_SDR_DDR1_MEM_CTL 0x835 /* SDR/DDR1 memory controller core */
1337 #define BCMA_CORE_SHIM 0x837 /* SHIM component in ubus/6362 */
1338 +#define BCMA_CORE_PHY_AC 0x83B
1339 +#define BCMA_CORE_PCIE2 0x83C /* PCI Express Gen2 */
1340 +#define BCMA_CORE_USB30_DEV 0x83D
1341 +#define BCMA_CORE_ARM_CR4 0x83E
1342 #define BCMA_CORE_DEFAULT 0xFFF
1343
1344 #define BCMA_MAX_NR_CORES 16
1345
1346 /* Chip IDs of PCIe devices */
1347 #define BCMA_CHIP_ID_BCM4313 0x4313
1348 +#define BCMA_CHIP_ID_BCM43142 43142
1349 #define BCMA_CHIP_ID_BCM43224 43224
1350 #define BCMA_PKG_ID_BCM43224_FAB_CSM 0x8
1351 #define BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa
1352 @@ -173,6 +178,60 @@ struct bcma_host_ops {
1353 #define BCMA_CHIP_ID_BCM53572 53572
1354 #define BCMA_PKG_ID_BCM47188 9
1355
1356 +/* Board types (on PCI usually equals to the subsystem dev id) */
1357 +/* BCM4313 */
1358 +#define BCMA_BOARD_TYPE_BCM94313BU 0X050F
1359 +#define BCMA_BOARD_TYPE_BCM94313HM 0X0510
1360 +#define BCMA_BOARD_TYPE_BCM94313EPA 0X0511
1361 +#define BCMA_BOARD_TYPE_BCM94313HMG 0X051C
1362 +/* BCM4716 */
1363 +#define BCMA_BOARD_TYPE_BCM94716NR2 0X04CD
1364 +/* BCM43224 */
1365 +#define BCMA_BOARD_TYPE_BCM943224X21 0X056E
1366 +#define BCMA_BOARD_TYPE_BCM943224X21_FCC 0X00D1
1367 +#define BCMA_BOARD_TYPE_BCM943224X21B 0X00E9
1368 +#define BCMA_BOARD_TYPE_BCM943224M93 0X008B
1369 +#define BCMA_BOARD_TYPE_BCM943224M93A 0X0090
1370 +#define BCMA_BOARD_TYPE_BCM943224X16 0X0093
1371 +#define BCMA_BOARD_TYPE_BCM94322X9 0X008D
1372 +#define BCMA_BOARD_TYPE_BCM94322M35E 0X008E
1373 +/* BCM43228 */
1374 +#define BCMA_BOARD_TYPE_BCM943228BU8 0X0540
1375 +#define BCMA_BOARD_TYPE_BCM943228BU9 0X0541
1376 +#define BCMA_BOARD_TYPE_BCM943228BU 0X0542
1377 +#define BCMA_BOARD_TYPE_BCM943227HM4L 0X0543
1378 +#define BCMA_BOARD_TYPE_BCM943227HMB 0X0544
1379 +#define BCMA_BOARD_TYPE_BCM943228HM4L 0X0545
1380 +#define BCMA_BOARD_TYPE_BCM943228SD 0X0573
1381 +/* BCM4331 */
1382 +#define BCMA_BOARD_TYPE_BCM94331X19 0X00D6
1383 +#define BCMA_BOARD_TYPE_BCM94331X28 0X00E4
1384 +#define BCMA_BOARD_TYPE_BCM94331X28B 0X010E
1385 +#define BCMA_BOARD_TYPE_BCM94331PCIEBT3AX 0X00E4
1386 +#define BCMA_BOARD_TYPE_BCM94331X12_2G 0X00EC
1387 +#define BCMA_BOARD_TYPE_BCM94331X12_5G 0X00ED
1388 +#define BCMA_BOARD_TYPE_BCM94331X29B 0X00EF
1389 +#define BCMA_BOARD_TYPE_BCM94331CSAX 0X00EF
1390 +#define BCMA_BOARD_TYPE_BCM94331X19C 0X00F5
1391 +#define BCMA_BOARD_TYPE_BCM94331X33 0X00F4
1392 +#define BCMA_BOARD_TYPE_BCM94331BU 0X0523
1393 +#define BCMA_BOARD_TYPE_BCM94331S9BU 0X0524
1394 +#define BCMA_BOARD_TYPE_BCM94331MC 0X0525
1395 +#define BCMA_BOARD_TYPE_BCM94331MCI 0X0526
1396 +#define BCMA_BOARD_TYPE_BCM94331PCIEBT4 0X0527
1397 +#define BCMA_BOARD_TYPE_BCM94331HM 0X0574
1398 +#define BCMA_BOARD_TYPE_BCM94331PCIEDUAL 0X059B
1399 +#define BCMA_BOARD_TYPE_BCM94331MCH5 0X05A9
1400 +#define BCMA_BOARD_TYPE_BCM94331CS 0X05C6
1401 +#define BCMA_BOARD_TYPE_BCM94331CD 0X05DA
1402 +/* BCM53572 */
1403 +#define BCMA_BOARD_TYPE_BCM953572BU 0X058D
1404 +#define BCMA_BOARD_TYPE_BCM953572NR2 0X058E
1405 +#define BCMA_BOARD_TYPE_BCM947188NR2 0X058F
1406 +#define BCMA_BOARD_TYPE_BCM953572SDRNR2 0X0590
1407 +/* BCM43142 */
1408 +#define BCMA_BOARD_TYPE_BCM943142HM 0X05E0
1409 +
1410 struct bcma_device {
1411 struct bcma_bus *bus;
1412 struct bcma_device_id id;
1413 --- a/include/linux/bcma/bcma_driver_chipcommon.h
1414 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
1415 @@ -27,7 +27,7 @@
1416 #define BCMA_CC_FLASHT_NONE 0x00000000 /* No flash */
1417 #define BCMA_CC_FLASHT_STSER 0x00000100 /* ST serial flash */
1418 #define BCMA_CC_FLASHT_ATSER 0x00000200 /* Atmel serial flash */
1419 -#define BCMA_CC_FLASHT_NFLASH 0x00000200 /* NAND flash */
1420 +#define BCMA_CC_FLASHT_NAND 0x00000300 /* NAND flash */
1421 #define BCMA_CC_FLASHT_PARA 0x00000700 /* Parallel flash */
1422 #define BCMA_CC_CAP_PLLT 0x00038000 /* PLL Type */
1423 #define BCMA_PLLTYPE_NONE 0x00000000
1424 @@ -104,6 +104,7 @@
1425 #define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */
1426 #define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */
1427 #define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */
1428 +#define BCMA_CC_CHIPST_4360_XTAL_40MZ 0x00000001
1429 #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
1430 #define BCMA_CC_JCMD_START 0x80000000
1431 #define BCMA_CC_JCMD_BUSY 0x80000000
1432 @@ -315,6 +316,9 @@
1433 #define BCMA_CC_PMU_CTL 0x0600 /* PMU control */
1434 #define BCMA_CC_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
1435 #define BCMA_CC_PMU_CTL_ILP_DIV_SHIFT 16
1436 +#define BCMA_CC_PMU_CTL_RES 0x00006000 /* reset control mask */
1437 +#define BCMA_CC_PMU_CTL_RES_SHIFT 13
1438 +#define BCMA_CC_PMU_CTL_RES_RELOAD 0x2 /* reload POR values */
1439 #define BCMA_CC_PMU_CTL_PLL_UPD 0x00000400
1440 #define BCMA_CC_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
1441 #define BCMA_CC_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
1442 @@ -326,6 +330,8 @@
1443 #define BCMA_CC_PMU_CAP 0x0604 /* PMU capabilities */
1444 #define BCMA_CC_PMU_CAP_REVISION 0x000000FF /* Revision mask */
1445 #define BCMA_CC_PMU_STAT 0x0608 /* PMU status */
1446 +#define BCMA_CC_PMU_STAT_EXT_LPO_AVAIL 0x00000100
1447 +#define BCMA_CC_PMU_STAT_WDRESET 0x00000080
1448 #define BCMA_CC_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */
1449 #define BCMA_CC_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */
1450 #define BCMA_CC_PMU_STAT_HAVEALP 0x00000008 /* ALP available */
1451 @@ -351,6 +357,11 @@
1452 #define BCMA_CC_REGCTL_DATA 0x065C
1453 #define BCMA_CC_PLLCTL_ADDR 0x0660
1454 #define BCMA_CC_PLLCTL_DATA 0x0664
1455 +#define BCMA_CC_PMU_STRAPOPT 0x0668 /* (corerev >= 28) */
1456 +#define BCMA_CC_PMU_XTAL_FREQ 0x066C /* (pmurev >= 10) */
1457 +#define BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK 0x00001FFF
1458 +#define BCMA_CC_PMU_XTAL_FREQ_MEASURE_MASK 0x80000000
1459 +#define BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT 31
1460 #define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
1461 /* NAND flash MLC controller registers (corerev >= 38) */
1462 #define BCMA_CC_NAND_REVISION 0x0C00
1463 @@ -431,6 +442,23 @@
1464 #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_MASK 0x00000007
1465 #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_SHIFT 0
1466
1467 +/* PMU rev 15 */
1468 +#define BCMA_CC_PMU15_PLL_PLLCTL0 0
1469 +#define BCMA_CC_PMU15_PLL_PC0_CLKSEL_MASK 0x00000003
1470 +#define BCMA_CC_PMU15_PLL_PC0_CLKSEL_SHIFT 0
1471 +#define BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK 0x003FFFFC
1472 +#define BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT 2
1473 +#define BCMA_CC_PMU15_PLL_PC0_PRESCALE_MASK 0x00C00000
1474 +#define BCMA_CC_PMU15_PLL_PC0_PRESCALE_SHIFT 22
1475 +#define BCMA_CC_PMU15_PLL_PC0_KPCTRL_MASK 0x07000000
1476 +#define BCMA_CC_PMU15_PLL_PC0_KPCTRL_SHIFT 24
1477 +#define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_MASK 0x38000000
1478 +#define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_SHIFT 27
1479 +#define BCMA_CC_PMU15_PLL_PC0_FDCMODE_MASK 0x40000000
1480 +#define BCMA_CC_PMU15_PLL_PC0_FDCMODE_SHIFT 30
1481 +#define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_MASK 0x80000000
1482 +#define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_SHIFT 31
1483 +
1484 /* ALP clock on pre-PMU chips */
1485 #define BCMA_CC_PMU_ALP_CLOCK 20000000
1486 /* HT clock for systems with PMU-enabled chipcommon */
1487 @@ -503,6 +531,37 @@
1488 #define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE BIT(18)
1489 #define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE BIT(19)
1490
1491 +#define BCMA_RES_4314_LPLDO_PU BIT(0)
1492 +#define BCMA_RES_4314_PMU_SLEEP_DIS BIT(1)
1493 +#define BCMA_RES_4314_PMU_BG_PU BIT(2)
1494 +#define BCMA_RES_4314_CBUCK_LPOM_PU BIT(3)
1495 +#define BCMA_RES_4314_CBUCK_PFM_PU BIT(4)
1496 +#define BCMA_RES_4314_CLDO_PU BIT(5)
1497 +#define BCMA_RES_4314_LPLDO2_LVM BIT(6)
1498 +#define BCMA_RES_4314_WL_PMU_PU BIT(7)
1499 +#define BCMA_RES_4314_LNLDO_PU BIT(8)
1500 +#define BCMA_RES_4314_LDO3P3_PU BIT(9)
1501 +#define BCMA_RES_4314_OTP_PU BIT(10)
1502 +#define BCMA_RES_4314_XTAL_PU BIT(11)
1503 +#define BCMA_RES_4314_WL_PWRSW_PU BIT(12)
1504 +#define BCMA_RES_4314_LQ_AVAIL BIT(13)
1505 +#define BCMA_RES_4314_LOGIC_RET BIT(14)
1506 +#define BCMA_RES_4314_MEM_SLEEP BIT(15)
1507 +#define BCMA_RES_4314_MACPHY_RET BIT(16)
1508 +#define BCMA_RES_4314_WL_CORE_READY BIT(17)
1509 +#define BCMA_RES_4314_ILP_REQ BIT(18)
1510 +#define BCMA_RES_4314_ALP_AVAIL BIT(19)
1511 +#define BCMA_RES_4314_MISC_PWRSW_PU BIT(20)
1512 +#define BCMA_RES_4314_SYNTH_PWRSW_PU BIT(21)
1513 +#define BCMA_RES_4314_RX_PWRSW_PU BIT(22)
1514 +#define BCMA_RES_4314_RADIO_PU BIT(23)
1515 +#define BCMA_RES_4314_VCO_LDO_PU BIT(24)
1516 +#define BCMA_RES_4314_AFE_LDO_PU BIT(25)
1517 +#define BCMA_RES_4314_RX_LDO_PU BIT(26)
1518 +#define BCMA_RES_4314_TX_LDO_PU BIT(27)
1519 +#define BCMA_RES_4314_HT_AVAIL BIT(28)
1520 +#define BCMA_RES_4314_MACPHY_CLK_AVAIL BIT(29)
1521 +
1522 /* Data for the PMU, if available.
1523 * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
1524 */
1525 @@ -528,6 +587,7 @@ struct bcma_sflash {
1526 u32 size;
1527
1528 struct mtd_info *mtd;
1529 + void *priv;
1530 };
1531 #endif
1532
1533 @@ -606,6 +666,8 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct
1534
1535 extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks);
1536
1537 +extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc);
1538 +
1539 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
1540
1541 u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask);
1542 @@ -634,4 +696,6 @@ extern void bcma_chipco_regctl_maskset(s
1543 u32 offset, u32 mask, u32 set);
1544 extern void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid);
1545
1546 +extern u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc);
1547 +
1548 #endif /* LINUX_BCMA_DRIVER_CC_H_ */
1549 --- a/include/linux/bcma/bcma_driver_mips.h
1550 +++ b/include/linux/bcma/bcma_driver_mips.h
1551 @@ -28,6 +28,7 @@
1552 #define BCMA_MIPS_MIPS74K_GPIOEN 0x0048
1553 #define BCMA_MIPS_MIPS74K_CLKCTLST 0x01E0
1554
1555 +#define BCMA_MIPS_OOBSELINA74 0x004
1556 #define BCMA_MIPS_OOBSELOUTA30 0x100
1557
1558 struct bcma_device;
1559 @@ -36,19 +37,23 @@ struct bcma_drv_mips {
1560 struct bcma_device *core;
1561 u8 setup_done:1;
1562 u8 early_setup_done:1;
1563 - unsigned int assigned_irqs;
1564 };
1565
1566 #ifdef CONFIG_BCMA_DRIVER_MIPS
1567 extern void bcma_core_mips_init(struct bcma_drv_mips *mcore);
1568 extern void bcma_core_mips_early_init(struct bcma_drv_mips *mcore);
1569 +
1570 +extern unsigned int bcma_core_irq(struct bcma_device *core);
1571 #else
1572 static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { }
1573 static inline void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) { }
1574 +
1575 +static inline unsigned int bcma_core_irq(struct bcma_device *core)
1576 +{
1577 + return 0;
1578 +}
1579 #endif
1580
1581 extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore);
1582
1583 -extern unsigned int bcma_core_mips_irq(struct bcma_device *dev);
1584 -
1585 #endif /* LINUX_BCMA_DRIVER_MIPS_H_ */
1586 --- a/include/linux/bcma/bcma_driver_pci.h
1587 +++ b/include/linux/bcma/bcma_driver_pci.h
1588 @@ -179,6 +179,8 @@ struct pci_dev;
1589 #define BCMA_CORE_PCI_CFG_FUN_MASK 7 /* Function mask */
1590 #define BCMA_CORE_PCI_CFG_OFF_MASK 0xfff /* Register mask */
1591
1592 +#define BCMA_CORE_PCI_CFG_DEVCTRL 0xd8
1593 +
1594 /* PCIE Root Capability Register bits (Host mode only) */
1595 #define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001
1596
1597 --- a/include/linux/bcma/bcma_regs.h
1598 +++ b/include/linux/bcma/bcma_regs.h
1599 @@ -37,6 +37,7 @@
1600 #define BCMA_IOST_BIST_DONE 0x8000
1601 #define BCMA_RESET_CTL 0x0800
1602 #define BCMA_RESET_CTL_RESET 0x0001
1603 +#define BCMA_RESET_ST 0x0804
1604
1605 /* BCMA PCI config space registers. */
1606 #define BCMA_PCI_PMCSR 0x44
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