target/linux/generic/patches-3.8/025-bcma_backport.patch

   1 --- a/arch/mips/bcm47xx/serial.c
   2 +++ b/arch/mips/bcm47xx/serial.c
   3 @@ -62,7 +62,7 @@ static int __init uart8250_init_bcma(voi
   4
   5                 p->mapbase = (unsigned int) bcma_port->regs;
   6                 p->membase = (void *) bcma_port->regs;
   7 -               p->irq = bcma_port->irq + 2;
   8 +               p->irq = bcma_port->irq;
   9                 p->uartclk = bcma_port->baud_base;
  10                 p->regshift = bcma_port->reg_shift;
  11                 p->iotype = UPIO_MEM;
  12 --- a/drivers/bcma/bcma_private.h
  13 +++ b/drivers/bcma/bcma_private.h
  14 @@ -31,6 +31,8 @@ int __init bcma_bus_early_register(struc
  15  int bcma_bus_suspend(struct bcma_bus *bus);
  16  int bcma_bus_resume(struct bcma_bus *bus);
  17  #endif
  18 +struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
  19 +                                       u8 unit);
  20
  21  /* scan.c */
  22  int bcma_bus_scan(struct bcma_bus *bus);
  23 @@ -45,6 +47,7 @@ int bcma_sprom_get(struct bcma_bus *bus)
  24  /* driver_chipcommon.c */
  25  #ifdef CONFIG_BCMA_DRIVER_MIPS
  26  void bcma_chipco_serial_init(struct bcma_drv_cc *cc);
  27 +extern struct platform_device bcma_pflash_dev;
  28  #endif /* CONFIG_BCMA_DRIVER_MIPS */
  29
  30  /* driver_chipcommon_pmu.c */
  31 --- a/drivers/bcma/driver_chipcommon.c
  32 +++ b/drivers/bcma/driver_chipcommon.c
  33 @@ -329,7 +329,7 @@ void bcma_chipco_serial_init(struct bcma
  34                 return;
  35         }
  36
  37 -       irq = bcma_core_mips_irq(cc->core);
  38 +       irq = bcma_core_irq(cc->core);
  39
  40         /* Determine the registers of the UARTs */
  41         cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART);
  42 --- a/drivers/bcma/driver_chipcommon_nflash.c
  43 +++ b/drivers/bcma/driver_chipcommon_nflash.c
  44 @@ -5,11 +5,11 @@
  45   * Licensed under the GNU/GPL. See COPYING for details.
  46   */
  47
  48 +#include "bcma_private.h"
  49 +
  50  #include <linux/platform_device.h>
  51  #include <linux/bcma/bcma.h>
  52
  53 -#include "bcma_private.h"
  54 -
  55  struct platform_device bcma_nflash_dev = {
  56         .name           = "bcma_nflash",
  57         .num_resources  = 0,
  58 --- a/drivers/bcma/driver_chipcommon_sflash.c
  59 +++ b/drivers/bcma/driver_chipcommon_sflash.c
  60 @@ -5,11 +5,11 @@
  61   * Licensed under the GNU/GPL. See COPYING for details.
  62   */
  63
  64 +#include "bcma_private.h"
  65 +
  66  #include <linux/platform_device.h>
  67  #include <linux/bcma/bcma.h>
  68
  69 -#include "bcma_private.h"
  70 -
  71  static struct resource bcma_sflash_resource = {
  72         .name   = "bcma_sflash",
  73         .start  = BCMA_SOC_FLASH2,
  74 --- a/drivers/bcma/driver_gpio.c
  75 +++ b/drivers/bcma/driver_gpio.c
  76 @@ -73,6 +73,16 @@ static void bcma_gpio_free(struct gpio_c
  77         bcma_chipco_gpio_pullup(cc, 1 << gpio, 0);
  78  }
  79
  80 +static int bcma_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
  81 +{
  82 +       struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
  83 +
  84 +       if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
  85 +               return bcma_core_irq(cc->core);
  86 +       else
  87 +               return -EINVAL;
  88 +}
  89 +
  90  int bcma_gpio_init(struct bcma_drv_cc *cc)
  91  {
  92         struct gpio_chip *chip = &cc->gpio;
  93 @@ -85,6 +95,7 @@ int bcma_gpio_init(struct bcma_drv_cc *c
  94         chip->set               = bcma_gpio_set_value;
  95         chip->direction_input   = bcma_gpio_direction_input;
  96         chip->direction_output  = bcma_gpio_direction_output;
  97 +       chip->to_irq            = bcma_gpio_to_irq;
  98         chip->ngpio             = 16;
  99         /* There is just one SoC in one device and its GPIO addresses should be
 100          * deterministic to address them more easily. The other buses could get
 101 --- a/drivers/bcma/driver_mips.c
 102 +++ b/drivers/bcma/driver_mips.c
 103 @@ -14,11 +14,33 @@
 104
 105  #include <linux/bcma/bcma.h>
 106
 107 +#include <linux/mtd/physmap.h>
 108 +#include <linux/platform_device.h>
 109  #include <linux/serial.h>
 110  #include <linux/serial_core.h>
 111  #include <linux/serial_reg.h>
 112  #include <linux/time.h>
 113
 114 +static const char *part_probes[] = { "bcm47xxpart", NULL };
 115 +
 116 +static struct physmap_flash_data bcma_pflash_data = {
 117 +       .part_probe_types       = part_probes,
 118 +};
 119 +
 120 +static struct resource bcma_pflash_resource = {
 121 +       .name   = "bcma_pflash",
 122 +       .flags  = IORESOURCE_MEM,
 123 +};
 124 +
 125 +struct platform_device bcma_pflash_dev = {
 126 +       .name           = "physmap-flash",
 127 +       .dev            = {
 128 +               .platform_data  = &bcma_pflash_data,
 129 +       },
 130 +       .resource       = &bcma_pflash_resource,
 131 +       .num_resources  = 1,
 132 +};
 133 +
 134  /* The 47162a0 hangs when reading MIPS DMP registers registers */
 135  static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev)
 136  {
 137 @@ -74,28 +96,41 @@ static u32 bcma_core_mips_irqflag(struct
 138                 return dev->core_index;
 139         flag = bcma_aread32(dev, BCMA_MIPS_OOBSELOUTA30);
 140
 141 -       return flag & 0x1F;
 142 +       if (flag)
 143 +               return flag & 0x1F;
 144 +       else
 145 +               return 0x3f;
 146  }
 147
 148  /* Get the MIPS IRQ assignment for a specified device.
 149   * If unassigned, 0 is returned.
 150 + * If disabled, 5 is returned.
 151 + * If not supported, 6 is returned.
 152   */
 153 -unsigned int bcma_core_mips_irq(struct bcma_device *dev)
 154 +static unsigned int bcma_core_mips_irq(struct bcma_device *dev)
 155  {
 156         struct bcma_device *mdev = dev->bus->drv_mips.core;
 157         u32 irqflag;
 158         unsigned int irq;
 159
 160         irqflag = bcma_core_mips_irqflag(dev);
 161 +       if (irqflag == 0x3f)
 162 +               return 6;
 163
 164 -       for (irq = 1; irq <= 4; irq++)
 165 +       for (irq = 0; irq <= 4; irq++)
 166                 if (bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq)) &
 167                     (1 << irqflag))
 168                         return irq;
 169
 170 -       return 0;
 171 +       return 5;
 172  }
 173 -EXPORT_SYMBOL(bcma_core_mips_irq);
 174 +
 175 +unsigned int bcma_core_irq(struct bcma_device *dev)
 176 +{
 177 +       unsigned int mips_irq = bcma_core_mips_irq(dev);
 178 +       return mips_irq <= 4 ? mips_irq + 2 : 0;
 179 +}
 180 +EXPORT_SYMBOL(bcma_core_irq);
 181
 182  static void bcma_core_mips_set_irq(struct bcma_device *dev, unsigned int irq)
 183  {
 184 @@ -114,7 +149,7 @@ static void bcma_core_mips_set_irq(struc
 185                 bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0),
 186                             bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) &
 187                             ~(1 << irqflag));
 188 -       else
 189 +       else if (oldirq != 5)
 190                 bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(oldirq), 0);
 191
 192         /* assign the new one */
 193 @@ -123,9 +158,9 @@ static void bcma_core_mips_set_irq(struc
 194                             bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) |
 195                             (1 << irqflag));
 196         } else {
 197 -               u32 oldirqflag = bcma_read32(mdev,
 198 -                                            BCMA_MIPS_MIPS74K_INTMASK(irq));
 199 -               if (oldirqflag) {
 200 +               u32 irqinitmask = bcma_read32(mdev,
 201 +                                             BCMA_MIPS_MIPS74K_INTMASK(irq));
 202 +               if (irqinitmask) {
 203                         struct bcma_device *core;
 204
 205                         /* backplane irq line is in use, find out who uses
 206 @@ -133,7 +168,7 @@ static void bcma_core_mips_set_irq(struc
 207                          */
 208                         list_for_each_entry(core, &bus->cores, list) {
 209                                 if ((1 << bcma_core_mips_irqflag(core)) ==
 210 -                                   oldirqflag) {
 211 +                                   irqinitmask) {
 212                                         bcma_core_mips_set_irq(core, 0);
 213                                         break;
 214                                 }
 215 @@ -143,15 +178,31 @@ static void bcma_core_mips_set_irq(struc
 216                              1 << irqflag);
 217         }
 218
 219 -       bcma_info(bus, "set_irq: core 0x%04x, irq %d => %d\n",
 220 -                 dev->id.id, oldirq + 2, irq + 2);
 221 +       bcma_debug(bus, "set_irq: core 0x%04x, irq %d => %d\n",
 222 +                  dev->id.id, oldirq <= 4 ? oldirq + 2 : 0, irq + 2);
 223 +}
 224 +
 225 +static void bcma_core_mips_set_irq_name(struct bcma_bus *bus, unsigned int irq,
 226 +                                       u16 coreid, u8 unit)
 227 +{
 228 +       struct bcma_device *core;
 229 +
 230 +       core = bcma_find_core_unit(bus, coreid, unit);
 231 +       if (!core) {
 232 +               bcma_warn(bus,
 233 +                         "Can not find core (id: 0x%x, unit %i) for IRQ configuration.\n",
 234 +                         coreid, unit);
 235 +               return;
 236 +       }
 237 +
 238 +       bcma_core_mips_set_irq(core, irq);
 239  }
 240
 241  static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq)
 242  {
 243         int i;
 244         static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
 245 -       printk(KERN_INFO KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
 246 +       printk(KERN_DEBUG KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
 247         for (i = 0; i <= 6; i++)
 248                 printk(" %s%s", irq_name[i], i == irq ? "*" : " ");
 249         printk("\n");
 250 @@ -182,6 +233,7 @@ static void bcma_core_mips_flash_detect(
 251  {
 252         struct bcma_bus *bus = mcore->core->bus;
 253         struct bcma_drv_cc *cc = &bus->drv_cc;
 254 +       struct bcma_pflash *pflash = &cc->pflash;
 255
 256         switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
 257         case BCMA_CC_FLASHT_STSER:
 258 @@ -191,15 +243,20 @@ static void bcma_core_mips_flash_detect(
 259                 break;
 260         case BCMA_CC_FLASHT_PARA:
 261                 bcma_debug(bus, "Found parallel flash\n");
 262 -               cc->pflash.present = true;
 263 -               cc->pflash.window = BCMA_SOC_FLASH2;
 264 -               cc->pflash.window_size = BCMA_SOC_FLASH2_SZ;
 265 +               pflash->present = true;
 266 +               pflash->window = BCMA_SOC_FLASH2;
 267 +               pflash->window_size = BCMA_SOC_FLASH2_SZ;
 268
 269                 if ((bcma_read32(cc->core, BCMA_CC_FLASH_CFG) &
 270                      BCMA_CC_FLASH_CFG_DS) == 0)
 271 -                       cc->pflash.buswidth = 1;
 272 +                       pflash->buswidth = 1;
 273                 else
 274 -                       cc->pflash.buswidth = 2;
 275 +                       pflash->buswidth = 2;
 276 +
 277 +               bcma_pflash_data.width = pflash->buswidth;
 278 +               bcma_pflash_resource.start = pflash->window;
 279 +               bcma_pflash_resource.end = pflash->window + pflash->window_size;
 280 +
 281                 break;
 282         default:
 283                 bcma_err(bus, "Flash type not supported\n");
 284 @@ -227,6 +284,32 @@ void bcma_core_mips_early_init(struct bc
 285         mcore->early_setup_done = true;
 286  }
 287
 288 +static void bcma_fix_i2s_irqflag(struct bcma_bus *bus)
 289 +{
 290 +       struct bcma_device *cpu, *pcie, *i2s;
 291 +
 292 +       /* Fixup the interrupts in 4716/4748 for i2s core (2010 Broadcom SDK)
 293 +        * (IRQ flags > 7 are ignored when setting the interrupt masks)
 294 +        */
 295 +       if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4716 &&
 296 +           bus->chipinfo.id != BCMA_CHIP_ID_BCM4748)
 297 +               return;
 298 +
 299 +       cpu = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
 300 +       pcie = bcma_find_core(bus, BCMA_CORE_PCIE);
 301 +       i2s = bcma_find_core(bus, BCMA_CORE_I2S);
 302 +       if (cpu && pcie && i2s &&
 303 +           bcma_aread32(cpu, BCMA_MIPS_OOBSELINA74) == 0x08060504 &&
 304 +           bcma_aread32(pcie, BCMA_MIPS_OOBSELINA74) == 0x08060504 &&
 305 +           bcma_aread32(i2s, BCMA_MIPS_OOBSELOUTA30) == 0x88) {
 306 +               bcma_awrite32(cpu, BCMA_MIPS_OOBSELINA74, 0x07060504);
 307 +               bcma_awrite32(pcie, BCMA_MIPS_OOBSELINA74, 0x07060504);
 308 +               bcma_awrite32(i2s, BCMA_MIPS_OOBSELOUTA30, 0x87);
 309 +               bcma_debug(bus,
 310 +                          "Moved i2s interrupt to oob line 7 instead of 8\n");
 311 +       }
 312 +}
 313 +
 314  void bcma_core_mips_init(struct bcma_drv_mips *mcore)
 315  {
 316         struct bcma_bus *bus;
 317 @@ -236,43 +319,55 @@ void bcma_core_mips_init(struct bcma_drv
 318         if (mcore->setup_done)
 319                 return;
 320
 321 -       bcma_info(bus, "Initializing MIPS core...\n");
 322 +       bcma_debug(bus, "Initializing MIPS core...\n");
 323
 324         bcma_core_mips_early_init(mcore);
 325
 326 -       mcore->assigned_irqs = 1;
 327 +       bcma_fix_i2s_irqflag(bus);
 328
 329 -       /* Assign IRQs to all cores on the bus */
 330 -       list_for_each_entry(core, &bus->cores, list) {
 331 -               int mips_irq;
 332 -               if (core->irq)
 333 -                       continue;
 334 -
 335 -               mips_irq = bcma_core_mips_irq(core);
 336 -               if (mips_irq > 4)
 337 -                       core->irq = 0;
 338 -               else
 339 -                       core->irq = mips_irq + 2;
 340 -               if (core->irq > 5)
 341 -                       continue;
 342 -               switch (core->id.id) {
 343 -               case BCMA_CORE_PCI:
 344 -               case BCMA_CORE_PCIE:
 345 -               case BCMA_CORE_ETHERNET:
 346 -               case BCMA_CORE_ETHERNET_GBIT:
 347 -               case BCMA_CORE_MAC_GBIT:
 348 -               case BCMA_CORE_80211:
 349 -               case BCMA_CORE_USB20_HOST:
 350 -                       /* These devices get their own IRQ line if available,
 351 -                        * the rest goes on IRQ0
 352 -                        */
 353 -                       if (mcore->assigned_irqs <= 4)
 354 -                               bcma_core_mips_set_irq(core,
 355 -                                                      mcore->assigned_irqs++);
 356 -                       break;
 357 +       switch (bus->chipinfo.id) {
 358 +       case BCMA_CHIP_ID_BCM4716:
 359 +       case BCMA_CHIP_ID_BCM4748:
 360 +               bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
 361 +               bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
 362 +               bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
 363 +               bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_PCIE, 0);
 364 +               bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
 365 +               bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
 366 +               break;
 367 +       case BCMA_CHIP_ID_BCM5356:
 368 +       case BCMA_CHIP_ID_BCM47162:
 369 +       case BCMA_CHIP_ID_BCM53572:
 370 +               bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
 371 +               bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
 372 +               bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
 373 +               break;
 374 +       case BCMA_CHIP_ID_BCM5357:
 375 +       case BCMA_CHIP_ID_BCM4749:
 376 +               bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
 377 +               bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
 378 +               bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
 379 +               bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
 380 +               bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
 381 +               break;
 382 +       case BCMA_CHIP_ID_BCM4706:
 383 +               bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_PCIE, 0);
 384 +               bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_4706_MAC_GBIT,
 385 +                                           0);
 386 +               bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_PCIE, 1);
 387 +               bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_USB20_HOST, 0);
 388 +               bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_4706_CHIPCOMMON,
 389 +                                           0);
 390 +               break;
 391 +       default:
 392 +               list_for_each_entry(core, &bus->cores, list) {
 393 +                       core->irq = bcma_core_irq(core);
 394                 }
 395 +               bcma_err(bus,
 396 +                        "Unknown device (0x%x) found, can not configure IRQs\n",
 397 +                        bus->chipinfo.id);
 398         }
 399 -       bcma_info(bus, "IRQ reconfiguration done\n");
 400 +       bcma_debug(bus, "IRQ reconfiguration done\n");
 401         bcma_core_mips_dump_irq(bus);
 402
 403         mcore->setup_done = true;
 404 --- a/drivers/bcma/driver_pci_host.c
 405 +++ b/drivers/bcma/driver_pci_host.c
 406 @@ -94,19 +94,19 @@ static int bcma_extpci_read_config(struc
 407         if (dev == 0) {
 408                 /* we support only two functions on device 0 */
 409                 if (func > 1)
 410 -                       return -EINVAL;
 411 +                       goto out;
 412
 413                 /* accesses to config registers with offsets >= 256
 414                  * requires indirect access.
 415                  */
 416                 if (off >= PCI_CONFIG_SPACE_SIZE) {
 417                         addr = (func << 12);
 418 -                       addr |= (off & 0x0FFF);
 419 +                       addr |= (off & 0x0FFC);
 420                         val = bcma_pcie_read_config(pc, addr);
 421                 } else {
 422                         addr = BCMA_CORE_PCI_PCICFG0;
 423                         addr |= (func << 8);
 424 -                       addr |= (off & 0xfc);
 425 +                       addr |= (off & 0xFC);
 426                         val = pcicore_read32(pc, addr);
 427                 }
 428         } else {
 429 @@ -119,11 +119,9 @@ static int bcma_extpci_read_config(struc
 430                         goto out;
 431
 432                 if (mips_busprobe32(val, mmio)) {
 433 -                       val = 0xffffffff;
 434 +                       val = 0xFFFFFFFF;
 435                         goto unmap;
 436                 }
 437 -
 438 -               val = readl(mmio);
 439         }
 440         val >>= (8 * (off & 3));
 441
 442 @@ -151,7 +149,7 @@ static int bcma_extpci_write_config(stru
 443                                    const void *buf, int len)
 444  {
 445         int err = -EINVAL;
 446 -       u32 addr = 0, val = 0;
 447 +       u32 addr, val;
 448         void __iomem *mmio = 0;
 449         u16 chipid = pc->core->bus->chipinfo.id;
 450
 451 @@ -159,16 +157,22 @@ static int bcma_extpci_write_config(stru
 452         if (unlikely(len != 1 && len != 2 && len != 4))
 453                 goto out;
 454         if (dev == 0) {
 455 +               /* we support only two functions on device 0 */
 456 +               if (func > 1)
 457 +                       goto out;
 458 +
 459                 /* accesses to config registers with offsets >= 256
 460                  * requires indirect access.
 461                  */
 462 -               if (off < PCI_CONFIG_SPACE_SIZE) {
 463 -                       addr = pc->core->addr + BCMA_CORE_PCI_PCICFG0;
 464 +               if (off >= PCI_CONFIG_SPACE_SIZE) {
 465 +                       addr = (func << 12);
 466 +                       addr |= (off & 0x0FFC);
 467 +                       val = bcma_pcie_read_config(pc, addr);
 468 +               } else {
 469 +                       addr = BCMA_CORE_PCI_PCICFG0;
 470                         addr |= (func << 8);
 471 -                       addr |= (off & 0xfc);
 472 -                       mmio = ioremap_nocache(addr, sizeof(val));
 473 -                       if (!mmio)
 474 -                               goto out;
 475 +                       addr |= (off & 0xFC);
 476 +                       val = pcicore_read32(pc, addr);
 477                 }
 478         } else {
 479                 addr = bcma_get_cfgspace_addr(pc, dev, func, off);
 480 @@ -180,19 +184,17 @@ static int bcma_extpci_write_config(stru
 481                         goto out;
 482
 483                 if (mips_busprobe32(val, mmio)) {
 484 -                       val = 0xffffffff;
 485 +                       val = 0xFFFFFFFF;
 486                         goto unmap;
 487                 }
 488         }
 489
 490         switch (len) {
 491         case 1:
 492 -               val = readl(mmio);
 493                 val &= ~(0xFF << (8 * (off & 3)));
 494                 val |= *((const u8 *)buf) << (8 * (off & 3));
 495                 break;
 496         case 2:
 497 -               val = readl(mmio);
 498                 val &= ~(0xFFFF << (8 * (off & 3)));
 499                 val |= *((const u16 *)buf) << (8 * (off & 3));
 500                 break;
 501 @@ -200,13 +202,14 @@ static int bcma_extpci_write_config(stru
 502                 val = *((const u32 *)buf);
 503                 break;
 504         }
 505 -       if (dev == 0 && !addr) {
 506 +       if (dev == 0) {
 507                 /* accesses to config registers with offsets >= 256
 508                  * requires indirect access.
 509                  */
 510 -               addr = (func << 12);
 511 -               addr |= (off & 0x0FFF);
 512 -               bcma_pcie_write_config(pc, addr, val);
 513 +               if (off >= PCI_CONFIG_SPACE_SIZE)
 514 +                       bcma_pcie_write_config(pc, addr, val);
 515 +               else
 516 +                       pcicore_write32(pc, addr, val);
 517         } else {
 518                 writel(val, mmio);
 519
 520 @@ -276,7 +279,7 @@ static u8 bcma_find_pci_capability(struc
 521         /* check for Header type 0 */
 522         bcma_extpci_read_config(pc, dev, func, PCI_HEADER_TYPE, &byte_val,
 523                                 sizeof(u8));
 524 -       if ((byte_val & 0x7f) != PCI_HEADER_TYPE_NORMAL)
 525 +       if ((byte_val & 0x7F) != PCI_HEADER_TYPE_NORMAL)
 526                 return cap_ptr;
 527
 528         /* check if the capability pointer field exists */
 529 @@ -426,7 +429,7 @@ void bcma_core_pci_hostmode_init(struct
 530         /* Reset RC */
 531         usleep_range(3000, 5000);
 532         pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE);
 533 -       usleep_range(1000, 2000);
 534 +       msleep(50);
 535         pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST |
 536                         BCMA_CORE_PCI_CTL_RST_OE);
 537
 538 @@ -488,6 +491,17 @@ void bcma_core_pci_hostmode_init(struct
 539
 540         bcma_core_pci_enable_crs(pc);
 541
 542 +       if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706 ||
 543 +           bus->chipinfo.id == BCMA_CHIP_ID_BCM4716) {
 544 +               u16 val16;
 545 +               bcma_extpci_read_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL,
 546 +                                       &val16, sizeof(val16));
 547 +               val16 |= (2 << 5);      /* Max payload size of 512 */
 548 +               val16 |= (2 << 12);     /* MRRS 512 */
 549 +               bcma_extpci_write_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL,
 550 +                                        &val16, sizeof(val16));
 551 +       }
 552 +
 553         /* Enable PCI bridge BAR0 memory & master access */
 554         tmp = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 555         bcma_extpci_write_config(pc, 0, 0, PCI_COMMAND, &tmp, sizeof(tmp));
 556 @@ -576,7 +590,7 @@ int bcma_core_pci_plat_dev_init(struct p
 557         pr_info("PCI: Fixing up device %s\n", pci_name(dev));
 558
 559         /* Fix up interrupt lines */
 560 -       dev->irq = bcma_core_mips_irq(pc_host->pdev->core) + 2;
 561 +       dev->irq = bcma_core_irq(pc_host->pdev->core);
 562         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
 563
 564         return 0;
 565 @@ -595,6 +609,6 @@ int bcma_core_pci_pcibios_map_irq(const
 566
 567         pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
 568                                pci_ops);
 569 -       return bcma_core_mips_irq(pc_host->pdev->core) + 2;
 570 +       return bcma_core_irq(pc_host->pdev->core);
 571  }
 572  EXPORT_SYMBOL(bcma_core_pci_pcibios_map_irq);
 573 --- a/drivers/bcma/main.c
 574 +++ b/drivers/bcma/main.c
 575 @@ -81,8 +81,8 @@ struct bcma_device *bcma_find_core(struc
 576  }
 577  EXPORT_SYMBOL_GPL(bcma_find_core);
 578
 579 -static struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
 580 -                                              u8 unit)
 581 +struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
 582 +                                       u8 unit)
 583  {
 584         struct bcma_device *core;
 585
 586 @@ -149,6 +149,14 @@ static int bcma_register_cores(struct bc
 587                 dev_id++;
 588         }
 589
 590 +#ifdef CONFIG_BCMA_DRIVER_MIPS
 591 +       if (bus->drv_cc.pflash.present) {
 592 +               err = platform_device_register(&bcma_pflash_dev);
 593 +               if (err)
 594 +                       bcma_err(bus, "Error registering parallel flash\n");
 595 +       }
 596 +#endif
 597 +
 598  #ifdef CONFIG_BCMA_SFLASH
 599         if (bus->drv_cc.sflash.present) {
 600                 err = platform_device_register(&bcma_sflash_dev);
 601 --- a/include/linux/bcma/bcma_driver_chipcommon.h
 602 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
 603 @@ -27,7 +27,7 @@
 604  #define   BCMA_CC_FLASHT_NONE          0x00000000      /* No flash */
 605  #define   BCMA_CC_FLASHT_STSER         0x00000100      /* ST serial flash */
 606  #define   BCMA_CC_FLASHT_ATSER         0x00000200      /* Atmel serial flash */
 607 -#define   BCMA_CC_FLASHT_NFLASH                0x00000200      /* NAND flash */
 608 +#define   BCMA_CC_FLASHT_NAND          0x00000300      /* NAND flash */
 609  #define          BCMA_CC_FLASHT_PARA           0x00000700      /* Parallel flash */
 610  #define  BCMA_CC_CAP_PLLT              0x00038000      /* PLL Type */
 611  #define   BCMA_PLLTYPE_NONE            0x00000000
 612 --- a/include/linux/bcma/bcma_driver_mips.h
 613 +++ b/include/linux/bcma/bcma_driver_mips.h
 614 @@ -28,6 +28,7 @@
 615  #define BCMA_MIPS_MIPS74K_GPIOEN       0x0048
 616  #define BCMA_MIPS_MIPS74K_CLKCTLST     0x01E0
 617
 618 +#define BCMA_MIPS_OOBSELINA74          0x004
 619  #define BCMA_MIPS_OOBSELOUTA30         0x100
 620
 621  struct bcma_device;
 622 @@ -36,19 +37,23 @@ struct bcma_drv_mips {
 623         struct bcma_device *core;
 624         u8 setup_done:1;
 625         u8 early_setup_done:1;
 626 -       unsigned int assigned_irqs;
 627  };
 628
 629  #ifdef CONFIG_BCMA_DRIVER_MIPS
 630  extern void bcma_core_mips_init(struct bcma_drv_mips *mcore);
 631  extern void bcma_core_mips_early_init(struct bcma_drv_mips *mcore);
 632 +
 633 +extern unsigned int bcma_core_irq(struct bcma_device *core);
 634  #else
 635  static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { }
 636  static inline void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) { }
 637 +
 638 +static inline unsigned int bcma_core_irq(struct bcma_device *core)
 639 +{
 640 +       return 0;
 641 +}
 642  #endif
 643
 644  extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore);
 645
 646 -extern unsigned int bcma_core_mips_irq(struct bcma_device *dev);
 647 -
 648  #endif /* LINUX_BCMA_DRIVER_MIPS_H_ */
 649 --- a/include/linux/bcma/bcma_driver_pci.h
 650 +++ b/include/linux/bcma/bcma_driver_pci.h
 651 @@ -179,6 +179,8 @@ struct pci_dev;
 652  #define BCMA_CORE_PCI_CFG_FUN_MASK             7       /* Function mask */
 653  #define BCMA_CORE_PCI_CFG_OFF_MASK             0xfff   /* Register mask */
 654
 655 +#define BCMA_CORE_PCI_CFG_DEVCTRL              0xd8
 656 +
 657  /* PCIE Root Capability Register bits (Host mode only) */
 658  #define BCMA_CORE_PCI_RC_CRS_VISIBILITY                0x0001
 659