0b17f77eef451172f4138203416c09214c24cfc2
[openwrt/staging/dedeckeh.git] / target / linux / generic / pending-5.15 / 728-net-mtk_sgmii-set-the-speed-according-to-the-phy-int.patch
1 From 952b64575613d26163a5afa5ff8bfdb57840091b Mon Sep 17 00:00:00 2001
2 From: Alexander Couzens <lynxis@fe80.eu>
3 Date: Mon, 15 Aug 2022 15:00:14 +0200
4 Subject: [PATCH 08/10] net: mtk_sgmii: set the speed according to the phy
5 interface in AN
6
7 The non auto-negotioting code path is setting the correct speed for the
8 interface. Ensure auto-negotiation code path is doing it as well.
9
10 Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
11 ---
12 drivers/net/ethernet/mediatek/mtk_sgmii.c | 11 +++++++++--
13 1 file changed, 9 insertions(+), 2 deletions(-)
14
15 --- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
16 +++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
17 @@ -21,13 +21,20 @@ static struct mtk_pcs *pcs_to_mtk_pcs(st
18 }
19
20 /* For SGMII interface mode */
21 -static int mtk_pcs_setup_mode_an(struct mtk_pcs *mpcs)
22 +static int mtk_pcs_setup_mode_an(struct mtk_pcs *mpcs, phy_interface_t interface)
23 {
24 unsigned int val;
25
26 /* PHYA power down */
27 regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD);
28
29 + /* Set SGMII phy speed */
30 + regmap_read(mpcs->regmap, mpcs->ana_rgc3, &val);
31 + val &= ~RG_PHY_SPEED_MASK;
32 + if (interface == PHY_INTERFACE_MODE_2500BASEX)
33 + val |= RG_PHY_SPEED_3_125G;
34 + regmap_write(mpcs->regmap, mpcs->ana_rgc3, val);
35 +
36 /* Setup the link timer and QPHY power up inside SGMIISYS */
37 regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER,
38 SGMII_LINK_TIMER_DEFAULT);
39 @@ -100,7 +107,7 @@ static int mtk_pcs_config(struct phylink
40 if (interface != PHY_INTERFACE_MODE_SGMII)
41 err = mtk_pcs_setup_mode_force(mpcs, interface);
42 else if (phylink_autoneg_inband(mode))
43 - err = mtk_pcs_setup_mode_an(mpcs);
44 + err = mtk_pcs_setup_mode_an(mpcs, interface);
45
46 return err;
47 }