1 From: Sujuan Chen <sujuan.chen@mediatek.com>
2 Date: Sat, 5 Nov 2022 23:36:18 +0100
3 Subject: [PATCH] net: ethernet: mtk_wed: introduce wed mcu support
5 Introduce WED mcu support used to configure WED WO chip.
6 This is a preliminary patch in order to add RX Wireless
7 Ethernet Dispatch available on MT7986 SoC.
9 Tested-by: Daniel Golle <daniel@makrotopia.org>
10 Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>
11 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
12 Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
13 Signed-off-by: David S. Miller <davem@davemloft.net>
15 create mode 100644 drivers/net/ethernet/mediatek/mtk_wed_mcu.c
16 create mode 100644 drivers/net/ethernet/mediatek/mtk_wed_wo.h
18 --- a/drivers/net/ethernet/mediatek/Makefile
19 +++ b/drivers/net/ethernet/mediatek/Makefile
22 obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o
23 mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_eth_path.o mtk_ppe.o mtk_ppe_debugfs.o mtk_ppe_offload.o
24 -mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed.o
25 +mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed.o mtk_wed_mcu.o
27 mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed_debugfs.o
30 +++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
32 +// SPDX-License-Identifier: GPL-2.0-only
33 +/* Copyright (C) 2022 MediaTek Inc.
35 + * Author: Lorenzo Bianconi <lorenzo@kernel.org>
36 + * Sujuan Chen <sujuan.chen@mediatek.com>
39 +#include <linux/firmware.h>
40 +#include <linux/of_address.h>
41 +#include <linux/of_reserved_mem.h>
42 +#include <linux/mfd/syscon.h>
43 +#include <linux/soc/mediatek/mtk_wed.h>
45 +#include "mtk_wed_regs.h"
46 +#include "mtk_wed_wo.h"
49 +static u32 wo_r32(struct mtk_wed_wo *wo, u32 reg)
51 + return readl(wo->boot.addr + reg);
54 +static void wo_w32(struct mtk_wed_wo *wo, u32 reg, u32 val)
56 + writel(val, wo->boot.addr + reg);
59 +static struct sk_buff *
60 +mtk_wed_mcu_msg_alloc(const void *data, int data_len)
62 + int length = sizeof(struct mtk_wed_mcu_hdr) + data_len;
63 + struct sk_buff *skb;
65 + skb = alloc_skb(length, GFP_KERNEL);
69 + memset(skb->head, 0, length);
70 + skb_reserve(skb, sizeof(struct mtk_wed_mcu_hdr));
71 + if (data && data_len)
72 + skb_put_data(skb, data, data_len);
77 +static struct sk_buff *
78 +mtk_wed_mcu_get_response(struct mtk_wed_wo *wo, unsigned long expires)
80 + if (!time_is_after_jiffies(expires))
83 + wait_event_timeout(wo->mcu.wait, !skb_queue_empty(&wo->mcu.res_q),
85 + return skb_dequeue(&wo->mcu.res_q);
88 +void mtk_wed_mcu_rx_event(struct mtk_wed_wo *wo, struct sk_buff *skb)
90 + skb_queue_tail(&wo->mcu.res_q, skb);
91 + wake_up(&wo->mcu.wait);
94 +void mtk_wed_mcu_rx_unsolicited_event(struct mtk_wed_wo *wo,
95 + struct sk_buff *skb)
97 + struct mtk_wed_mcu_hdr *hdr = (struct mtk_wed_mcu_hdr *)skb->data;
100 + case MTK_WED_WO_EVT_LOG_DUMP: {
101 + const char *msg = (const char *)(skb->data + sizeof(*hdr));
103 + dev_notice(wo->hw->dev, "%s\n", msg);
106 + case MTK_WED_WO_EVT_PROFILING: {
107 + struct mtk_wed_wo_log_info *info;
108 + u32 count = (skb->len - sizeof(*hdr)) / sizeof(*info);
111 + info = (struct mtk_wed_wo_log_info *)(skb->data + sizeof(*hdr));
112 + for (i = 0 ; i < count ; i++)
113 + dev_notice(wo->hw->dev,
114 + "SN:%u latency: total=%u, rro:%u, mod:%u\n",
115 + le32_to_cpu(info[i].sn),
116 + le32_to_cpu(info[i].total),
117 + le32_to_cpu(info[i].rro),
118 + le32_to_cpu(info[i].mod));
121 + case MTK_WED_WO_EVT_RXCNT_INFO:
127 + dev_kfree_skb(skb);
131 +mtk_wed_mcu_skb_send_msg(struct mtk_wed_wo *wo, struct sk_buff *skb,
132 + int id, int cmd, u16 *wait_seq, bool wait_resp)
134 + struct mtk_wed_mcu_hdr *hdr;
136 + /* TODO: make it dynamic based on cmd */
137 + wo->mcu.timeout = 20 * HZ;
139 + hdr = (struct mtk_wed_mcu_hdr *)skb_push(skb, sizeof(*hdr));
141 + hdr->length = cpu_to_le16(skb->len);
143 + if (wait_resp && wait_seq) {
144 + u16 seq = ++wo->mcu.seq;
147 + seq = ++wo->mcu.seq;
150 + hdr->flag |= cpu_to_le16(MTK_WED_WARP_CMD_FLAG_NEED_RSP);
151 + hdr->seq = cpu_to_le16(seq);
153 + if (id == MTK_WED_MODULE_ID_WO)
154 + hdr->flag |= cpu_to_le16(MTK_WED_WARP_CMD_FLAG_FROM_TO_WO);
156 + dev_kfree_skb(skb);
161 +mtk_wed_mcu_parse_response(struct mtk_wed_wo *wo, struct sk_buff *skb,
164 + struct mtk_wed_mcu_hdr *hdr;
167 + dev_err(wo->hw->dev, "Message %08x (seq %d) timeout\n",
172 + hdr = (struct mtk_wed_mcu_hdr *)skb->data;
173 + if (le16_to_cpu(hdr->seq) != seq)
176 + skb_pull(skb, sizeof(*hdr));
178 + case MTK_WED_WO_CMD_RXCNT_INFO:
186 +int mtk_wed_mcu_send_msg(struct mtk_wed_wo *wo, int id, int cmd,
187 + const void *data, int len, bool wait_resp)
189 + unsigned long expires;
190 + struct sk_buff *skb;
194 + skb = mtk_wed_mcu_msg_alloc(data, len);
198 + mutex_lock(&wo->mcu.mutex);
200 + ret = mtk_wed_mcu_skb_send_msg(wo, skb, id, cmd, &seq, wait_resp);
201 + if (ret || !wait_resp)
204 + expires = jiffies + wo->mcu.timeout;
206 + skb = mtk_wed_mcu_get_response(wo, expires);
207 + ret = mtk_wed_mcu_parse_response(wo, skb, cmd, seq);
208 + dev_kfree_skb(skb);
209 + } while (ret == -EAGAIN);
212 + mutex_unlock(&wo->mcu.mutex);
218 +mtk_wed_get_memory_region(struct mtk_wed_wo *wo,
219 + struct mtk_wed_wo_memory_region *region)
221 + struct reserved_mem *rmem;
222 + struct device_node *np;
225 + index = of_property_match_string(wo->hw->node, "memory-region-names",
230 + np = of_parse_phandle(wo->hw->node, "memory-region", index);
234 + rmem = of_reserved_mem_lookup(np);
240 + region->phy_addr = rmem->base;
241 + region->size = rmem->size;
242 + region->addr = devm_ioremap(wo->hw->dev, region->phy_addr, region->size);
244 + return !region->addr ? -EINVAL : 0;
248 +mtk_wed_mcu_run_firmware(struct mtk_wed_wo *wo, const struct firmware *fw,
249 + struct mtk_wed_wo_memory_region *region)
251 + const u8 *first_region_ptr, *region_ptr, *trailer_ptr, *ptr = fw->data;
252 + const struct mtk_wed_fw_trailer *trailer;
253 + const struct mtk_wed_fw_region *fw_region;
255 + trailer_ptr = fw->data + fw->size - sizeof(*trailer);
256 + trailer = (const struct mtk_wed_fw_trailer *)trailer_ptr;
257 + region_ptr = trailer_ptr - trailer->num_region * sizeof(*fw_region);
258 + first_region_ptr = region_ptr;
260 + while (region_ptr < trailer_ptr) {
263 + fw_region = (const struct mtk_wed_fw_region *)region_ptr;
264 + length = le32_to_cpu(fw_region->len);
266 + if (region->phy_addr != le32_to_cpu(fw_region->addr))
269 + if (region->size < length)
272 + if (first_region_ptr < ptr + length)
275 + if (region->shared && region->consumed)
278 + if (!region->shared || !region->consumed) {
279 + memcpy_toio(region->addr, ptr, length);
280 + region->consumed = true;
284 + region_ptr += sizeof(*fw_region);
292 +mtk_wed_mcu_load_firmware(struct mtk_wed_wo *wo)
294 + static struct mtk_wed_wo_memory_region mem_region[] = {
295 + [MTK_WED_WO_REGION_EMI] = {
298 + [MTK_WED_WO_REGION_ILM] = {
301 + [MTK_WED_WO_REGION_DATA] = {
306 + const struct mtk_wed_fw_trailer *trailer;
307 + const struct firmware *fw;
308 + const char *fw_name;
312 + /* load firmware region metadata */
313 + for (i = 0; i < ARRAY_SIZE(mem_region); i++) {
314 + ret = mtk_wed_get_memory_region(wo, &mem_region[i]);
319 + wo->boot.name = "wo-boot";
320 + ret = mtk_wed_get_memory_region(wo, &wo->boot);
325 + wed_w32(wo->hw->wed_dev, MTK_WED_SCR0 + 4 * MTK_WED_DUMMY_CR_FWDL,
326 + wo->hw->index + 1);
328 + /* load firmware */
329 + fw_name = wo->hw->index ? MT7986_FIRMWARE_WO1 : MT7986_FIRMWARE_WO0;
330 + ret = request_firmware(&fw, fw_name, wo->hw->dev);
334 + trailer = (void *)(fw->data + fw->size -
335 + sizeof(struct mtk_wed_fw_trailer));
336 + dev_info(wo->hw->dev,
337 + "MTK WED WO Firmware Version: %.10s, Build Time: %.15s\n",
338 + trailer->fw_ver, trailer->build_date);
339 + dev_info(wo->hw->dev, "MTK WED WO Chip ID %02x Region %d\n",
340 + trailer->chip_id, trailer->num_region);
342 + for (i = 0; i < ARRAY_SIZE(mem_region); i++) {
343 + ret = mtk_wed_mcu_run_firmware(wo, fw, &mem_region[i]);
348 + /* set the start address */
349 + boot_cr = wo->hw->index ? MTK_WO_MCU_CFG_LS_WA_BOOT_ADDR_ADDR
350 + : MTK_WO_MCU_CFG_LS_WM_BOOT_ADDR_ADDR;
351 + wo_w32(wo, boot_cr, mem_region[MTK_WED_WO_REGION_EMI].phy_addr >> 16);
352 + /* wo firmware reset */
353 + wo_w32(wo, MTK_WO_MCU_CFG_LS_WF_MCCR_CLR_ADDR, 0xc00);
355 + val = wo_r32(wo, MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR);
356 + val |= wo->hw->index ? MTK_WO_MCU_CFG_LS_WF_WM_WA_WA_CPU_RSTB_MASK
357 + : MTK_WO_MCU_CFG_LS_WF_WM_WA_WM_CPU_RSTB_MASK;
358 + wo_w32(wo, MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR, val);
360 + release_firmware(fw);
366 +mtk_wed_mcu_read_fw_dl(struct mtk_wed_wo *wo)
368 + return wed_r32(wo->hw->wed_dev,
369 + MTK_WED_SCR0 + 4 * MTK_WED_DUMMY_CR_FWDL);
372 +int mtk_wed_mcu_init(struct mtk_wed_wo *wo)
377 + skb_queue_head_init(&wo->mcu.res_q);
378 + init_waitqueue_head(&wo->mcu.wait);
379 + mutex_init(&wo->mcu.mutex);
381 + ret = mtk_wed_mcu_load_firmware(wo);
385 + return readx_poll_timeout(mtk_wed_mcu_read_fw_dl, wo, val, !val,
386 + 100, MTK_FW_DL_TIMEOUT);
389 +MODULE_FIRMWARE(MT7986_FIRMWARE_WO0);
390 +MODULE_FIRMWARE(MT7986_FIRMWARE_WO1);
391 --- a/drivers/net/ethernet/mediatek/mtk_wed_regs.h
392 +++ b/drivers/net/ethernet/mediatek/mtk_wed_regs.h
393 @@ -152,6 +152,7 @@ struct mtk_wdma_desc {
395 #define MTK_WED_RING_RX(_n) (0x400 + (_n) * 0x10)
397 +#define MTK_WED_SCR0 0x3c0
398 #define MTK_WED_WPDMA_INT_TRIGGER 0x504
399 #define MTK_WED_WPDMA_INT_TRIGGER_RX_DONE BIT(1)
400 #define MTK_WED_WPDMA_INT_TRIGGER_TX_DONE GENMASK(5, 4)
402 +++ b/drivers/net/ethernet/mediatek/mtk_wed_wo.h
404 +/* SPDX-License-Identifier: GPL-2.0-only */
405 +/* Copyright (C) 2022 Lorenzo Bianconi <lorenzo@kernel.org> */
407 +#ifndef __MTK_WED_WO_H
408 +#define __MTK_WED_WO_H
410 +#include <linux/skbuff.h>
411 +#include <linux/netdevice.h>
415 +struct mtk_wed_mcu_hdr {
432 +struct mtk_wed_wo_log_info {
439 +enum mtk_wed_wo_event {
440 + MTK_WED_WO_EVT_LOG_DUMP = 0x1,
441 + MTK_WED_WO_EVT_PROFILING = 0x2,
442 + MTK_WED_WO_EVT_RXCNT_INFO = 0x3,
445 +#define MTK_WED_MODULE_ID_WO 1
446 +#define MTK_FW_DL_TIMEOUT 4000000 /* us */
447 +#define MTK_WOCPU_TIMEOUT 2000000 /* us */
450 + MTK_WED_WARP_CMD_FLAG_RSP = BIT(0),
451 + MTK_WED_WARP_CMD_FLAG_NEED_RSP = BIT(1),
452 + MTK_WED_WARP_CMD_FLAG_FROM_TO_WO = BIT(2),
456 + MTK_WED_WO_REGION_EMI,
457 + MTK_WED_WO_REGION_ILM,
458 + MTK_WED_WO_REGION_DATA,
459 + MTK_WED_WO_REGION_BOOT,
460 + __MTK_WED_WO_REGION_MAX,
463 +enum mtk_wed_dummy_cr_idx {
464 + MTK_WED_DUMMY_CR_FWDL,
465 + MTK_WED_DUMMY_CR_WO_STATUS,
468 +#define MT7986_FIRMWARE_WO0 "mediatek/mt7986_wo_0.bin"
469 +#define MT7986_FIRMWARE_WO1 "mediatek/mt7986_wo_1.bin"
471 +#define MTK_WO_MCU_CFG_LS_BASE 0
472 +#define MTK_WO_MCU_CFG_LS_HW_VER_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x000)
473 +#define MTK_WO_MCU_CFG_LS_FW_VER_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x004)
474 +#define MTK_WO_MCU_CFG_LS_CFG_DBG1_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x00c)
475 +#define MTK_WO_MCU_CFG_LS_CFG_DBG2_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x010)
476 +#define MTK_WO_MCU_CFG_LS_WF_MCCR_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x014)
477 +#define MTK_WO_MCU_CFG_LS_WF_MCCR_SET_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x018)
478 +#define MTK_WO_MCU_CFG_LS_WF_MCCR_CLR_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x01c)
479 +#define MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x050)
480 +#define MTK_WO_MCU_CFG_LS_WM_BOOT_ADDR_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x060)
481 +#define MTK_WO_MCU_CFG_LS_WA_BOOT_ADDR_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x064)
483 +#define MTK_WO_MCU_CFG_LS_WF_WM_WA_WM_CPU_RSTB_MASK BIT(5)
484 +#define MTK_WO_MCU_CFG_LS_WF_WM_WA_WA_CPU_RSTB_MASK BIT(0)
486 +struct mtk_wed_wo_memory_region {
488 + void __iomem *addr;
489 + phys_addr_t phy_addr;
495 +struct mtk_wed_fw_region {
498 + __le32 decomp_blk_sz;
506 +struct mtk_wed_fw_trailer {
514 + char build_date[15];
519 + struct mtk_wed_hw *hw;
520 + struct mtk_wed_wo_memory_region boot;
523 + struct mutex mutex;
527 + struct sk_buff_head res_q;
528 + wait_queue_head_t wait;
533 +mtk_wed_mcu_check_msg(struct mtk_wed_wo *wo, struct sk_buff *skb)
535 + struct mtk_wed_mcu_hdr *hdr = (struct mtk_wed_mcu_hdr *)skb->data;
540 + if (skb->len < sizeof(*hdr) || skb->len != le16_to_cpu(hdr->length))
546 +void mtk_wed_mcu_rx_event(struct mtk_wed_wo *wo, struct sk_buff *skb);
547 +void mtk_wed_mcu_rx_unsolicited_event(struct mtk_wed_wo *wo,
548 + struct sk_buff *skb);
549 +int mtk_wed_mcu_send_msg(struct mtk_wed_wo *wo, int id, int cmd,
550 + const void *data, int len, bool wait_resp);
551 +int mtk_wed_mcu_init(struct mtk_wed_wo *wo);
553 +#endif /* __MTK_WED_WO_H */
554 --- a/include/linux/soc/mediatek/mtk_wed.h
555 +++ b/include/linux/soc/mediatek/mtk_wed.h
558 struct mtk_wdma_desc;
560 +enum mtk_wed_wo_cmd {
561 + MTK_WED_WO_CMD_WED_CFG,
562 + MTK_WED_WO_CMD_WED_RX_STAT,
563 + MTK_WED_WO_CMD_RRO_SER,
564 + MTK_WED_WO_CMD_DBG_INFO,
565 + MTK_WED_WO_CMD_DEV_INFO,
566 + MTK_WED_WO_CMD_BSS_INFO,
567 + MTK_WED_WO_CMD_STA_REC,
568 + MTK_WED_WO_CMD_DEV_INFO_DUMP,
569 + MTK_WED_WO_CMD_BSS_INFO_DUMP,
570 + MTK_WED_WO_CMD_STA_REC_DUMP,
571 + MTK_WED_WO_CMD_BA_INFO_DUMP,
572 + MTK_WED_WO_CMD_FBCMD_Q_DUMP,
573 + MTK_WED_WO_CMD_FW_LOG_CTRL,
574 + MTK_WED_WO_CMD_LOG_FLUSH,
575 + MTK_WED_WO_CMD_CHANGE_STATE,
576 + MTK_WED_WO_CMD_CPU_STATS_ENABLE,
577 + MTK_WED_WO_CMD_CPU_STATS_DUMP,
578 + MTK_WED_WO_CMD_EXCEPTION_INIT,
579 + MTK_WED_WO_CMD_PROF_CTRL,
580 + MTK_WED_WO_CMD_STA_BA_DUMP,
581 + MTK_WED_WO_CMD_BA_CTRL_DUMP,
582 + MTK_WED_WO_CMD_RXCNT_CTRL,
583 + MTK_WED_WO_CMD_RXCNT_INFO,
584 + MTK_WED_WO_CMD_SET_CAP,
585 + MTK_WED_WO_CMD_CCIF_RING_DUMP,
586 + MTK_WED_WO_CMD_WED_END
589 enum mtk_wed_bus_tye {