target/linux/generic/pending-5.15/737-05-net-ethernet-mtk_eth_soc-convert-caps-in-mtk_soc_dat.patch

   1 From 45b575fd9e6a455090820248bf1b98b1f2c7b6c8 Mon Sep 17 00:00:00 2001
   2 From: Lorenzo Bianconi <lorenzo@kernel.org>
   3 Date: Tue, 7 Mar 2023 15:56:00 +0000
   4 Subject: [PATCH 5/7] net: ethernet: mtk_eth_soc: convert caps in mtk_soc_data
   5  struct to u64
   6
   7 This is a preliminary patch to introduce support for MT7988 SoC.
   8
   9 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  10 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  11 ---
  12  drivers/net/ethernet/mediatek/mtk_eth_path.c | 22 +++----
  13  drivers/net/ethernet/mediatek/mtk_eth_soc.h  | 62 ++++++++++----------
  14  2 files changed, 42 insertions(+), 42 deletions(-)
  15
  16 --- a/drivers/net/ethernet/mediatek/mtk_eth_path.c
  17 +++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c
  18 @@ -15,10 +15,10 @@
  19  struct mtk_eth_muxc {
  20         const char      *name;
  21         int             cap_bit;
  22 -       int             (*set_path)(struct mtk_eth *eth, int path);
  23 +       int             (*set_path)(struct mtk_eth *eth, u64 path);
  24  };
  25
  26 -static const char *mtk_eth_path_name(int path)
  27 +static const char *mtk_eth_path_name(u64 path)
  28  {
  29         switch (path) {
  30         case MTK_ETH_PATH_GMAC1_RGMII:
  31 @@ -40,7 +40,7 @@ static const char *mtk_eth_path_name(int
  32         }
  33  }
  34
  35 -static int set_mux_gdm1_to_gmac1_esw(struct mtk_eth *eth, int path)
  36 +static int set_mux_gdm1_to_gmac1_esw(struct mtk_eth *eth, u64 path)
  37  {
  38         bool updated = true;
  39         u32 val, mask, set;
  40 @@ -71,7 +71,7 @@ static int set_mux_gdm1_to_gmac1_esw(str
  41         return 0;
  42  }
  43
  44 -static int set_mux_gmac2_gmac0_to_gephy(struct mtk_eth *eth, int path)
  45 +static int set_mux_gmac2_gmac0_to_gephy(struct mtk_eth *eth, u64 path)
  46  {
  47         unsigned int val = 0;
  48         bool updated = true;
  49 @@ -94,7 +94,7 @@ static int set_mux_gmac2_gmac0_to_gephy(
  50         return 0;
  51  }
  52
  53 -static int set_mux_u3_gmac2_to_qphy(struct mtk_eth *eth, int path)
  54 +static int set_mux_u3_gmac2_to_qphy(struct mtk_eth *eth, u64 path)
  55  {
  56         unsigned int val = 0, mask = 0, reg = 0;
  57         bool updated = true;
  58 @@ -125,7 +125,7 @@ static int set_mux_u3_gmac2_to_qphy(stru
  59         return 0;
  60  }
  61
  62 -static int set_mux_gmac1_gmac2_to_sgmii_rgmii(struct mtk_eth *eth, int path)
  63 +static int set_mux_gmac1_gmac2_to_sgmii_rgmii(struct mtk_eth *eth, u64 path)
  64  {
  65         unsigned int val = 0;
  66         bool updated = true;
  67 @@ -163,7 +163,7 @@ static int set_mux_gmac1_gmac2_to_sgmii_
  68         return 0;
  69  }
  70
  71 -static int set_mux_gmac12_to_gephy_sgmii(struct mtk_eth *eth, int path)
  72 +static int set_mux_gmac12_to_gephy_sgmii(struct mtk_eth *eth, u64 path)
  73  {
  74         unsigned int val = 0;
  75         bool updated = true;
  76 @@ -218,7 +218,7 @@ static const struct mtk_eth_muxc mtk_eth
  77         },
  78  };
  79
  80 -static int mtk_eth_mux_setup(struct mtk_eth *eth, int path)
  81 +static int mtk_eth_mux_setup(struct mtk_eth *eth, u64 path)
  82  {
  83         int i, err = 0;
  84
  85 @@ -249,7 +249,7 @@ out:
  86
  87  int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id)
  88  {
  89 -       int path;
  90 +       u64 path;
  91
  92         path = (mac_id == 0) ?  MTK_ETH_PATH_GMAC1_SGMII :
  93                                 MTK_ETH_PATH_GMAC2_SGMII;
  94 @@ -260,7 +260,7 @@ int mtk_gmac_sgmii_path_setup(struct mtk
  95
  96  int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id)
  97  {
  98 -       int path = 0;
  99 +       u64 path = 0;
 100
 101         if (mac_id == 1)
 102                 path = MTK_ETH_PATH_GMAC2_GEPHY;
 103 @@ -274,7 +274,7 @@ int mtk_gmac_gephy_path_setup(struct mtk
 104
 105  int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id)
 106  {
 107 -       int path;
 108 +       u64 path;
 109
 110         path = (mac_id == 0) ?  MTK_ETH_PATH_GMAC1_RGMII :
 111                                 MTK_ETH_PATH_GMAC2_RGMII;
 112 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 113 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 114 @@ -878,44 +878,44 @@ enum mkt_eth_capabilities {
 115  };
 116
 117  /* Supported hardware group on SoCs */
 118 -#define MTK_RGMII              BIT(MTK_RGMII_BIT)
 119 -#define MTK_TRGMII             BIT(MTK_TRGMII_BIT)
 120 -#define MTK_SGMII              BIT(MTK_SGMII_BIT)
 121 -#define MTK_ESW                        BIT(MTK_ESW_BIT)
 122 -#define MTK_GEPHY              BIT(MTK_GEPHY_BIT)
 123 -#define MTK_MUX                        BIT(MTK_MUX_BIT)
 124 -#define MTK_INFRA              BIT(MTK_INFRA_BIT)
 125 -#define MTK_SHARED_SGMII       BIT(MTK_SHARED_SGMII_BIT)
 126 -#define MTK_HWLRO              BIT(MTK_HWLRO_BIT)
 127 -#define MTK_SHARED_INT         BIT(MTK_SHARED_INT_BIT)
 128 -#define MTK_TRGMII_MT7621_CLK  BIT(MTK_TRGMII_MT7621_CLK_BIT)
 129 -#define MTK_QDMA               BIT(MTK_QDMA_BIT)
 130 -#define MTK_NETSYS_V1          BIT(MTK_NETSYS_V1_BIT)
 131 -#define MTK_NETSYS_V2          BIT(MTK_NETSYS_V2_BIT)
 132 -#define MTK_NETSYS_V3          BIT(MTK_NETSYS_V3_BIT)
 133 -#define MTK_SOC_MT7628         BIT(MTK_SOC_MT7628_BIT)
 134 -#define MTK_RSTCTRL_PPE1       BIT(MTK_RSTCTRL_PPE1_BIT)
 135 -#define MTK_U3_COPHY_V2                BIT(MTK_U3_COPHY_V2_BIT)
 136 +#define MTK_RGMII              BIT_ULL(MTK_RGMII_BIT)
 137 +#define MTK_TRGMII             BIT_ULL(MTK_TRGMII_BIT)
 138 +#define MTK_SGMII              BIT_ULL(MTK_SGMII_BIT)
 139 +#define MTK_ESW                        BIT_ULL(MTK_ESW_BIT)
 140 +#define MTK_GEPHY              BIT_ULL(MTK_GEPHY_BIT)
 141 +#define MTK_MUX                        BIT_ULL(MTK_MUX_BIT)
 142 +#define MTK_INFRA              BIT_ULL(MTK_INFRA_BIT)
 143 +#define MTK_SHARED_SGMII       BIT_ULL(MTK_SHARED_SGMII_BIT)
 144 +#define MTK_HWLRO              BIT_ULL(MTK_HWLRO_BIT)
 145 +#define MTK_SHARED_INT         BIT_ULL(MTK_SHARED_INT_BIT)
 146 +#define MTK_TRGMII_MT7621_CLK  BIT_ULL(MTK_TRGMII_MT7621_CLK_BIT)
 147 +#define MTK_QDMA               BIT_ULL(MTK_QDMA_BIT)
 148 +#define MTK_NETSYS_V1          BIT_ULL(MTK_NETSYS_V1_BIT)
 149 +#define MTK_NETSYS_V2          BIT_ULL(MTK_NETSYS_V2_BIT)
 150 +#define MTK_NETSYS_V3          BIT_ULL(MTK_NETSYS_V3_BIT)
 151 +#define MTK_SOC_MT7628         BIT_ULL(MTK_SOC_MT7628_BIT)
 152 +#define MTK_RSTCTRL_PPE1       BIT_ULL(MTK_RSTCTRL_PPE1_BIT)
 153 +#define MTK_U3_COPHY_V2                BIT_ULL(MTK_U3_COPHY_V2_BIT)
 154
 155  #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW          \
 156 -       BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT)
 157 +       BIT_ULL(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT)
 158  #define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY       \
 159 -       BIT(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT)
 160 +       BIT_ULL(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT)
 161  #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY           \
 162 -       BIT(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT)
 163 +       BIT_ULL(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT)
 164  #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \
 165 -       BIT(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT)
 166 +       BIT_ULL(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT)
 167  #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII      \
 168 -       BIT(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT)
 169 +       BIT_ULL(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT)
 170
 171  /* Supported path present on SoCs */
 172 -#define MTK_ETH_PATH_GMAC1_RGMII       BIT(MTK_ETH_PATH_GMAC1_RGMII_BIT)
 173 -#define MTK_ETH_PATH_GMAC1_TRGMII      BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT)
 174 -#define MTK_ETH_PATH_GMAC1_SGMII       BIT(MTK_ETH_PATH_GMAC1_SGMII_BIT)
 175 -#define MTK_ETH_PATH_GMAC2_RGMII       BIT(MTK_ETH_PATH_GMAC2_RGMII_BIT)
 176 -#define MTK_ETH_PATH_GMAC2_SGMII       BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT)
 177 -#define MTK_ETH_PATH_GMAC2_GEPHY       BIT(MTK_ETH_PATH_GMAC2_GEPHY_BIT)
 178 -#define MTK_ETH_PATH_GDM1_ESW          BIT(MTK_ETH_PATH_GDM1_ESW_BIT)
 179 +#define MTK_ETH_PATH_GMAC1_RGMII       BIT_ULL(MTK_ETH_PATH_GMAC1_RGMII_BIT)
 180 +#define MTK_ETH_PATH_GMAC1_TRGMII      BIT_ULL(MTK_ETH_PATH_GMAC1_TRGMII_BIT)
 181 +#define MTK_ETH_PATH_GMAC1_SGMII       BIT_ULL(MTK_ETH_PATH_GMAC1_SGMII_BIT)
 182 +#define MTK_ETH_PATH_GMAC2_RGMII       BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT)
 183 +#define MTK_ETH_PATH_GMAC2_SGMII       BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT)
 184 +#define MTK_ETH_PATH_GMAC2_GEPHY       BIT_ULL(MTK_ETH_PATH_GMAC2_GEPHY_BIT)
 185 +#define MTK_ETH_PATH_GDM1_ESW          BIT_ULL(MTK_ETH_PATH_GDM1_ESW_BIT)
 186
 187  #define MTK_GMAC1_RGMII                (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII)
 188  #define MTK_GMAC1_TRGMII       (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
 189 @@ -1071,7 +1071,7 @@ struct mtk_reg_map {
 190  struct mtk_soc_data {
 191         const struct mtk_reg_map *reg_map;
 192         u32             ana_rgc3;
 193 -       u32             caps;
 194 +       u64             caps;
 195         u32             required_clks;
 196         bool            required_pctl;
 197         u8              offload_version;