1 From ab817f559d505329d8a413c7d29250f6d87d77a0 Mon Sep 17 00:00:00 2001
2 From: Lorenzo Bianconi <lorenzo@kernel.org>
3 Date: Tue, 7 Mar 2023 15:55:47 +0000
4 Subject: [PATCH 4/7] net: ethernet: mtk_eth_soc: add MTK_NETSYS_V3 capability
7 Introduce MTK_NETSYS_V3 bit in the device capabilities.
8 This is a preliminary patch to introduce support for MT7988 SoC.
10 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
11 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
13 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 115 ++++++++++++++++----
14 drivers/net/ethernet/mediatek/mtk_eth_soc.h | 44 +++++++-
15 2 files changed, 134 insertions(+), 25 deletions(-)
17 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
18 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
19 @@ -924,17 +924,32 @@ void mtk_stats_update_mac(struct mtk_mac
20 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x20 + offs);
21 hw_stats->rx_flow_control_packets +=
22 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x24 + offs);
23 - hw_stats->tx_skip +=
24 - mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x28 + offs);
25 - hw_stats->tx_collisions +=
26 - mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x2c + offs);
27 - hw_stats->tx_bytes +=
28 - mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x30 + offs);
29 - stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x34 + offs);
31 - hw_stats->tx_bytes += (stats << 32);
32 - hw_stats->tx_packets +=
33 - mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x38 + offs);
35 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) {
36 + hw_stats->tx_skip +=
37 + mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x50 + offs);
38 + hw_stats->tx_collisions +=
39 + mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x54 + offs);
40 + hw_stats->tx_bytes +=
41 + mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x40 + offs);
42 + stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x44 + offs);
44 + hw_stats->tx_bytes += (stats << 32);
45 + hw_stats->tx_packets +=
46 + mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x48 + offs);
48 + hw_stats->tx_skip +=
49 + mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x28 + offs);
50 + hw_stats->tx_collisions +=
51 + mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x2c + offs);
52 + hw_stats->tx_bytes +=
53 + mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x30 + offs);
54 + stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x34 + offs);
56 + hw_stats->tx_bytes += (stats << 32);
57 + hw_stats->tx_packets +=
58 + mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x38 + offs);
62 u64_stats_update_end(&hw_stats->syncp);
63 @@ -1238,7 +1253,10 @@ static void mtk_tx_set_dma_desc_v2(struc
65 WRITE_ONCE(desc->txd3, data);
67 - data = (mac->id + 1) << TX_DMA_FPORT_SHIFT_V2; /* forward port */
68 + if (mac->id == MTK_GMAC3_ID)
69 + data = PSE_GDM3_PORT;
71 + data = (mac->id + 1) << TX_DMA_FPORT_SHIFT_V2; /* forward port */
72 data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid);
73 WRITE_ONCE(desc->txd4, data);
75 @@ -1249,6 +1267,9 @@ static void mtk_tx_set_dma_desc_v2(struc
76 /* tx checksum offload */
78 data |= TX_DMA_CHKSUM_V2;
79 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3) &&
80 + netdev_uses_dsa(dev))
81 + data |= TX_DMA_SPTAG_V3;
83 WRITE_ONCE(desc->txd5, data);
85 @@ -1314,8 +1335,13 @@ static int mtk_tx_map(struct sk_buff *sk
86 mtk_tx_set_dma_desc(dev, itxd, &txd_info);
88 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
89 - itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 :
90 - MTK_TX_FLAGS_FPORT1;
91 + if (mac->id == MTK_GMAC1_ID)
92 + itx_buf->flags |= MTK_TX_FLAGS_FPORT0;
93 + else if (mac->id == MTK_GMAC2_ID)
94 + itx_buf->flags |= MTK_TX_FLAGS_FPORT1;
96 + itx_buf->flags |= MTK_TX_FLAGS_FPORT2;
98 setup_tx_buf(eth, itx_buf, itxd_pdma, txd_info.addr, txd_info.size,
101 @@ -1363,8 +1389,13 @@ static int mtk_tx_map(struct sk_buff *sk
102 memset(tx_buf, 0, sizeof(*tx_buf));
103 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
104 tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
105 - tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 :
106 - MTK_TX_FLAGS_FPORT1;
108 + if (mac->id == MTK_GMAC1_ID)
109 + tx_buf->flags |= MTK_TX_FLAGS_FPORT0;
110 + else if (mac->id == MTK_GMAC2_ID)
111 + tx_buf->flags |= MTK_TX_FLAGS_FPORT1;
113 + tx_buf->flags |= MTK_TX_FLAGS_FPORT2;
115 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info.addr,
117 @@ -1950,11 +1981,24 @@ static int mtk_poll_rx(struct napi_struc
120 /* find out which mac the packet come from. values start at 1 */
121 - if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1))
122 - mac = RX_DMA_GET_SPORT_V2(trxd.rxd5) - 1;
123 - else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) &&
124 - !(trxd.rxd4 & RX_DMA_SPECIAL_TAG))
125 + if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) {
126 + u32 val = RX_DMA_GET_SPORT_V2(trxd.rxd5);
129 + case PSE_GDM1_PORT:
130 + case PSE_GDM2_PORT:
133 + case PSE_GDM3_PORT:
134 + mac = MTK_GMAC3_ID;
139 + } else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) &&
140 + !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) {
141 mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1;
144 if (unlikely(mac < 0 || mac >= eth->soc->num_devs ||
146 @@ -2185,7 +2229,9 @@ static int mtk_poll_tx_qdma(struct mtk_e
147 tx_buf = mtk_desc_to_tx_buf(ring, desc,
148 eth->soc->txrx.txd_size);
149 if (tx_buf->flags & MTK_TX_FLAGS_FPORT1)
151 + mac = MTK_GMAC2_ID;
152 + else if (tx_buf->flags & MTK_TX_FLAGS_FPORT2)
153 + mac = MTK_GMAC3_ID;
157 @@ -3796,7 +3842,26 @@ static int mtk_hw_init(struct mtk_eth *e
158 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4);
159 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
161 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
162 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) {
163 + /* PSE should not drop port1, port8 and port9 packets */
164 + mtk_w32(eth, 0x00000302, PSE_DROP_CFG);
166 + /* GDM and CDM Threshold */
167 + mtk_w32(eth, 0x00000707, MTK_CDMW0_THRES);
168 + mtk_w32(eth, 0x00000077, MTK_CDMW1_THRES);
170 + /* Disable GDM1 RX CRC stripping */
171 + val = mtk_r32(eth, MTK_GDMA_FWD_CFG(0));
172 + val &= ~MTK_GDMA_STRP_CRC;
173 + mtk_w32(eth, val, MTK_GDMA_FWD_CFG(0));
175 + /* PSE GDM3 MIB counter has incorrect hw default values,
176 + * so the driver ought to read clear the values beforehand
177 + * in case ethtool retrieve wrong mib values.
179 + for (i = 0; i < 0x80; i += 0x4)
180 + mtk_r32(eth, reg_map->gdm1_cnt + 0x100 + i);
181 + } else if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
182 /* PSE should not drop port8 and port9 packets from WDMA Tx */
183 mtk_w32(eth, 0x00000300, PSE_DROP_CFG);
185 @@ -4361,7 +4426,11 @@ static int mtk_add_mac(struct mtk_eth *e
187 spin_lock_init(&mac->hw_stats->stats_lock);
188 u64_stats_init(&mac->hw_stats->syncp);
189 - mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
191 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3))
192 + mac->hw_stats->reg_offset = id * 0x80;
194 + mac->hw_stats->reg_offset = id * 0x40;
197 err = of_get_phy_mode(np, &phy_mode);
198 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
199 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
201 #define MTK_GDMA_ICS_EN BIT(22)
202 #define MTK_GDMA_TCS_EN BIT(21)
203 #define MTK_GDMA_UCS_EN BIT(20)
204 +#define MTK_GDMA_STRP_CRC BIT(16)
205 #define MTK_GDMA_TO_PDMA 0x0
206 #define MTK_GDMA_DROP_ALL 0x7777
209 /* QDMA Interrupt grouping registers */
210 #define MTK_RLS_DONE_INT BIT(0)
212 -#define MTK_STAT_OFFSET 0x40
215 #define QID_BITS_V2(x) (((x) & 0x3f) << 16)
216 #define MTK_QDMA_GMAC2_QID 8
218 #define TX_DMA_CHKSUM_V2 (0x7 << 28)
219 #define TX_DMA_TSO_V2 BIT(31)
221 +#define TX_DMA_SPTAG_V3 BIT(27)
223 /* QDMA V2 descriptor txd4 */
224 #define TX_DMA_FPORT_SHIFT_V2 8
225 #define TX_DMA_FPORT_MASK_V2 0xf
226 @@ -639,6 +640,7 @@ enum mtk_tx_flags {
228 MTK_TX_FLAGS_FPORT0 = 0x04,
229 MTK_TX_FLAGS_FPORT1 = 0x08,
230 + MTK_TX_FLAGS_FPORT2 = 0x10,
233 /* This enum allows us to identify how the clock is defined on the array of the
234 @@ -724,6 +726,42 @@ enum mtk_dev_state {
238 +/* PSE Port Definition */
259 +/* GMAC Identifier */
274 enum mtk_tx_buf_type {
277 @@ -820,6 +858,7 @@ enum mkt_eth_capabilities {
283 MTK_RSTCTRL_PPE1_BIT,
285 @@ -856,6 +895,7 @@ enum mkt_eth_capabilities {
286 #define MTK_QDMA BIT(MTK_QDMA_BIT)
287 #define MTK_NETSYS_V1 BIT(MTK_NETSYS_V1_BIT)
288 #define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT)
289 +#define MTK_NETSYS_V3 BIT(MTK_NETSYS_V3_BIT)
290 #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT)
291 #define MTK_RSTCTRL_PPE1 BIT(MTK_RSTCTRL_PPE1_BIT)
292 #define MTK_U3_COPHY_V2 BIT(MTK_U3_COPHY_V2_BIT)