1 From 91bda2f441f9e37273922028ffc48ce8e91bf5bd Mon Sep 17 00:00:00 2001
2 From: Daniel Golle <daniel@makrotopia.org>
3 Date: Tue, 12 Dec 2023 03:51:14 +0000
4 Subject: [PATCH] net: ethernet: mtk_eth_soc: add paths and SerDes modes for
7 MT7988 comes with a built-in 2.5G PHY as well as SerDes lanes to
8 connect external PHYs or transceivers in USXGMII, 10GBase-R, 5GBase-R,
9 2500Base-X, 1000Base-X and Cisco SGMII interface modes.
11 Implement support for configuring for the new paths to SerDes interfaces
12 and the internal 2.5G PHY.
14 Add USXGMII PCS driver for 10GBase-R, 5GBase-R and USXGMII mode, and
15 setup the new PHYA on MT7988 to access the also still existing old
16 LynxI PCS for 1000Base-X, 2500Base-X and Cisco SGMII PCS interface
19 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
21 drivers/net/ethernet/mediatek/mtk_eth_path.c | 122 +++++++-
22 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 291 +++++++++++++++++--
23 drivers/net/ethernet/mediatek/mtk_eth_soc.h | 107 ++++++-
24 3 files changed, 469 insertions(+), 51 deletions(-)
26 --- a/drivers/net/ethernet/mediatek/mtk_eth_path.c
27 +++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c
28 @@ -31,10 +31,20 @@ static const char *mtk_eth_path_name(u64
30 case MTK_ETH_PATH_GMAC2_SGMII:
32 + case MTK_ETH_PATH_GMAC2_2P5GPHY:
33 + return "gmac2_2p5gphy";
34 case MTK_ETH_PATH_GMAC2_GEPHY:
36 + case MTK_ETH_PATH_GMAC3_SGMII:
37 + return "gmac3_sgmii";
38 case MTK_ETH_PATH_GDM1_ESW:
40 + case MTK_ETH_PATH_GMAC1_USXGMII:
41 + return "gmac1_usxgmii";
42 + case MTK_ETH_PATH_GMAC2_USXGMII:
43 + return "gmac2_usxgmii";
44 + case MTK_ETH_PATH_GMAC3_USXGMII:
45 + return "gmac3_usxgmii";
47 return "unknown path";
49 @@ -127,6 +137,27 @@ static int set_mux_u3_gmac2_to_qphy(stru
53 +static int set_mux_gmac2_to_2p5gphy(struct mtk_eth *eth, u64 path)
57 + if (path == MTK_ETH_PATH_GMAC2_2P5GPHY) {
58 + ret = regmap_clear_bits(eth->ethsys, ETHSYS_SYSCFG0, SYSCFG0_SGMII_GMAC2_V2);
62 + /* Setup mux to 2p5g PHY */
63 + ret = regmap_clear_bits(eth->infra, TOP_MISC_NETSYS_PCS_MUX, MUX_G2_USXGMII_SEL);
67 + dev_dbg(eth->dev, "path %s in %s updated\n",
68 + mtk_eth_path_name(path), __func__);
74 static int set_mux_gmac1_gmac2_to_sgmii_rgmii(struct mtk_eth *eth, u64 path)
77 @@ -165,7 +196,48 @@ static int set_mux_gmac1_gmac2_to_sgmii_
81 -static int set_mux_gmac12_to_gephy_sgmii(struct mtk_eth *eth, u64 path)
82 +static int set_mux_gmac123_to_usxgmii(struct mtk_eth *eth, u64 path)
84 + unsigned int val = 0;
85 + bool updated = true;
88 + /* Disable SYSCFG1 SGMII */
89 + regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
92 + case MTK_ETH_PATH_GMAC1_USXGMII:
93 + val &= ~(u32)SYSCFG0_SGMII_GMAC1_V2;
94 + mac_id = MTK_GMAC1_ID;
96 + case MTK_ETH_PATH_GMAC2_USXGMII:
97 + val &= ~(u32)SYSCFG0_SGMII_GMAC2_V2;
98 + mac_id = MTK_GMAC2_ID;
100 + case MTK_ETH_PATH_GMAC3_USXGMII:
101 + val &= ~(u32)SYSCFG0_SGMII_GMAC3_V2;
102 + mac_id = MTK_GMAC3_ID;
109 + regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
110 + SYSCFG0_SGMII_MASK, val);
112 + if (mac_id == MTK_GMAC2_ID)
113 + regmap_set_bits(eth->infra, TOP_MISC_NETSYS_PCS_MUX,
114 + MUX_G2_USXGMII_SEL);
117 + dev_dbg(eth->dev, "path %s in %s updated = %d\n",
118 + mtk_eth_path_name(path), __func__, updated);
123 +static int set_mux_gmac123_to_gephy_sgmii(struct mtk_eth *eth, u64 path)
125 unsigned int val = 0;
127 @@ -182,6 +254,9 @@ static int set_mux_gmac12_to_gephy_sgmii
128 case MTK_ETH_PATH_GMAC2_SGMII:
129 val |= SYSCFG0_SGMII_GMAC2_V2;
131 + case MTK_ETH_PATH_GMAC3_SGMII:
132 + val |= SYSCFG0_SGMII_GMAC3_V2;
137 @@ -210,13 +285,25 @@ static const struct mtk_eth_muxc mtk_eth
138 .cap_bit = MTK_ETH_MUX_U3_GMAC2_TO_QPHY,
139 .set_path = set_mux_u3_gmac2_to_qphy,
141 + .name = "mux_gmac2_to_2p5gphy",
142 + .cap_bit = MTK_ETH_MUX_GMAC2_TO_2P5GPHY,
143 + .set_path = set_mux_gmac2_to_2p5gphy,
145 .name = "mux_gmac1_gmac2_to_sgmii_rgmii",
146 .cap_bit = MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII,
147 .set_path = set_mux_gmac1_gmac2_to_sgmii_rgmii,
149 .name = "mux_gmac12_to_gephy_sgmii",
150 .cap_bit = MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII,
151 - .set_path = set_mux_gmac12_to_gephy_sgmii,
152 + .set_path = set_mux_gmac123_to_gephy_sgmii,
154 + .name = "mux_gmac123_to_gephy_sgmii",
155 + .cap_bit = MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII,
156 + .set_path = set_mux_gmac123_to_gephy_sgmii,
158 + .name = "mux_gmac123_to_usxgmii",
159 + .cap_bit = MTK_ETH_MUX_GMAC123_TO_USXGMII,
160 + .set_path = set_mux_gmac123_to_usxgmii,
164 @@ -249,12 +336,39 @@ out:
168 +int mtk_gmac_usxgmii_path_setup(struct mtk_eth *eth, int mac_id)
172 + path = (mac_id == MTK_GMAC1_ID) ? MTK_ETH_PATH_GMAC1_USXGMII :
173 + (mac_id == MTK_GMAC2_ID) ? MTK_ETH_PATH_GMAC2_USXGMII :
174 + MTK_ETH_PATH_GMAC3_USXGMII;
176 + /* Setup proper MUXes along the path */
177 + return mtk_eth_mux_setup(eth, path);
180 int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id)
184 - path = (mac_id == 0) ? MTK_ETH_PATH_GMAC1_SGMII :
185 - MTK_ETH_PATH_GMAC2_SGMII;
186 + path = (mac_id == MTK_GMAC1_ID) ? MTK_ETH_PATH_GMAC1_SGMII :
187 + (mac_id == MTK_GMAC2_ID) ? MTK_ETH_PATH_GMAC2_SGMII :
188 + MTK_ETH_PATH_GMAC3_SGMII;
190 + /* Setup proper MUXes along the path */
191 + return mtk_eth_mux_setup(eth, path);
194 +int mtk_gmac_2p5gphy_path_setup(struct mtk_eth *eth, int mac_id)
198 + if (mac_id == MTK_GMAC2_ID)
199 + path = MTK_ETH_PATH_GMAC2_2P5GPHY;
204 /* Setup proper MUXes along the path */
205 return mtk_eth_mux_setup(eth, path);
206 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
207 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
209 #include <linux/pinctrl/devinfo.h>
210 #include <linux/phylink.h>
211 #include <linux/pcs/pcs-mtk-lynxi.h>
212 +#include <linux/pcs/pcs-mtk-usxgmii.h>
213 +#include <linux/phy/phy.h>
214 #include <linux/jhash.h>
215 #include <linux/bitfield.h>
217 @@ -258,12 +260,8 @@ static const char * const mtk_clks_sourc
221 - "top_usxgmii0_sel",
222 - "top_usxgmii1_sel",
225 - "top_xfi_phy0_xtal_sel",
226 - "top_xfi_phy1_xtal_sel",
228 "top_eth_refck_50m_sel",
229 "top_eth_sys_200m_sel",
230 @@ -475,6 +473,30 @@ static void mtk_setup_bridge_switch(stru
234 +static bool mtk_check_gmac23_idle(struct mtk_mac *mac)
236 + u32 mac_fsm, gdm_fsm;
238 + mac_fsm = mtk_r32(mac->hw, MTK_MAC_FSM(mac->id));
242 + gdm_fsm = mtk_r32(mac->hw, MTK_FE_GDM2_FSM);
245 + gdm_fsm = mtk_r32(mac->hw, MTK_FE_GDM3_FSM);
251 + if ((mac_fsm & 0xFFFF0000) == 0x01010000 &&
252 + (gdm_fsm & 0xFFFF0000) == 0x00000000)
258 static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config,
259 phy_interface_t interface)
261 @@ -483,6 +505,21 @@ static struct phylink_pcs *mtk_mac_selec
262 struct mtk_eth *eth = mac->hw;
265 + if (mtk_is_netsys_v3_or_greater(eth)) {
266 + switch (interface) {
267 + case PHY_INTERFACE_MODE_1000BASEX:
268 + case PHY_INTERFACE_MODE_2500BASEX:
269 + case PHY_INTERFACE_MODE_SGMII:
270 + return mac->sgmii_pcs;
271 + case PHY_INTERFACE_MODE_5GBASER:
272 + case PHY_INTERFACE_MODE_10GBASER:
273 + case PHY_INTERFACE_MODE_USXGMII:
274 + return mac->usxgmii_pcs;
280 if (interface == PHY_INTERFACE_MODE_SGMII ||
281 phy_interface_mode_is_8023z(interface)) {
282 sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
283 @@ -544,7 +581,22 @@ static void mtk_mac_config(struct phylin
287 + case PHY_INTERFACE_MODE_USXGMII:
288 + case PHY_INTERFACE_MODE_10GBASER:
289 + case PHY_INTERFACE_MODE_5GBASER:
290 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII)) {
291 + err = mtk_gmac_usxgmii_path_setup(eth, mac->id);
296 case PHY_INTERFACE_MODE_INTERNAL:
297 + if (mac->id == MTK_GMAC2_ID &&
298 + MTK_HAS_CAPS(eth->soc->caps, MTK_2P5GPHY)) {
299 + err = mtk_gmac_2p5gphy_path_setup(eth, mac->id);
306 @@ -599,8 +651,6 @@ static void mtk_mac_config(struct phylin
307 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
308 val |= SYSCFG0_GE_MODE(ge_mode, mac->id);
309 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
311 - mac->interface = state->interface;
315 @@ -617,21 +667,40 @@ static void mtk_mac_config(struct phylin
317 /* Save the syscfg0 value for mac_finish */
319 - } else if (phylink_autoneg_inband(mode)) {
320 + } else if (state->interface != PHY_INTERFACE_MODE_USXGMII &&
321 + state->interface != PHY_INTERFACE_MODE_10GBASER &&
322 + state->interface != PHY_INTERFACE_MODE_5GBASER &&
323 + phylink_autoneg_inband(mode)) {
325 - "In-band mode not supported in non SGMII mode!\n");
326 + "In-band mode not supported in non-SerDes modes!\n");
331 - if (mtk_is_netsys_v3_or_greater(eth) &&
332 - mac->interface == PHY_INTERFACE_MODE_INTERNAL) {
333 - mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id));
334 - mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id));
335 + if (mtk_is_netsys_v3_or_greater(eth)) {
336 + if (mtk_interface_mode_is_xgmii(state->interface)) {
337 + mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id));
338 + mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id));
340 + if (mac->id == MTK_GMAC1_ID)
341 + mtk_setup_bridge_switch(eth);
343 + mtk_w32(eth, 0, MTK_GDMA_EG_CTRL(mac->id));
345 - mtk_setup_bridge_switch(eth);
346 + /* FIXME: In current hardware design, we have to reset FE
347 + * when swtiching XGDM to GDM. Therefore, here trigger an SER
348 + * to let GDM go back to the initial state.
350 + if ((mtk_interface_mode_is_xgmii(mac->interface) ||
351 + mac->interface == PHY_INTERFACE_MODE_NA) &&
352 + !mtk_check_gmac23_idle(mac) &&
353 + !test_bit(MTK_RESETTING, ð->state))
354 + schedule_work(ð->pending_work);
358 + mac->interface = state->interface;
363 @@ -644,6 +713,18 @@ init_err:
364 mac->id, phy_modes(state->interface), err);
367 +static int mtk_mac_prepare(struct phylink_config *config, unsigned int mode,
368 + phy_interface_t interface)
370 + struct mtk_mac *mac = container_of(config, struct mtk_mac,
373 + if (mac->pextp && mac->interface != interface)
374 + phy_reset(mac->pextp);
379 static int mtk_mac_finish(struct phylink_config *config, unsigned int mode,
380 phy_interface_t interface)
382 @@ -652,6 +733,10 @@ static int mtk_mac_finish(struct phylink
383 struct mtk_eth *eth = mac->hw;
384 u32 mcr_cur, mcr_new;
386 + /* Setup PMA/PMD */
388 + phy_set_mode_ext(mac->pextp, PHY_MODE_ETHERNET, interface);
391 if (interface == PHY_INTERFACE_MODE_SGMII ||
392 phy_interface_mode_is_8023z(interface))
393 @@ -677,10 +762,13 @@ static void mtk_mac_link_down(struct phy
395 struct mtk_mac *mac = container_of(config, struct mtk_mac,
397 - u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
399 - mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN);
400 - mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
401 + if (!mtk_interface_mode_is_xgmii(interface)) {
402 + mtk_m32(mac->hw, MAC_MCR_TX_EN | MAC_MCR_RX_EN, 0, MTK_MAC_MCR(mac->id));
403 + mtk_m32(mac->hw, MTK_XGMAC_FORCE_LINK(mac->id), 0, MTK_XGMAC_STS(mac->id));
404 + } else if (mac->id != MTK_GMAC1_ID) {
405 + mtk_m32(mac->hw, XMAC_MCR_TRX_DISABLE, XMAC_MCR_TRX_DISABLE, MTK_XMAC_MCR(mac->id));
409 static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx,
410 @@ -752,13 +840,11 @@ static void mtk_set_queue_speed(struct m
411 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs);
414 -static void mtk_mac_link_up(struct phylink_config *config,
415 - struct phy_device *phy,
416 - unsigned int mode, phy_interface_t interface,
417 - int speed, int duplex, bool tx_pause, bool rx_pause)
418 +static void mtk_gdm_mac_link_up(struct mtk_mac *mac,
419 + struct phy_device *phy,
420 + unsigned int mode, phy_interface_t interface,
421 + int speed, int duplex, bool tx_pause, bool rx_pause)
423 - struct mtk_mac *mac = container_of(config, struct mtk_mac,
427 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
428 @@ -792,9 +878,63 @@ static void mtk_mac_link_up(struct phyli
429 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
432 +static void mtk_xgdm_mac_link_up(struct mtk_mac *mac,
433 + struct phy_device *phy,
434 + unsigned int mode, phy_interface_t interface,
435 + int speed, int duplex, bool tx_pause, bool rx_pause)
437 + u32 mcr, force_link = 0;
439 + if (mac->id == MTK_GMAC1_ID)
442 + /* Eliminate the interference(before link-up) caused by PHY noise */
443 + mtk_m32(mac->hw, XMAC_LOGIC_RST, 0, MTK_XMAC_LOGIC_RST(mac->id));
445 + mtk_m32(mac->hw, XMAC_GLB_CNTCLR, XMAC_GLB_CNTCLR, MTK_XMAC_CNT_CTRL(mac->id));
447 + if (mac->interface == PHY_INTERFACE_MODE_INTERNAL || mac->id == MTK_GMAC3_ID)
448 + force_link = MTK_XGMAC_FORCE_LINK(mac->id);
450 + mtk_m32(mac->hw, MTK_XGMAC_FORCE_LINK(mac->id), force_link, MTK_XGMAC_STS(mac->id));
452 + mcr = mtk_r32(mac->hw, MTK_XMAC_MCR(mac->id));
453 + mcr &= ~(XMAC_MCR_FORCE_TX_FC | XMAC_MCR_FORCE_RX_FC | XMAC_MCR_TRX_DISABLE);
454 + /* Configure pause modes -
455 + * phylink will avoid these for half duplex
458 + mcr |= XMAC_MCR_FORCE_TX_FC;
460 + mcr |= XMAC_MCR_FORCE_RX_FC;
462 + mtk_w32(mac->hw, mcr, MTK_XMAC_MCR(mac->id));
465 +static void mtk_mac_link_up(struct phylink_config *config,
466 + struct phy_device *phy,
467 + unsigned int mode, phy_interface_t interface,
468 + int speed, int duplex, bool tx_pause, bool rx_pause)
470 + struct mtk_mac *mac = container_of(config, struct mtk_mac,
473 + if (mtk_interface_mode_is_xgmii(interface))
474 + mtk_xgdm_mac_link_up(mac, phy, mode, interface, speed, duplex,
475 + tx_pause, rx_pause);
477 + mtk_gdm_mac_link_up(mac, phy, mode, interface, speed, duplex,
478 + tx_pause, rx_pause);
480 + /* Repeat pextp setup to tune link */
482 + phy_set_mode_ext(mac->pextp, PHY_MODE_ETHERNET, interface);
485 static const struct phylink_mac_ops mtk_phylink_ops = {
486 .mac_select_pcs = mtk_mac_select_pcs,
487 .mac_config = mtk_mac_config,
488 + .mac_prepare = mtk_mac_prepare,
489 .mac_finish = mtk_mac_finish,
490 .mac_link_down = mtk_mac_link_down,
491 .mac_link_up = mtk_mac_link_up,
492 @@ -3373,6 +3513,9 @@ static int mtk_open(struct net_device *d
493 struct mtk_eth *eth = mac->hw;
497 + phy_power_on(mac->pextp);
499 err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0);
501 netdev_err(dev, "%s: could not attach PHY: %d\n", __func__,
502 @@ -3501,6 +3644,9 @@ static int mtk_stop(struct net_device *d
503 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++)
504 mtk_ppe_stop(eth->ppe[i]);
507 + phy_power_off(mac->pextp);
512 @@ -4498,6 +4644,7 @@ static const struct net_device_ops mtk_n
513 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
515 const __be32 *_id = of_get_property(np, "reg", NULL);
516 + struct device_node *pcs_np;
517 phy_interface_t phy_mode;
518 struct phylink *phylink;
520 @@ -4533,16 +4680,41 @@ static int mtk_add_mac(struct mtk_eth *e
524 + pcs_np = of_parse_phandle(mac->of_node, "pcs-handle", 0);
526 + mac->sgmii_pcs = mtk_pcs_lynxi_get(eth->dev, pcs_np);
527 + if (IS_ERR(mac->sgmii_pcs)) {
528 + if (PTR_ERR(mac->sgmii_pcs) == -EPROBE_DEFER)
529 + return -EPROBE_DEFER;
531 - err = of_get_ethdev_address(mac->of_node, eth->netdev[id]);
532 - if (err == -EPROBE_DEFER)
534 + dev_err(eth->dev, "cannot select SGMII PCS, error %ld\n",
535 + PTR_ERR(mac->sgmii_pcs));
536 + return PTR_ERR(mac->sgmii_pcs);
541 - /* If the mac address is invalid, use random mac address */
542 - eth_hw_addr_random(eth->netdev[id]);
543 - dev_err(eth->dev, "generated random MAC address %pM\n",
544 - eth->netdev[id]->dev_addr);
545 + pcs_np = of_parse_phandle(mac->of_node, "pcs-handle", 1);
547 + mac->usxgmii_pcs = mtk_usxgmii_pcs_get(eth->dev, pcs_np);
548 + if (IS_ERR(mac->usxgmii_pcs)) {
549 + if (PTR_ERR(mac->usxgmii_pcs) == -EPROBE_DEFER)
550 + return -EPROBE_DEFER;
552 + dev_err(eth->dev, "cannot select USXGMII PCS, error %ld\n",
553 + PTR_ERR(mac->usxgmii_pcs));
554 + return PTR_ERR(mac->usxgmii_pcs);
558 + if (mtk_is_netsys_v3_or_greater(eth) && (mac->sgmii_pcs || mac->usxgmii_pcs)) {
559 + mac->pextp = devm_of_phy_get(eth->dev, mac->of_node, NULL);
560 + if (IS_ERR(mac->pextp)) {
561 + if (PTR_ERR(mac->pextp) != -EPROBE_DEFER)
562 + dev_err(eth->dev, "cannot get PHY, error %ld\n",
563 + PTR_ERR(mac->pextp));
565 + return PTR_ERR(mac->pextp);
569 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip));
570 @@ -4616,8 +4788,21 @@ static int mtk_add_mac(struct mtk_eth *e
571 phy_interface_zero(mac->phylink_config.supported_interfaces);
572 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
573 mac->phylink_config.supported_interfaces);
574 + } else if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_USXGMII)) {
575 + mac->phylink_config.mac_capabilities |= MAC_5000FD | MAC_10000FD;
576 + __set_bit(PHY_INTERFACE_MODE_5GBASER,
577 + mac->phylink_config.supported_interfaces);
578 + __set_bit(PHY_INTERFACE_MODE_10GBASER,
579 + mac->phylink_config.supported_interfaces);
580 + __set_bit(PHY_INTERFACE_MODE_USXGMII,
581 + mac->phylink_config.supported_interfaces);
584 + if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_2P5GPHY) &&
585 + id == MTK_GMAC2_ID)
586 + __set_bit(PHY_INTERFACE_MODE_INTERNAL,
587 + mac->phylink_config.supported_interfaces);
589 phylink = phylink_create(&mac->phylink_config,
590 of_fwnode_handle(mac->of_node),
591 phy_mode, &mtk_phylink_ops);
592 @@ -4662,6 +4847,26 @@ free_netdev:
596 +static int mtk_mac_assign_address(struct mtk_eth *eth, int i, bool test_defer_only)
598 + int err = of_get_ethdev_address(eth->mac[i]->of_node, eth->netdev[i]);
600 + if (err == -EPROBE_DEFER)
603 + if (test_defer_only)
607 + /* If the mac address is invalid, use random mac address */
608 + eth_hw_addr_random(eth->netdev[i]);
609 + dev_err(eth->dev, "generated random MAC address %pM\n",
616 void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev)
618 struct net_device *dev, *tmp;
619 @@ -4805,7 +5010,8 @@ static int mtk_probe(struct platform_dev
620 regmap_write(cci, 0, 3);
623 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
624 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII) &&
625 + !mtk_is_netsys_v3_or_greater(eth)) {
626 err = mtk_sgmii_init(eth);
629 @@ -4916,6 +5122,24 @@ static int mtk_probe(struct platform_dev
633 + for (i = 0; i < MTK_MAX_DEVS; i++) {
634 + if (!eth->netdev[i])
637 + err = mtk_mac_assign_address(eth, i, true);
639 + goto err_deinit_hw;
642 + for (i = 0; i < MTK_MAX_DEVS; i++) {
643 + if (!eth->netdev[i])
646 + err = mtk_mac_assign_address(eth, i, false);
648 + goto err_deinit_hw;
651 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) {
652 err = devm_request_irq(eth->dev, eth->irq[0],
654 @@ -5018,6 +5242,11 @@ static int mtk_remove(struct platform_de
655 mtk_stop(eth->netdev[i]);
656 mac = netdev_priv(eth->netdev[i]);
657 phylink_disconnect_phy(mac->phylink);
658 + if (mac->sgmii_pcs)
659 + mtk_pcs_lynxi_put(mac->sgmii_pcs);
661 + if (mac->usxgmii_pcs)
662 + mtk_usxgmii_pcs_put(mac->usxgmii_pcs);
666 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
667 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
669 #include <linux/u64_stats_sync.h>
670 #include <linux/refcount.h>
671 #include <linux/phylink.h>
672 +#include <linux/reset.h>
673 #include <linux/rhashtable.h>
674 #include <linux/dim.h>
675 #include <linux/bitfield.h>
677 #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED)
678 #define INTF_MODE_RGMII_10_100 0
680 +/* XFI Mac control registers */
681 +#define MTK_XMAC_BASE(x) (0x12000 + (((x) - 1) * 0x1000))
682 +#define MTK_XMAC_MCR(x) (MTK_XMAC_BASE(x))
683 +#define XMAC_MCR_TRX_DISABLE 0xf
684 +#define XMAC_MCR_FORCE_TX_FC BIT(5)
685 +#define XMAC_MCR_FORCE_RX_FC BIT(4)
687 +/* XFI Mac logic reset registers */
688 +#define MTK_XMAC_LOGIC_RST(x) (MTK_XMAC_BASE(x) + 0x10)
689 +#define XMAC_LOGIC_RST BIT(0)
691 +/* XFI Mac count global control */
692 +#define MTK_XMAC_CNT_CTRL(x) (MTK_XMAC_BASE(x) + 0x100)
693 +#define XMAC_GLB_CNTCLR BIT(0)
695 /* GPIO port control registers for GMAC 2*/
696 #define GPIO_OD33_CTRL8 0x4c0
697 #define GPIO_BIAS_CTRL 0xed0
699 #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK)
700 #define SYSCFG0_SGMII_GMAC1_V2 BIT(9)
701 #define SYSCFG0_SGMII_GMAC2_V2 BIT(8)
702 +#define SYSCFG0_SGMII_GMAC3_V2 BIT(7)
705 /* ethernet subsystem clock register */
707 #define GEPHY_MAC_SEL BIT(1)
709 /* Top misc registers */
710 +#define TOP_MISC_NETSYS_PCS_MUX 0x84
711 +#define NETSYS_PCS_MUX_MASK GENMASK(1, 0)
712 +#define MUX_G2_USXGMII_SEL BIT(1)
713 +#define MUX_HSGMII1_G1_SEL BIT(0)
715 #define USB_PHY_SWITCH_REG 0x218
716 #define QPHY_SEL_MASK GENMASK(1, 0)
717 #define SGMII_QPHY_SEL 0x2
719 #define MT7628_SDM_RBCNT (MT7628_SDM_OFFSET + 0x10c)
720 #define MT7628_SDM_CS_ERR (MT7628_SDM_OFFSET + 0x110)
722 +/* Debug Purpose Register */
723 +#define MTK_PSE_FQFC_CFG 0x100
724 #define MTK_FE_CDM1_FSM 0x220
725 #define MTK_FE_CDM2_FSM 0x224
726 #define MTK_FE_CDM3_FSM 0x238
728 #define MTK_FE_CDM6_FSM 0x328
729 #define MTK_FE_GDM1_FSM 0x228
730 #define MTK_FE_GDM2_FSM 0x22C
731 +#define MTK_FE_GDM3_FSM 0x23C
732 +#define MTK_FE_PSE_FREE 0x240
733 +#define MTK_FE_DROP_FQ 0x244
734 +#define MTK_FE_DROP_FC 0x248
735 +#define MTK_FE_DROP_PPE 0x24C
737 #define MTK_MAC_FSM(x) (0x1010C + ((x) * 0x100))
739 @@ -721,12 +750,8 @@ enum mtk_clks_map {
740 MTK_CLK_ETHWARP_WOCPU2,
741 MTK_CLK_ETHWARP_WOCPU1,
742 MTK_CLK_ETHWARP_WOCPU0,
743 - MTK_CLK_TOP_USXGMII_SBUS_0_SEL,
744 - MTK_CLK_TOP_USXGMII_SBUS_1_SEL,
745 MTK_CLK_TOP_SGM_0_SEL,
746 MTK_CLK_TOP_SGM_1_SEL,
747 - MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL,
748 - MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL,
749 MTK_CLK_TOP_ETH_GMII_SEL,
750 MTK_CLK_TOP_ETH_REFCK_50M_SEL,
751 MTK_CLK_TOP_ETH_SYS_200M_SEL,
752 @@ -797,19 +822,9 @@ enum mtk_clks_map {
753 BIT_ULL(MTK_CLK_GP3) | BIT_ULL(MTK_CLK_XGP1) | \
754 BIT_ULL(MTK_CLK_XGP2) | BIT_ULL(MTK_CLK_XGP3) | \
755 BIT_ULL(MTK_CLK_CRYPTO) | \
756 - BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
757 - BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
758 - BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
759 - BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
760 BIT_ULL(MTK_CLK_ETHWARP_WOCPU2) | \
761 BIT_ULL(MTK_CLK_ETHWARP_WOCPU1) | \
762 BIT_ULL(MTK_CLK_ETHWARP_WOCPU0) | \
763 - BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_0_SEL) | \
764 - BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_1_SEL) | \
765 - BIT_ULL(MTK_CLK_TOP_SGM_0_SEL) | \
766 - BIT_ULL(MTK_CLK_TOP_SGM_1_SEL) | \
767 - BIT_ULL(MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL) | \
768 - BIT_ULL(MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL) | \
769 BIT_ULL(MTK_CLK_TOP_ETH_GMII_SEL) | \
770 BIT_ULL(MTK_CLK_TOP_ETH_REFCK_50M_SEL) | \
771 BIT_ULL(MTK_CLK_TOP_ETH_SYS_200M_SEL) | \
772 @@ -943,6 +958,8 @@ enum mkt_eth_capabilities {
781 @@ -963,8 +980,11 @@ enum mkt_eth_capabilities {
782 MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
783 MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT,
784 MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT,
785 + MTK_ETH_MUX_GMAC2_TO_2P5GPHY_BIT,
786 MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT,
787 MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT,
788 + MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII_BIT,
789 + MTK_ETH_MUX_GMAC123_TO_USXGMII_BIT,
792 MTK_ETH_PATH_GMAC1_RGMII_BIT,
793 @@ -972,14 +992,21 @@ enum mkt_eth_capabilities {
794 MTK_ETH_PATH_GMAC1_SGMII_BIT,
795 MTK_ETH_PATH_GMAC2_RGMII_BIT,
796 MTK_ETH_PATH_GMAC2_SGMII_BIT,
797 + MTK_ETH_PATH_GMAC2_2P5GPHY_BIT,
798 MTK_ETH_PATH_GMAC2_GEPHY_BIT,
799 + MTK_ETH_PATH_GMAC3_SGMII_BIT,
800 MTK_ETH_PATH_GDM1_ESW_BIT,
801 + MTK_ETH_PATH_GMAC1_USXGMII_BIT,
802 + MTK_ETH_PATH_GMAC2_USXGMII_BIT,
803 + MTK_ETH_PATH_GMAC3_USXGMII_BIT,
806 /* Supported hardware group on SoCs */
807 #define MTK_RGMII BIT_ULL(MTK_RGMII_BIT)
808 #define MTK_TRGMII BIT_ULL(MTK_TRGMII_BIT)
809 #define MTK_SGMII BIT_ULL(MTK_SGMII_BIT)
810 +#define MTK_USXGMII BIT_ULL(MTK_USXGMII_BIT)
811 +#define MTK_2P5GPHY BIT_ULL(MTK_2P5GPHY_BIT)
812 #define MTK_ESW BIT_ULL(MTK_ESW_BIT)
813 #define MTK_GEPHY BIT_ULL(MTK_GEPHY_BIT)
814 #define MTK_MUX BIT_ULL(MTK_MUX_BIT)
815 @@ -1002,10 +1029,16 @@ enum mkt_eth_capabilities {
816 BIT_ULL(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT)
817 #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \
818 BIT_ULL(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT)
819 +#define MTK_ETH_MUX_GMAC2_TO_2P5GPHY \
820 + BIT_ULL(MTK_ETH_MUX_GMAC2_TO_2P5GPHY_BIT)
821 #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \
822 BIT_ULL(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT)
823 #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \
824 BIT_ULL(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT)
825 +#define MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII \
826 + BIT_ULL(MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII_BIT)
827 +#define MTK_ETH_MUX_GMAC123_TO_USXGMII \
828 + BIT_ULL(MTK_ETH_MUX_GMAC123_TO_USXGMII_BIT)
830 /* Supported path present on SoCs */
831 #define MTK_ETH_PATH_GMAC1_RGMII BIT_ULL(MTK_ETH_PATH_GMAC1_RGMII_BIT)
832 @@ -1013,8 +1046,13 @@ enum mkt_eth_capabilities {
833 #define MTK_ETH_PATH_GMAC1_SGMII BIT_ULL(MTK_ETH_PATH_GMAC1_SGMII_BIT)
834 #define MTK_ETH_PATH_GMAC2_RGMII BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT)
835 #define MTK_ETH_PATH_GMAC2_SGMII BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT)
836 +#define MTK_ETH_PATH_GMAC2_2P5GPHY BIT_ULL(MTK_ETH_PATH_GMAC2_2P5GPHY_BIT)
837 #define MTK_ETH_PATH_GMAC2_GEPHY BIT_ULL(MTK_ETH_PATH_GMAC2_GEPHY_BIT)
838 +#define MTK_ETH_PATH_GMAC3_SGMII BIT_ULL(MTK_ETH_PATH_GMAC3_SGMII_BIT)
839 #define MTK_ETH_PATH_GDM1_ESW BIT_ULL(MTK_ETH_PATH_GDM1_ESW_BIT)
840 +#define MTK_ETH_PATH_GMAC1_USXGMII BIT_ULL(MTK_ETH_PATH_GMAC1_USXGMII_BIT)
841 +#define MTK_ETH_PATH_GMAC2_USXGMII BIT_ULL(MTK_ETH_PATH_GMAC2_USXGMII_BIT)
842 +#define MTK_ETH_PATH_GMAC3_USXGMII BIT_ULL(MTK_ETH_PATH_GMAC3_USXGMII_BIT)
844 #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII)
845 #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
846 @@ -1022,7 +1060,12 @@ enum mkt_eth_capabilities {
847 #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII)
848 #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII)
849 #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY)
850 +#define MTK_GMAC2_2P5GPHY (MTK_ETH_PATH_GMAC2_2P5GPHY | MTK_2P5GPHY)
851 +#define MTK_GMAC3_SGMII (MTK_ETH_PATH_GMAC3_SGMII | MTK_SGMII)
852 #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW)
853 +#define MTK_GMAC1_USXGMII (MTK_ETH_PATH_GMAC1_USXGMII | MTK_USXGMII)
854 +#define MTK_GMAC2_USXGMII (MTK_ETH_PATH_GMAC2_USXGMII | MTK_USXGMII)
855 +#define MTK_GMAC3_USXGMII (MTK_ETH_PATH_GMAC3_USXGMII | MTK_USXGMII)
857 /* MUXes present on SoCs */
858 /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */
859 @@ -1041,10 +1084,20 @@ enum mkt_eth_capabilities {
860 (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \
863 +/* 2: GMAC2 -> XGMII */
864 +#define MTK_MUX_GMAC2_TO_2P5GPHY \
865 + (MTK_ETH_MUX_GMAC2_TO_2P5GPHY | MTK_MUX | MTK_INFRA)
867 /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */
868 #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \
869 (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX)
871 +#define MTK_MUX_GMAC123_TO_GEPHY_SGMII \
872 + (MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII | MTK_MUX)
874 +#define MTK_MUX_GMAC123_TO_USXGMII \
875 + (MTK_ETH_MUX_GMAC123_TO_USXGMII | MTK_MUX | MTK_INFRA)
877 #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x))
879 #define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \
880 @@ -1076,8 +1129,12 @@ enum mkt_eth_capabilities {
881 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
882 MTK_RSTCTRL_PPE1 | MTK_SRAM)
884 -#define MT7988_CAPS (MTK_36BIT_DMA | MTK_GDM1_ESW | MTK_QDMA | \
885 - MTK_RSTCTRL_PPE1 | MTK_RSTCTRL_PPE2 | MTK_SRAM)
886 +#define MT7988_CAPS (MTK_36BIT_DMA | MTK_GDM1_ESW | MTK_GMAC1_SGMII | \
887 + MTK_GMAC2_2P5GPHY | MTK_GMAC2_SGMII | MTK_GMAC2_USXGMII | \
888 + MTK_GMAC3_SGMII | MTK_GMAC3_USXGMII | \
889 + MTK_MUX_GMAC123_TO_GEPHY_SGMII | \
890 + MTK_MUX_GMAC123_TO_USXGMII | MTK_MUX_GMAC2_TO_2P5GPHY | \
891 + MTK_QDMA | MTK_RSTCTRL_PPE1 | MTK_RSTCTRL_PPE2 | MTK_SRAM)
893 struct mtk_tx_dma_desc_info {
895 @@ -1314,6 +1371,9 @@ struct mtk_mac {
896 struct device_node *of_node;
897 struct phylink *phylink;
898 struct phylink_config phylink_config;
899 + struct phylink_pcs *sgmii_pcs;
900 + struct phylink_pcs *usxgmii_pcs;
903 struct mtk_hw_stats *hw_stats;
904 __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT];
905 @@ -1437,6 +1497,19 @@ static inline u32 mtk_get_ib2_multicast_
906 return MTK_FOE_IB2_MULTICAST;
909 +static inline bool mtk_interface_mode_is_xgmii(phy_interface_t interface)
911 + switch (interface) {
912 + case PHY_INTERFACE_MODE_INTERNAL:
913 + case PHY_INTERFACE_MODE_USXGMII:
914 + case PHY_INTERFACE_MODE_10GBASER:
915 + case PHY_INTERFACE_MODE_5GBASER:
922 /* read the hardware status register */
923 void mtk_stats_update_mac(struct mtk_mac *mac);
925 @@ -1445,8 +1518,10 @@ u32 mtk_r32(struct mtk_eth *eth, unsigne
926 u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg);
928 int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id);
929 +int mtk_gmac_2p5gphy_path_setup(struct mtk_eth *eth, int mac_id);
930 int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);
931 int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id);
932 +int mtk_gmac_usxgmii_path_setup(struct mtk_eth *eth, int mac_id);
934 int mtk_eth_offload_init(struct mtk_eth *eth);
935 int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type,