1 From 1e25ca1147579bda8b941be1b9851f5911d44eb0 Mon Sep 17 00:00:00 2001
2 From: Daniel Golle <daniel@makrotopia.org>
3 Date: Tue, 22 Aug 2023 19:04:42 +0100
4 Subject: [PATCH 098/125] net: ethernet: mtk_eth_soc: add paths and SerDes
7 MT7988 comes with a built-in 2.5G PHY as well as SerDes lanes to
8 connect external PHYs or transceivers in USXGMII, 10GBase-R, 5GBase-R,
9 2500Base-X, 1000Base-X and Cisco SGMII interface modes.
11 Implement support for configuring for the new paths to SerDes interfaces
12 and the internal 2.5G PHY.
14 Add USXGMII PCS driver for 10GBase-R, 5GBase-R and USXGMII mode, and
15 setup the new PHYA on MT7988 to access the also still existing old
16 LynxI PCS for 1000Base-X, 2500Base-X and Cisco SGMII PCS interface
19 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
21 drivers/net/ethernet/mediatek/Kconfig | 16 +
22 drivers/net/ethernet/mediatek/Makefile | 1 +
23 drivers/net/ethernet/mediatek/mtk_eth_path.c | 123 +++-
24 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 182 ++++-
25 drivers/net/ethernet/mediatek/mtk_eth_soc.h | 232 ++++++-
26 drivers/net/ethernet/mediatek/mtk_usxgmii.c | 692 +++++++++++++++++++
27 6 files changed, 1215 insertions(+), 31 deletions(-)
28 create mode 100644 drivers/net/ethernet/mediatek/mtk_usxgmii.c
30 --- a/drivers/net/ethernet/mediatek/Kconfig
31 +++ b/drivers/net/ethernet/mediatek/Kconfig
32 @@ -25,6 +25,22 @@ config NET_MEDIATEK_SOC
33 This driver supports the gigabit ethernet MACs in the
36 +config NET_MEDIATEK_SOC_USXGMII
37 + bool "Support USXGMII SerDes on MT7988"
38 + depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
39 + def_bool NET_MEDIATEK_SOC != n
41 + Include support for 10GE SerDes which can be found on MT7988.
42 + If this kernel should run on SoCs with 10 GBit/s Ethernet you
43 + will need to select this option to use GMAC2 and GMAC3 with
44 + external PHYs, SFP(+) cages in 10GBase-R, 5GBase-R or USXGMII
47 + Note that as the 2500Base-X/1000Base-X/Cisco SGMII SerDes PCS
48 + unit (MediaTek LynxI) in MT7988 is connected via the new 10GE
49 + SerDes, you will also need to select this option in case you
50 + want to use any of those SerDes modes.
52 config NET_MEDIATEK_STAR_EMAC
53 tristate "MediaTek STAR Ethernet MAC support"
55 --- a/drivers/net/ethernet/mediatek/Makefile
56 +++ b/drivers/net/ethernet/mediatek/Makefile
59 obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o
60 mtk_eth-y := mtk_eth_soc.o mtk_eth_path.o mtk_ppe.o mtk_ppe_debugfs.o mtk_ppe_offload.o
61 +mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_USXGMII) += mtk_usxgmii.o
62 mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed.o mtk_wed_mcu.o mtk_wed_wo.o
64 mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed_debugfs.o
65 --- a/drivers/net/ethernet/mediatek/mtk_eth_path.c
66 +++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c
67 @@ -31,10 +31,20 @@ static const char *mtk_eth_path_name(u64
69 case MTK_ETH_PATH_GMAC2_SGMII:
71 + case MTK_ETH_PATH_GMAC2_2P5GPHY:
72 + return "gmac2_2p5gphy";
73 case MTK_ETH_PATH_GMAC2_GEPHY:
75 + case MTK_ETH_PATH_GMAC3_SGMII:
76 + return "gmac3_sgmii";
77 case MTK_ETH_PATH_GDM1_ESW:
79 + case MTK_ETH_PATH_GMAC1_USXGMII:
80 + return "gmac1_usxgmii";
81 + case MTK_ETH_PATH_GMAC2_USXGMII:
82 + return "gmac2_usxgmii";
83 + case MTK_ETH_PATH_GMAC3_USXGMII:
84 + return "gmac3_usxgmii";
86 return "unknown path";
88 @@ -127,6 +137,27 @@ static int set_mux_u3_gmac2_to_qphy(stru
92 +static int set_mux_gmac2_to_2p5gphy(struct mtk_eth *eth, u64 path)
96 + if (path == MTK_ETH_PATH_GMAC2_2P5GPHY) {
97 + ret = regmap_clear_bits(eth->ethsys, ETHSYS_SYSCFG0, SYSCFG0_SGMII_GMAC2_V2);
101 + /* Setup mux to 2p5g PHY */
102 + ret = regmap_clear_bits(eth->infra, TOP_MISC_NETSYS_PCS_MUX, MUX_G2_USXGMII_SEL);
106 + dev_dbg(eth->dev, "path %s in %s updated\n",
107 + mtk_eth_path_name(path), __func__);
113 static int set_mux_gmac1_gmac2_to_sgmii_rgmii(struct mtk_eth *eth, u64 path)
115 unsigned int val = 0;
116 @@ -165,7 +196,48 @@ static int set_mux_gmac1_gmac2_to_sgmii_
120 -static int set_mux_gmac12_to_gephy_sgmii(struct mtk_eth *eth, u64 path)
121 +static int set_mux_gmac123_to_usxgmii(struct mtk_eth *eth, u64 path)
123 + unsigned int val = 0;
124 + bool updated = true;
127 + /* Disable SYSCFG1 SGMII */
128 + regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
131 + case MTK_ETH_PATH_GMAC1_USXGMII:
132 + val &= ~(u32)SYSCFG0_SGMII_GMAC1_V2;
133 + mac_id = MTK_GMAC1_ID;
135 + case MTK_ETH_PATH_GMAC2_USXGMII:
136 + val &= ~(u32)SYSCFG0_SGMII_GMAC2_V2;
137 + mac_id = MTK_GMAC2_ID;
139 + case MTK_ETH_PATH_GMAC3_USXGMII:
140 + val &= ~(u32)SYSCFG0_SGMII_GMAC3_V2;
141 + mac_id = MTK_GMAC3_ID;
148 + regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
149 + SYSCFG0_SGMII_MASK, val);
151 + if (mac_id == MTK_GMAC2_ID)
152 + regmap_set_bits(eth->infra, TOP_MISC_NETSYS_PCS_MUX,
153 + MUX_G2_USXGMII_SEL);
156 + dev_dbg(eth->dev, "path %s in %s updated = %d\n",
157 + mtk_eth_path_name(path), __func__, updated);
162 +static int set_mux_gmac123_to_gephy_sgmii(struct mtk_eth *eth, u64 path)
164 unsigned int val = 0;
166 @@ -182,6 +254,9 @@ static int set_mux_gmac12_to_gephy_sgmii
167 case MTK_ETH_PATH_GMAC2_SGMII:
168 val |= SYSCFG0_SGMII_GMAC2_V2;
170 + case MTK_ETH_PATH_GMAC3_SGMII:
171 + val |= SYSCFG0_SGMII_GMAC3_V2;
176 @@ -210,13 +285,25 @@ static const struct mtk_eth_muxc mtk_eth
177 .cap_bit = MTK_ETH_MUX_U3_GMAC2_TO_QPHY,
178 .set_path = set_mux_u3_gmac2_to_qphy,
180 + .name = "mux_gmac2_to_2p5gphy",
181 + .cap_bit = MTK_ETH_MUX_GMAC2_TO_2P5GPHY,
182 + .set_path = set_mux_gmac2_to_2p5gphy,
184 .name = "mux_gmac1_gmac2_to_sgmii_rgmii",
185 .cap_bit = MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII,
186 .set_path = set_mux_gmac1_gmac2_to_sgmii_rgmii,
188 .name = "mux_gmac12_to_gephy_sgmii",
189 .cap_bit = MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII,
190 - .set_path = set_mux_gmac12_to_gephy_sgmii,
191 + .set_path = set_mux_gmac123_to_gephy_sgmii,
193 + .name = "mux_gmac123_to_gephy_sgmii",
194 + .cap_bit = MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII,
195 + .set_path = set_mux_gmac123_to_gephy_sgmii,
197 + .name = "mux_gmac123_to_usxgmii",
198 + .cap_bit = MTK_ETH_MUX_GMAC123_TO_USXGMII,
199 + .set_path = set_mux_gmac123_to_usxgmii,
203 @@ -249,12 +336,39 @@ out:
207 +int mtk_gmac_usxgmii_path_setup(struct mtk_eth *eth, int mac_id)
211 + path = (mac_id == MTK_GMAC1_ID) ? MTK_ETH_PATH_GMAC1_USXGMII :
212 + (mac_id == MTK_GMAC2_ID) ? MTK_ETH_PATH_GMAC2_USXGMII :
213 + MTK_ETH_PATH_GMAC3_USXGMII;
215 + /* Setup proper MUXes along the path */
216 + return mtk_eth_mux_setup(eth, path);
219 int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id)
223 - path = (mac_id == 0) ? MTK_ETH_PATH_GMAC1_SGMII :
224 - MTK_ETH_PATH_GMAC2_SGMII;
225 + path = (mac_id == MTK_GMAC1_ID) ? MTK_ETH_PATH_GMAC1_SGMII :
226 + (mac_id == MTK_GMAC2_ID) ? MTK_ETH_PATH_GMAC2_SGMII :
227 + MTK_ETH_PATH_GMAC3_SGMII;
229 + /* Setup proper MUXes along the path */
230 + return mtk_eth_mux_setup(eth, path);
233 +int mtk_gmac_2p5gphy_path_setup(struct mtk_eth *eth, int mac_id)
237 + if (mac_id == MTK_GMAC2_ID)
238 + path = MTK_ETH_PATH_GMAC2_2P5GPHY;
243 /* Setup proper MUXes along the path */
244 return mtk_eth_mux_setup(eth, path);
245 @@ -284,4 +398,3 @@ int mtk_gmac_rgmii_path_setup(struct mtk
246 /* Setup proper MUXes along the path */
247 return mtk_eth_mux_setup(eth, path);
250 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
251 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
252 @@ -475,6 +475,30 @@ static void mtk_setup_bridge_switch(stru
256 +static bool mtk_check_gmac23_idle(struct mtk_mac *mac)
258 + u32 mac_fsm, gdm_fsm;
260 + mac_fsm = mtk_r32(mac->hw, MTK_MAC_FSM(mac->id));
264 + gdm_fsm = mtk_r32(mac->hw, MTK_FE_GDM2_FSM);
267 + gdm_fsm = mtk_r32(mac->hw, MTK_FE_GDM3_FSM);
273 + if ((mac_fsm & 0xFFFF0000) == 0x01010000 &&
274 + (gdm_fsm & 0xFFFF0000) == 0x00000000)
280 static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config,
281 phy_interface_t interface)
283 @@ -483,12 +507,20 @@ static struct phylink_pcs *mtk_mac_selec
284 struct mtk_eth *eth = mac->hw;
287 - if (interface == PHY_INTERFACE_MODE_SGMII ||
288 - phy_interface_mode_is_8023z(interface)) {
289 - sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
292 - return eth->sgmii_pcs[sid];
293 + if ((interface == PHY_INTERFACE_MODE_SGMII ||
294 + phy_interface_mode_is_8023z(interface)) &&
295 + MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
296 + sid = mtk_mac2xgmii_id(eth, mac->id);
297 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII))
298 + return mtk_sgmii_wrapper_select_pcs(eth, mac->id);
300 + return eth->sgmii_pcs[sid];
301 + } else if ((interface == PHY_INTERFACE_MODE_USXGMII ||
302 + interface == PHY_INTERFACE_MODE_10GBASER ||
303 + interface == PHY_INTERFACE_MODE_5GBASER) &&
304 + MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII) &&
305 + mac->id != MTK_GMAC1_ID) {
306 + return mtk_usxgmii_select_pcs(eth, mac->id);
310 @@ -544,7 +576,22 @@ static void mtk_mac_config(struct phylin
314 + case PHY_INTERFACE_MODE_USXGMII:
315 + case PHY_INTERFACE_MODE_10GBASER:
316 + case PHY_INTERFACE_MODE_5GBASER:
317 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII)) {
318 + err = mtk_gmac_usxgmii_path_setup(eth, mac->id);
323 case PHY_INTERFACE_MODE_INTERNAL:
324 + if (mac->id == MTK_GMAC2_ID &&
325 + MTK_HAS_CAPS(eth->soc->caps, MTK_2P5GPHY)) {
326 + err = mtk_gmac_2p5gphy_path_setup(eth, mac->id);
333 @@ -599,8 +646,6 @@ static void mtk_mac_config(struct phylin
334 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
335 val |= SYSCFG0_GE_MODE(ge_mode, mac->id);
336 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
338 - mac->interface = state->interface;
342 @@ -617,21 +662,40 @@ static void mtk_mac_config(struct phylin
344 /* Save the syscfg0 value for mac_finish */
346 - } else if (phylink_autoneg_inband(mode)) {
347 + } else if (state->interface != PHY_INTERFACE_MODE_USXGMII &&
348 + state->interface != PHY_INTERFACE_MODE_10GBASER &&
349 + state->interface != PHY_INTERFACE_MODE_5GBASER &&
350 + phylink_autoneg_inband(mode)) {
352 - "In-band mode not supported in non SGMII mode!\n");
353 + "In-band mode not supported in non-SerDes modes!\n");
358 - if (mtk_is_netsys_v3_or_greater(eth) &&
359 - mac->interface == PHY_INTERFACE_MODE_INTERNAL) {
360 - mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id));
361 - mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id));
362 + if (mtk_is_netsys_v3_or_greater(eth)) {
363 + if (mtk_interface_mode_is_xgmii(state->interface)) {
364 + mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id));
365 + mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id));
367 + if (mac->id == MTK_GMAC1_ID)
368 + mtk_setup_bridge_switch(eth);
370 + mtk_w32(eth, 0, MTK_GDMA_EG_CTRL(mac->id));
372 - mtk_setup_bridge_switch(eth);
373 + /* FIXME: In current hardware design, we have to reset FE
374 + * when swtiching XGDM to GDM. Therefore, here trigger an SER
375 + * to let GDM go back to the initial state.
377 + if ((mtk_interface_mode_is_xgmii(mac->interface) ||
378 + mac->interface == PHY_INTERFACE_MODE_NA) &&
379 + !mtk_check_gmac23_idle(mac) &&
380 + !test_bit(MTK_RESETTING, ð->state))
381 + schedule_work(ð->pending_work);
385 + mac->interface = state->interface;
390 @@ -677,10 +741,13 @@ static void mtk_mac_link_down(struct phy
392 struct mtk_mac *mac = container_of(config, struct mtk_mac,
394 - u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
396 - mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN);
397 - mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
398 + if (!mtk_interface_mode_is_xgmii(interface)) {
399 + mtk_m32(mac->hw, MAC_MCR_TX_EN | MAC_MCR_RX_EN, 0, MTK_MAC_MCR(mac->id));
400 + mtk_m32(mac->hw, MTK_XGMAC_FORCE_LINK(mac->id), 0, MTK_XGMAC_STS(mac->id));
401 + } else if (mac->id != MTK_GMAC1_ID) {
402 + mtk_m32(mac->hw, XMAC_MCR_TRX_DISABLE, XMAC_MCR_TRX_DISABLE, MTK_XMAC_MCR(mac->id));
406 static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx,
407 @@ -752,13 +819,11 @@ static void mtk_set_queue_speed(struct m
408 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs);
411 -static void mtk_mac_link_up(struct phylink_config *config,
412 - struct phy_device *phy,
413 - unsigned int mode, phy_interface_t interface,
414 - int speed, int duplex, bool tx_pause, bool rx_pause)
415 +static void mtk_gdm_mac_link_up(struct mtk_mac *mac,
416 + struct phy_device *phy,
417 + unsigned int mode, phy_interface_t interface,
418 + int speed, int duplex, bool tx_pause, bool rx_pause)
420 - struct mtk_mac *mac = container_of(config, struct mtk_mac,
424 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
425 @@ -792,6 +857,55 @@ static void mtk_mac_link_up(struct phyli
426 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
429 +static void mtk_xgdm_mac_link_up(struct mtk_mac *mac,
430 + struct phy_device *phy,
431 + unsigned int mode, phy_interface_t interface,
432 + int speed, int duplex, bool tx_pause, bool rx_pause)
434 + u32 mcr, force_link = 0;
436 + if (mac->id == MTK_GMAC1_ID)
439 + /* Eliminate the interference(before link-up) caused by PHY noise */
440 + mtk_m32(mac->hw, XMAC_LOGIC_RST, 0, MTK_XMAC_LOGIC_RST(mac->id));
442 + mtk_m32(mac->hw, XMAC_GLB_CNTCLR, XMAC_GLB_CNTCLR, MTK_XMAC_CNT_CTRL(mac->id));
444 + if (mac->interface == PHY_INTERFACE_MODE_INTERNAL || mac->id == MTK_GMAC3_ID)
445 + force_link = MTK_XGMAC_FORCE_LINK(mac->id);
447 + mtk_m32(mac->hw, MTK_XGMAC_FORCE_LINK(mac->id), force_link, MTK_XGMAC_STS(mac->id));
449 + mcr = mtk_r32(mac->hw, MTK_XMAC_MCR(mac->id));
450 + mcr &= ~(XMAC_MCR_FORCE_TX_FC | XMAC_MCR_FORCE_RX_FC | XMAC_MCR_TRX_DISABLE);
451 + /* Configure pause modes -
452 + * phylink will avoid these for half duplex
455 + mcr |= XMAC_MCR_FORCE_TX_FC;
457 + mcr |= XMAC_MCR_FORCE_RX_FC;
459 + mtk_w32(mac->hw, mcr, MTK_XMAC_MCR(mac->id));
462 +static void mtk_mac_link_up(struct phylink_config *config,
463 + struct phy_device *phy,
464 + unsigned int mode, phy_interface_t interface,
465 + int speed, int duplex, bool tx_pause, bool rx_pause)
467 + struct mtk_mac *mac = container_of(config, struct mtk_mac,
470 + if (mtk_interface_mode_is_xgmii(interface))
471 + mtk_xgdm_mac_link_up(mac, phy, mode, interface, speed, duplex,
472 + tx_pause, rx_pause);
474 + mtk_gdm_mac_link_up(mac, phy, mode, interface, speed, duplex,
475 + tx_pause, rx_pause);
478 static const struct phylink_mac_ops mtk_phylink_ops = {
479 .validate = phylink_generic_validate,
480 .mac_select_pcs = mtk_mac_select_pcs,
481 @@ -4617,8 +4731,21 @@ static int mtk_add_mac(struct mtk_eth *e
482 phy_interface_zero(mac->phylink_config.supported_interfaces);
483 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
484 mac->phylink_config.supported_interfaces);
485 + } else if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_USXGMII)) {
486 + mac->phylink_config.mac_capabilities |= MAC_5000FD | MAC_10000FD;
487 + __set_bit(PHY_INTERFACE_MODE_5GBASER,
488 + mac->phylink_config.supported_interfaces);
489 + __set_bit(PHY_INTERFACE_MODE_10GBASER,
490 + mac->phylink_config.supported_interfaces);
491 + __set_bit(PHY_INTERFACE_MODE_USXGMII,
492 + mac->phylink_config.supported_interfaces);
495 + if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_2P5GPHY) &&
496 + id == MTK_GMAC2_ID)
497 + __set_bit(PHY_INTERFACE_MODE_INTERNAL,
498 + mac->phylink_config.supported_interfaces);
500 phylink = phylink_create(&mac->phylink_config,
501 of_fwnode_handle(mac->of_node),
502 phy_mode, &mtk_phylink_ops);
503 @@ -4811,6 +4938,13 @@ static int mtk_probe(struct platform_dev
509 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII)) {
510 + err = mtk_usxgmii_init(eth);
516 if (eth->soc->required_pctl) {
517 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
518 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
520 #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED)
521 #define INTF_MODE_RGMII_10_100 0
523 +/* XFI Mac control registers */
524 +#define MTK_XMAC_BASE(x) (0x12000 + (((x) - 1) * 0x1000))
525 +#define MTK_XMAC_MCR(x) (MTK_XMAC_BASE(x))
526 +#define XMAC_MCR_TRX_DISABLE 0xf
527 +#define XMAC_MCR_FORCE_TX_FC BIT(5)
528 +#define XMAC_MCR_FORCE_RX_FC BIT(4)
530 +/* XFI Mac logic reset registers */
531 +#define MTK_XMAC_LOGIC_RST(x) (MTK_XMAC_BASE(x) + 0x10)
532 +#define XMAC_LOGIC_RST BIT(0)
534 +/* XFI Mac count global control */
535 +#define MTK_XMAC_CNT_CTRL(x) (MTK_XMAC_BASE(x) + 0x100)
536 +#define XMAC_GLB_CNTCLR BIT(0)
538 /* GPIO port control registers for GMAC 2*/
539 #define GPIO_OD33_CTRL8 0x4c0
540 #define GPIO_BIAS_CTRL 0xed0
542 #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK)
543 #define SYSCFG0_SGMII_GMAC1_V2 BIT(9)
544 #define SYSCFG0_SGMII_GMAC2_V2 BIT(8)
545 +#define SYSCFG0_SGMII_GMAC3_V2 BIT(7)
548 /* ethernet subsystem clock register */
549 @@ -559,12 +575,74 @@
550 #define ETHSYS_DMA_AG_MAP_QDMA BIT(1)
551 #define ETHSYS_DMA_AG_MAP_PPE BIT(2)
553 +/* USXGMII subsystem config registers */
554 +/* Register to control speed */
555 +#define RG_PHY_TOP_SPEED_CTRL1 0x80C
556 +#define USXGMII_RATE_UPDATE_MODE BIT(31)
557 +#define USXGMII_MAC_CK_GATED BIT(29)
558 +#define USXGMII_IF_FORCE_EN BIT(28)
559 +#define USXGMII_RATE_ADAPT_MODE GENMASK(10, 8)
560 +#define USXGMII_RATE_ADAPT_MODE_X1 0
561 +#define USXGMII_RATE_ADAPT_MODE_X2 1
562 +#define USXGMII_RATE_ADAPT_MODE_X4 2
563 +#define USXGMII_RATE_ADAPT_MODE_X10 3
564 +#define USXGMII_RATE_ADAPT_MODE_X100 4
565 +#define USXGMII_RATE_ADAPT_MODE_X5 5
566 +#define USXGMII_RATE_ADAPT_MODE_X50 6
567 +#define USXGMII_XFI_RX_MODE GENMASK(6, 4)
568 +#define USXGMII_XFI_RX_MODE_10G 0
569 +#define USXGMII_XFI_RX_MODE_5G 1
570 +#define USXGMII_XFI_TX_MODE GENMASK(2, 0)
571 +#define USXGMII_XFI_TX_MODE_10G 0
572 +#define USXGMII_XFI_TX_MODE_5G 1
574 +/* Register to control PCS AN */
575 +#define RG_PCS_AN_CTRL0 0x810
576 +#define USXGMII_AN_RESTART BIT(31)
577 +#define USXGMII_AN_SYNC_CNT GENMASK(30, 11)
578 +#define USXGMII_AN_ENABLE BIT(0)
580 +#define RG_PCS_AN_CTRL2 0x818
581 +#define USXGMII_LINK_TIMER_IDLE_DETECT GENMASK(29, 20)
582 +#define USXGMII_LINK_TIMER_COMP_ACK_DETECT GENMASK(19, 10)
583 +#define USXGMII_LINK_TIMER_AN_RESTART GENMASK(9, 0)
585 +/* Register to read PCS AN status */
586 +#define RG_PCS_AN_STS0 0x81c
587 +#define USXGMII_PCS_AN_WORD GENMASK(15, 0)
588 +#define USXGMII_LPA_LATCH BIT(31)
590 +/* Register to control USXGMII XFI PLL digital */
591 +#define XFI_PLL_DIG_GLB8 0x08
592 +#define RG_XFI_PLL_EN BIT(31)
594 +/* Register to control USXGMII XFI PLL analog */
595 +#define XFI_PLL_ANA_GLB8 0x108
596 +#define RG_XFI_PLL_ANA_SWWA 0x02283248
598 /* Infrasys subsystem config registers */
599 #define INFRA_MISC2 0x70c
600 #define CO_QPHY_SEL BIT(0)
601 #define GEPHY_MAC_SEL BIT(1)
603 +/* Toprgu subsystem config registers */
604 +#define TOPRGU_SWSYSRST 0x18
605 +#define SWSYSRST_UNLOCK_KEY GENMASK(31, 24)
606 +#define SWSYSRST_XFI_PLL_GRST BIT(16)
607 +#define SWSYSRST_XFI_PEXPT1_GRST BIT(15)
608 +#define SWSYSRST_XFI_PEXPT0_GRST BIT(14)
609 +#define SWSYSRST_XFI1_GRST BIT(13)
610 +#define SWSYSRST_XFI0_GRST BIT(12)
611 +#define SWSYSRST_SGMII1_GRST BIT(2)
612 +#define SWSYSRST_SGMII0_GRST BIT(1)
613 +#define TOPRGU_SWSYSRST_EN 0xFC
615 /* Top misc registers */
616 +#define TOP_MISC_NETSYS_PCS_MUX 0x84
617 +#define NETSYS_PCS_MUX_MASK GENMASK(1, 0)
618 +#define MUX_G2_USXGMII_SEL BIT(1)
619 +#define MUX_HSGMII1_G1_SEL BIT(0)
621 #define USB_PHY_SWITCH_REG 0x218
622 #define QPHY_SEL_MASK GENMASK(1, 0)
623 #define SGMII_QPHY_SEL 0x2
625 #define MT7628_SDM_RBCNT (MT7628_SDM_OFFSET + 0x10c)
626 #define MT7628_SDM_CS_ERR (MT7628_SDM_OFFSET + 0x110)
628 +/* Debug Purpose Register */
629 +#define MTK_PSE_FQFC_CFG 0x100
630 #define MTK_FE_CDM1_FSM 0x220
631 #define MTK_FE_CDM2_FSM 0x224
632 #define MTK_FE_CDM3_FSM 0x238
634 #define MTK_FE_CDM6_FSM 0x328
635 #define MTK_FE_GDM1_FSM 0x228
636 #define MTK_FE_GDM2_FSM 0x22C
637 +#define MTK_FE_GDM3_FSM 0x23C
638 +#define MTK_FE_PSE_FREE 0x240
639 +#define MTK_FE_DROP_FQ 0x244
640 +#define MTK_FE_DROP_FC 0x248
641 +#define MTK_FE_DROP_PPE 0x24C
643 #define MTK_MAC_FSM(x) (0x1010C + ((x) * 0x100))
645 @@ -943,6 +1028,8 @@ enum mkt_eth_capabilities {
654 @@ -963,8 +1050,11 @@ enum mkt_eth_capabilities {
655 MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
656 MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT,
657 MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT,
658 + MTK_ETH_MUX_GMAC2_TO_2P5GPHY_BIT,
659 MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT,
660 MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT,
661 + MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII_BIT,
662 + MTK_ETH_MUX_GMAC123_TO_USXGMII_BIT,
665 MTK_ETH_PATH_GMAC1_RGMII_BIT,
666 @@ -972,14 +1062,21 @@ enum mkt_eth_capabilities {
667 MTK_ETH_PATH_GMAC1_SGMII_BIT,
668 MTK_ETH_PATH_GMAC2_RGMII_BIT,
669 MTK_ETH_PATH_GMAC2_SGMII_BIT,
670 + MTK_ETH_PATH_GMAC2_2P5GPHY_BIT,
671 MTK_ETH_PATH_GMAC2_GEPHY_BIT,
672 + MTK_ETH_PATH_GMAC3_SGMII_BIT,
673 MTK_ETH_PATH_GDM1_ESW_BIT,
674 + MTK_ETH_PATH_GMAC1_USXGMII_BIT,
675 + MTK_ETH_PATH_GMAC2_USXGMII_BIT,
676 + MTK_ETH_PATH_GMAC3_USXGMII_BIT,
679 /* Supported hardware group on SoCs */
680 #define MTK_RGMII BIT_ULL(MTK_RGMII_BIT)
681 #define MTK_TRGMII BIT_ULL(MTK_TRGMII_BIT)
682 #define MTK_SGMII BIT_ULL(MTK_SGMII_BIT)
683 +#define MTK_USXGMII BIT_ULL(MTK_USXGMII_BIT)
684 +#define MTK_2P5GPHY BIT_ULL(MTK_2P5GPHY_BIT)
685 #define MTK_ESW BIT_ULL(MTK_ESW_BIT)
686 #define MTK_GEPHY BIT_ULL(MTK_GEPHY_BIT)
687 #define MTK_MUX BIT_ULL(MTK_MUX_BIT)
688 @@ -1002,10 +1099,16 @@ enum mkt_eth_capabilities {
689 BIT_ULL(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT)
690 #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \
691 BIT_ULL(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT)
692 +#define MTK_ETH_MUX_GMAC2_TO_2P5GPHY \
693 + BIT_ULL(MTK_ETH_MUX_GMAC2_TO_2P5GPHY_BIT)
694 #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \
695 BIT_ULL(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT)
696 #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \
697 BIT_ULL(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT)
698 +#define MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII \
699 + BIT_ULL(MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII_BIT)
700 +#define MTK_ETH_MUX_GMAC123_TO_USXGMII \
701 + BIT_ULL(MTK_ETH_MUX_GMAC123_TO_USXGMII_BIT)
703 /* Supported path present on SoCs */
704 #define MTK_ETH_PATH_GMAC1_RGMII BIT_ULL(MTK_ETH_PATH_GMAC1_RGMII_BIT)
705 @@ -1013,8 +1116,13 @@ enum mkt_eth_capabilities {
706 #define MTK_ETH_PATH_GMAC1_SGMII BIT_ULL(MTK_ETH_PATH_GMAC1_SGMII_BIT)
707 #define MTK_ETH_PATH_GMAC2_RGMII BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT)
708 #define MTK_ETH_PATH_GMAC2_SGMII BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT)
709 +#define MTK_ETH_PATH_GMAC2_2P5GPHY BIT_ULL(MTK_ETH_PATH_GMAC2_2P5GPHY_BIT)
710 #define MTK_ETH_PATH_GMAC2_GEPHY BIT_ULL(MTK_ETH_PATH_GMAC2_GEPHY_BIT)
711 +#define MTK_ETH_PATH_GMAC3_SGMII BIT_ULL(MTK_ETH_PATH_GMAC3_SGMII_BIT)
712 #define MTK_ETH_PATH_GDM1_ESW BIT_ULL(MTK_ETH_PATH_GDM1_ESW_BIT)
713 +#define MTK_ETH_PATH_GMAC1_USXGMII BIT_ULL(MTK_ETH_PATH_GMAC1_USXGMII_BIT)
714 +#define MTK_ETH_PATH_GMAC2_USXGMII BIT_ULL(MTK_ETH_PATH_GMAC2_USXGMII_BIT)
715 +#define MTK_ETH_PATH_GMAC3_USXGMII BIT_ULL(MTK_ETH_PATH_GMAC3_USXGMII_BIT)
717 #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII)
718 #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
719 @@ -1022,7 +1130,12 @@ enum mkt_eth_capabilities {
720 #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII)
721 #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII)
722 #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY)
723 +#define MTK_GMAC2_2P5GPHY (MTK_ETH_PATH_GMAC2_2P5GPHY | MTK_2P5GPHY)
724 +#define MTK_GMAC3_SGMII (MTK_ETH_PATH_GMAC3_SGMII | MTK_SGMII)
725 #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW)
726 +#define MTK_GMAC1_USXGMII (MTK_ETH_PATH_GMAC1_USXGMII | MTK_USXGMII)
727 +#define MTK_GMAC2_USXGMII (MTK_ETH_PATH_GMAC2_USXGMII | MTK_USXGMII)
728 +#define MTK_GMAC3_USXGMII (MTK_ETH_PATH_GMAC3_USXGMII | MTK_USXGMII)
730 /* MUXes present on SoCs */
731 /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */
732 @@ -1041,10 +1154,20 @@ enum mkt_eth_capabilities {
733 (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \
736 +/* 2: GMAC2 -> XGMII */
737 +#define MTK_MUX_GMAC2_TO_2P5GPHY \
738 + (MTK_ETH_MUX_GMAC2_TO_2P5GPHY | MTK_MUX | MTK_INFRA)
740 /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */
741 #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \
742 (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX)
744 +#define MTK_MUX_GMAC123_TO_GEPHY_SGMII \
745 + (MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII | MTK_MUX)
747 +#define MTK_MUX_GMAC123_TO_USXGMII \
748 + (MTK_ETH_MUX_GMAC123_TO_USXGMII | MTK_MUX | MTK_INFRA)
750 #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x))
752 #define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \
753 @@ -1076,8 +1199,12 @@ enum mkt_eth_capabilities {
754 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
755 MTK_RSTCTRL_PPE1 | MTK_SRAM)
757 -#define MT7988_CAPS (MTK_36BIT_DMA | MTK_GDM1_ESW | MTK_QDMA | \
758 - MTK_RSTCTRL_PPE1 | MTK_RSTCTRL_PPE2 | MTK_SRAM)
759 +#define MT7988_CAPS (MTK_36BIT_DMA | MTK_GDM1_ESW | MTK_GMAC1_SGMII | \
760 + MTK_GMAC2_2P5GPHY | MTK_GMAC2_SGMII | MTK_GMAC2_USXGMII | \
761 + MTK_GMAC3_SGMII | MTK_GMAC3_USXGMII | \
762 + MTK_MUX_GMAC123_TO_GEPHY_SGMII | \
763 + MTK_MUX_GMAC123_TO_USXGMII | MTK_MUX_GMAC2_TO_2P5GPHY | \
764 + MTK_QDMA | MTK_RSTCTRL_PPE1 | MTK_RSTCTRL_PPE2 | MTK_SRAM)
766 struct mtk_tx_dma_desc_info {
768 @@ -1187,6 +1314,24 @@ struct mtk_soc_data {
769 /* currently no SoC has more than 3 macs */
770 #define MTK_MAX_DEVS 3
772 +/* struct mtk_usxgmii_pcs - This structure holds each usxgmii regmap and
774 + * @regmap: The register map pointing at the range used to setup
776 + * @interface: Currently selected interface mode
777 + * @id: The element is used to record the index of PCS
778 + * @pcs: Phylink PCS structure
780 +struct mtk_usxgmii_pcs {
781 + struct mtk_eth *eth;
782 + struct regmap *regmap;
783 + struct phylink_pcs *wrapped_sgmii_pcs;
784 + phy_interface_t interface;
787 + struct phylink_pcs pcs;
790 /* struct mtk_eth - This is the main datasructure for holding the state
792 * @dev: The device pointer
793 @@ -1207,6 +1352,12 @@ struct mtk_soc_data {
794 * @infra: The register map pointing at the range used to setup
795 * SGMII and GePHY path
796 * @sgmii_pcs: Pointers to mtk-pcs-lynxi phylink_pcs instances
797 + * @sgmii_wrapped_pcs: Pointers to NETSYSv3 wrapper PCS instances
798 + * @usxgmii_pll: The register map pointing at the range used to control
799 + * the USXGMII SerDes PLL
800 + * @regmap_pextp: The register map pointing at the range used to setup
802 + * @usxgmii_pcs: Pointer to array of pointers to struct for USXGMII PCS
803 * @pctl: The register map pointing at the range used to setup
804 * GMAC port drive/slew values
805 * @dma_refcnt: track how many netdevs are using the DMA engine
806 @@ -1250,6 +1401,10 @@ struct mtk_eth {
807 struct regmap *ethsys;
808 struct regmap *infra;
809 struct phylink_pcs *sgmii_pcs[MTK_MAX_DEVS];
810 + struct regmap *toprgu;
811 + struct regmap *usxgmii_pll;
812 + struct regmap *regmap_pextp[MTK_MAX_DEVS];
813 + struct mtk_usxgmii_pcs *usxgmii_pcs[MTK_MAX_DEVS];
816 refcount_t dma_refcnt;
817 @@ -1437,6 +1592,19 @@ static inline u32 mtk_get_ib2_multicast_
818 return MTK_FOE_IB2_MULTICAST;
821 +static inline bool mtk_interface_mode_is_xgmii(phy_interface_t interface)
823 + switch (interface) {
824 + case PHY_INTERFACE_MODE_INTERNAL:
825 + case PHY_INTERFACE_MODE_USXGMII:
826 + case PHY_INTERFACE_MODE_10GBASER:
827 + case PHY_INTERFACE_MODE_5GBASER:
834 /* read the hardware status register */
835 void mtk_stats_update_mac(struct mtk_mac *mac);
837 @@ -1445,8 +1613,10 @@ u32 mtk_r32(struct mtk_eth *eth, unsigne
838 u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg);
840 int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id);
841 +int mtk_gmac_2p5gphy_path_setup(struct mtk_eth *eth, int mac_id);
842 int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);
843 int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id);
844 +int mtk_gmac_usxgmii_path_setup(struct mtk_eth *eth, int mac_id);
846 int mtk_eth_offload_init(struct mtk_eth *eth);
847 int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type,
848 @@ -1456,5 +1626,63 @@ int mtk_flow_offload_cmd(struct mtk_eth
849 void mtk_flow_offload_cleanup(struct mtk_eth *eth, struct list_head *list);
850 void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev);
852 +static inline int mtk_mac2xgmii_id(struct mtk_eth *eth, int mac_id)
854 + int xgmii_id = mac_id;
856 + if (mtk_is_netsys_v3_or_greater(eth)) {
870 + return MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII) ? 0 : xgmii_id;
873 +static inline int mtk_xgmii2mac_id(struct mtk_eth *eth, int xgmii_id)
875 + int mac_id = xgmii_id;
877 + if (mtk_is_netsys_v3_or_greater(eth)) {
878 + switch (xgmii_id) {
893 +#ifdef CONFIG_NET_MEDIATEK_SOC_USXGMII
894 +struct phylink_pcs *mtk_sgmii_wrapper_select_pcs(struct mtk_eth *eth, int id);
895 +struct phylink_pcs *mtk_usxgmii_select_pcs(struct mtk_eth *eth, int id);
896 +int mtk_usxgmii_init(struct mtk_eth *eth);
898 +static inline struct phylink_pcs *mtk_sgmii_wrapper_select_pcs(struct mtk_eth *eth, int id)
903 +static inline struct phylink_pcs *mtk_usxgmii_select_pcs(struct mtk_eth *eth, int id)
908 +static inline int mtk_usxgmii_init(struct mtk_eth *eth) { return 0; }
909 +#endif /* NET_MEDIATEK_SOC_USXGMII */
911 #endif /* MTK_ETH_H */
913 +++ b/drivers/net/ethernet/mediatek/mtk_usxgmii.c
915 +// SPDX-License-Identifier: GPL-2.0
917 + * Copyright (c) 2023 MediaTek Inc.
918 + * Author: Henry Yen <henry.yen@mediatek.com>
919 + * Daniel Golle <daniel@makrotopia.org>
922 +#include <linux/mfd/syscon.h>
923 +#include <linux/of.h>
924 +#include <linux/regmap.h>
925 +#include "mtk_eth_soc.h"
927 +static struct mtk_usxgmii_pcs *pcs_to_mtk_usxgmii_pcs(struct phylink_pcs *pcs)
929 + return container_of(pcs, struct mtk_usxgmii_pcs, pcs);
932 +static int mtk_xfi_pextp_init(struct mtk_eth *eth)
934 + struct device *dev = eth->dev;
935 + struct device_node *r = dev->of_node;
936 + struct device_node *np;
939 + for (i = 0; i < MTK_MAX_DEVS; i++) {
940 + np = of_parse_phandle(r, "mediatek,xfi-pextp", i);
944 + eth->regmap_pextp[i] = syscon_node_to_regmap(np);
945 + if (IS_ERR(eth->regmap_pextp[i]))
946 + return PTR_ERR(eth->regmap_pextp[i]);
952 +static int mtk_xfi_pll_init(struct mtk_eth *eth)
954 + struct device_node *r = eth->dev->of_node;
955 + struct device_node *np;
957 + np = of_parse_phandle(r, "mediatek,xfi-pll", 0);
961 + eth->usxgmii_pll = syscon_node_to_regmap(np);
962 + if (IS_ERR(eth->usxgmii_pll))
963 + return PTR_ERR(eth->usxgmii_pll);
968 +static int mtk_toprgu_init(struct mtk_eth *eth)
970 + struct device_node *r = eth->dev->of_node;
971 + struct device_node *np;
973 + np = of_parse_phandle(r, "mediatek,toprgu", 0);
977 + eth->toprgu = syscon_node_to_regmap(np);
978 + if (IS_ERR(eth->toprgu))
979 + return PTR_ERR(eth->toprgu);
984 +static int mtk_xfi_pll_enable(struct mtk_eth *eth)
988 + if (!eth->usxgmii_pll)
991 + /* Add software workaround for USXGMII PLL TCL issue */
992 + regmap_write(eth->usxgmii_pll, XFI_PLL_ANA_GLB8, RG_XFI_PLL_ANA_SWWA);
994 + regmap_read(eth->usxgmii_pll, XFI_PLL_DIG_GLB8, &val);
995 + val |= RG_XFI_PLL_EN;
996 + regmap_write(eth->usxgmii_pll, XFI_PLL_DIG_GLB8, val);
1001 +static void mtk_usxgmii_setup_phya(struct regmap *pextp, phy_interface_t interface, int id)
1003 + bool is_10g = (interface == PHY_INTERFACE_MODE_10GBASER ||
1004 + interface == PHY_INTERFACE_MODE_USXGMII);
1005 + bool is_2p5g = (interface == PHY_INTERFACE_MODE_2500BASEX);
1006 + bool is_5g = (interface == PHY_INTERFACE_MODE_5GBASER);
1008 + /* Setup operation mode */
1010 + regmap_write(pextp, 0x9024, 0x00C9071C);
1012 + regmap_write(pextp, 0x9024, 0x00D9071C);
1015 + regmap_write(pextp, 0x2020, 0xAAA5A5AA);
1017 + regmap_write(pextp, 0x2020, 0xAA8585AA);
1019 + if (is_2p5g || is_5g || is_10g) {
1020 + regmap_write(pextp, 0x2030, 0x0C020707);
1021 + regmap_write(pextp, 0x2034, 0x0E050F0F);
1022 + regmap_write(pextp, 0x2040, 0x00140032);
1024 + regmap_write(pextp, 0x2030, 0x0C020207);
1025 + regmap_write(pextp, 0x2034, 0x0E05050F);
1026 + regmap_write(pextp, 0x2040, 0x00200032);
1029 + if (is_2p5g || is_10g)
1030 + regmap_write(pextp, 0x50F0, 0x00C014AA);
1032 + regmap_write(pextp, 0x50F0, 0x00C018AA);
1034 + regmap_write(pextp, 0x50F0, 0x00C014BA);
1037 + regmap_write(pextp, 0x50E0, 0x3777812B);
1038 + regmap_write(pextp, 0x506C, 0x005C9CFF);
1039 + regmap_write(pextp, 0x5070, 0x9DFAFAFA);
1040 + regmap_write(pextp, 0x5074, 0x273F3F3F);
1041 + regmap_write(pextp, 0x5078, 0xA8883868);
1042 + regmap_write(pextp, 0x507C, 0x14661466);
1044 + regmap_write(pextp, 0x50E0, 0x3777C12B);
1045 + regmap_write(pextp, 0x506C, 0x005F9CFF);
1046 + regmap_write(pextp, 0x5070, 0x9D9DFAFA);
1047 + regmap_write(pextp, 0x5074, 0x27273F3F);
1048 + regmap_write(pextp, 0x5078, 0xA7883C68);
1049 + regmap_write(pextp, 0x507C, 0x11661166);
1052 + if (is_2p5g || is_10g) {
1053 + regmap_write(pextp, 0x5080, 0x0E000AAF);
1054 + regmap_write(pextp, 0x5084, 0x08080D0D);
1055 + regmap_write(pextp, 0x5088, 0x02030909);
1056 + } else if (is_5g) {
1057 + regmap_write(pextp, 0x5080, 0x0E001ABF);
1058 + regmap_write(pextp, 0x5084, 0x080B0D0D);
1059 + regmap_write(pextp, 0x5088, 0x02050909);
1061 + regmap_write(pextp, 0x5080, 0x0E000EAF);
1062 + regmap_write(pextp, 0x5084, 0x08080E0D);
1063 + regmap_write(pextp, 0x5088, 0x02030B09);
1067 + regmap_write(pextp, 0x50E4, 0x0C000000);
1068 + regmap_write(pextp, 0x50E8, 0x04000000);
1070 + regmap_write(pextp, 0x50E4, 0x0C0C0000);
1071 + regmap_write(pextp, 0x50E8, 0x04040000);
1074 + if (is_2p5g || mtk_interface_mode_is_xgmii(interface))
1075 + regmap_write(pextp, 0x50EC, 0x0F0F0C06);
1077 + regmap_write(pextp, 0x50EC, 0x0F0F0606);
1080 + regmap_write(pextp, 0x50A8, 0x50808C8C);
1081 + regmap_write(pextp, 0x6004, 0x18000000);
1083 + regmap_write(pextp, 0x50A8, 0x506E8C8C);
1084 + regmap_write(pextp, 0x6004, 0x18190000);
1088 + regmap_write(pextp, 0x00F8, 0x01423342);
1090 + regmap_write(pextp, 0x00F8, 0x00A132A1);
1092 + regmap_write(pextp, 0x00F8, 0x009C329C);
1094 + regmap_write(pextp, 0x00F8, 0x00FA32FA);
1096 + /* Force SGDT_OUT off and select PCS */
1097 + if (mtk_interface_mode_is_xgmii(interface))
1098 + regmap_write(pextp, 0x00F4, 0x80201F20);
1100 + regmap_write(pextp, 0x00F4, 0x80201F21);
1102 + /* Force GLB_CKDET_OUT */
1103 + regmap_write(pextp, 0x0030, 0x00050C00);
1105 + /* Force AEQ on */
1106 + regmap_write(pextp, 0x0070, 0x02002800);
1109 + /* Setup DA default value */
1110 + regmap_write(pextp, 0x30B0, 0x00000020);
1111 + regmap_write(pextp, 0x3028, 0x00008A01);
1112 + regmap_write(pextp, 0x302C, 0x0000A884);
1113 + regmap_write(pextp, 0x3024, 0x00083002);
1114 + if (mtk_interface_mode_is_xgmii(interface)) {
1115 + regmap_write(pextp, 0x3010, 0x00022220);
1116 + regmap_write(pextp, 0x5064, 0x0F020A01);
1117 + regmap_write(pextp, 0x50B4, 0x06100600);
1118 + if (interface == PHY_INTERFACE_MODE_USXGMII)
1119 + regmap_write(pextp, 0x3048, 0x40704000);
1121 + regmap_write(pextp, 0x3048, 0x47684100);
1123 + regmap_write(pextp, 0x3010, 0x00011110);
1124 + regmap_write(pextp, 0x3048, 0x40704000);
1127 + if (!mtk_interface_mode_is_xgmii(interface) && !is_2p5g)
1128 + regmap_write(pextp, 0x3064, 0x0000C000);
1130 + if (interface == PHY_INTERFACE_MODE_USXGMII) {
1131 + regmap_write(pextp, 0x3050, 0xA8000000);
1132 + regmap_write(pextp, 0x3054, 0x000000AA);
1133 + } else if (mtk_interface_mode_is_xgmii(interface)) {
1134 + regmap_write(pextp, 0x3050, 0x00000000);
1135 + regmap_write(pextp, 0x3054, 0x00000000);
1137 + regmap_write(pextp, 0x3050, 0xA8000000);
1138 + regmap_write(pextp, 0x3054, 0x000000AA);
1141 + if (mtk_interface_mode_is_xgmii(interface))
1142 + regmap_write(pextp, 0x306C, 0x00000F00);
1144 + regmap_write(pextp, 0x306C, 0x22000F00);
1146 + regmap_write(pextp, 0x306C, 0x20200F00);
1148 + if (interface == PHY_INTERFACE_MODE_10GBASER && id == 0)
1149 + regmap_write(pextp, 0xA008, 0x0007B400);
1151 + if (mtk_interface_mode_is_xgmii(interface))
1152 + regmap_write(pextp, 0xA060, 0x00040000);
1154 + regmap_write(pextp, 0xA060, 0x00050000);
1157 + regmap_write(pextp, 0x90D0, 0x00000001);
1159 + regmap_write(pextp, 0x90D0, 0x00000003);
1161 + regmap_write(pextp, 0x90D0, 0x00000005);
1163 + regmap_write(pextp, 0x90D0, 0x00000007);
1165 + /* Release reset */
1166 + regmap_write(pextp, 0x0070, 0x0200E800);
1167 + usleep_range(150, 500);
1169 + /* Switch to P0 */
1170 + regmap_write(pextp, 0x0070, 0x0200C111);
1172 + regmap_write(pextp, 0x0070, 0x0200C101);
1173 + usleep_range(15, 50);
1175 + if (mtk_interface_mode_is_xgmii(interface)) {
1176 + /* Switch to Gen3 */
1177 + regmap_write(pextp, 0x0070, 0x0202C111);
1179 + /* Switch to Gen2 */
1180 + regmap_write(pextp, 0x0070, 0x0201C111);
1183 + if (mtk_interface_mode_is_xgmii(interface))
1184 + regmap_write(pextp, 0x0070, 0x0202C101);
1186 + regmap_write(pextp, 0x0070, 0x0201C101);
1187 + usleep_range(100, 500);
1188 + regmap_write(pextp, 0x30B0, 0x00000030);
1189 + if (mtk_interface_mode_is_xgmii(interface))
1190 + regmap_write(pextp, 0x00F4, 0x80201F00);
1192 + regmap_write(pextp, 0x00F4, 0x80201F01);
1194 + regmap_write(pextp, 0x3040, 0x30000000);
1195 + usleep_range(400, 1000);
1198 +static void mtk_usxgmii_reset(struct mtk_eth *eth, int id)
1202 + if (id >= MTK_MAX_DEVS || !eth->toprgu)
1207 + toggle = SWSYSRST_XFI_PEXPT0_GRST | SWSYSRST_XFI0_GRST |
1208 + SWSYSRST_SGMII0_GRST;
1211 + toggle = SWSYSRST_XFI_PEXPT1_GRST | SWSYSRST_XFI1_GRST |
1212 + SWSYSRST_SGMII1_GRST;
1218 + /* Enable software reset */
1219 + regmap_set_bits(eth->toprgu, TOPRGU_SWSYSRST_EN, toggle);
1221 + /* Assert USXGMII reset */
1222 + regmap_set_bits(eth->toprgu, TOPRGU_SWSYSRST,
1223 + FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88) | toggle);
1225 + usleep_range(100, 500);
1227 + /* De-assert USXGMII reset */
1228 + regmap_read(eth->toprgu, TOPRGU_SWSYSRST, &val);
1229 + val |= FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88);
1231 + regmap_write(eth->toprgu, TOPRGU_SWSYSRST, val);
1233 + /* Disable software reset */
1234 + regmap_clear_bits(eth->toprgu, TOPRGU_SWSYSRST_EN, toggle);
1239 +/* As the USXGMII PHYA is shared with the 1000Base-X/2500Base-X/Cisco SGMII unit
1240 + * the psc-mtk-lynxi instance needs to be wrapped, so that calls to .pcs_config
1241 + * also trigger an initial reset and subsequent configuration of the PHYA.
1243 +struct mtk_sgmii_wrapper_pcs {
1244 + struct mtk_eth *eth;
1245 + struct phylink_pcs *wrapped_pcs;
1247 + struct phylink_pcs pcs;
1250 +static int mtk_sgmii_wrapped_pcs_config(struct phylink_pcs *pcs,
1251 + unsigned int mode,
1252 + phy_interface_t interface,
1253 + const unsigned long *advertising,
1254 + bool permit_pause_to_mac)
1256 + struct mtk_sgmii_wrapper_pcs *wp = container_of(pcs, struct mtk_sgmii_wrapper_pcs, pcs);
1260 + full_reconf = interface != wp->eth->usxgmii_pcs[wp->id]->interface;
1261 + if (full_reconf) {
1262 + mtk_xfi_pll_enable(wp->eth);
1263 + mtk_usxgmii_reset(wp->eth, wp->id);
1266 + ret = wp->wrapped_pcs->ops->pcs_config(wp->wrapped_pcs, mode, interface,
1267 + advertising, permit_pause_to_mac);
1270 + mtk_usxgmii_setup_phya(wp->eth->regmap_pextp[wp->id], interface, wp->id);
1272 + wp->eth->usxgmii_pcs[wp->id]->interface = interface;
1277 +static void mtk_sgmii_wrapped_pcs_get_state(struct phylink_pcs *pcs,
1278 + struct phylink_link_state *state)
1280 + struct mtk_sgmii_wrapper_pcs *wp = container_of(pcs, struct mtk_sgmii_wrapper_pcs, pcs);
1282 + return wp->wrapped_pcs->ops->pcs_get_state(wp->wrapped_pcs, state);
1285 +static void mtk_sgmii_wrapped_pcs_an_restart(struct phylink_pcs *pcs)
1287 + struct mtk_sgmii_wrapper_pcs *wp = container_of(pcs, struct mtk_sgmii_wrapper_pcs, pcs);
1289 + wp->wrapped_pcs->ops->pcs_an_restart(wp->wrapped_pcs);
1292 +static void mtk_sgmii_wrapped_pcs_link_up(struct phylink_pcs *pcs,
1293 + unsigned int mode,
1294 + phy_interface_t interface, int speed,
1297 + struct mtk_sgmii_wrapper_pcs *wp = container_of(pcs, struct mtk_sgmii_wrapper_pcs, pcs);
1299 + wp->wrapped_pcs->ops->pcs_link_up(wp->wrapped_pcs, mode, interface, speed, duplex);
1302 +static void mtk_sgmii_wrapped_pcs_disable(struct phylink_pcs *pcs)
1304 + struct mtk_sgmii_wrapper_pcs *wp = container_of(pcs, struct mtk_sgmii_wrapper_pcs, pcs);
1306 + wp->wrapped_pcs->ops->pcs_disable(wp->wrapped_pcs);
1308 + wp->eth->usxgmii_pcs[wp->id]->interface = PHY_INTERFACE_MODE_NA;
1311 +static const struct phylink_pcs_ops mtk_sgmii_wrapped_pcs_ops = {
1312 + .pcs_get_state = mtk_sgmii_wrapped_pcs_get_state,
1313 + .pcs_config = mtk_sgmii_wrapped_pcs_config,
1314 + .pcs_an_restart = mtk_sgmii_wrapped_pcs_an_restart,
1315 + .pcs_link_up = mtk_sgmii_wrapped_pcs_link_up,
1316 + .pcs_disable = mtk_sgmii_wrapped_pcs_disable,
1319 +static int mtk_sgmii_wrapper_init(struct mtk_eth *eth)
1321 + struct mtk_sgmii_wrapper_pcs *wp;
1324 + for (i = 0; i < MTK_MAX_DEVS; i++) {
1325 + if (!eth->sgmii_pcs[i])
1328 + if (!eth->usxgmii_pcs[i])
1331 + /* Make sure all PCS ops are supported by wrapped PCS */
1332 + if (!eth->sgmii_pcs[i]->ops->pcs_get_state ||
1333 + !eth->sgmii_pcs[i]->ops->pcs_config ||
1334 + !eth->sgmii_pcs[i]->ops->pcs_an_restart ||
1335 + !eth->sgmii_pcs[i]->ops->pcs_link_up ||
1336 + !eth->sgmii_pcs[i]->ops->pcs_disable)
1337 + return -EOPNOTSUPP;
1339 + wp = devm_kzalloc(eth->dev, sizeof(*wp), GFP_KERNEL);
1343 + wp->wrapped_pcs = eth->sgmii_pcs[i];
1345 + wp->pcs.poll = true;
1346 + wp->pcs.ops = &mtk_sgmii_wrapped_pcs_ops;
1349 + eth->usxgmii_pcs[i]->wrapped_sgmii_pcs = &wp->pcs;
1355 +struct phylink_pcs *mtk_sgmii_wrapper_select_pcs(struct mtk_eth *eth, int mac_id)
1357 + u32 xgmii_id = mtk_mac2xgmii_id(eth, mac_id);
1359 + if (!eth->usxgmii_pcs[xgmii_id])
1362 + return eth->usxgmii_pcs[xgmii_id]->wrapped_sgmii_pcs;
1365 +static int mtk_usxgmii_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
1366 + phy_interface_t interface,
1367 + const unsigned long *advertising,
1368 + bool permit_pause_to_mac)
1370 + struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
1371 + struct mtk_eth *eth = mpcs->eth;
1372 + struct regmap *pextp = eth->regmap_pextp[mpcs->id];
1373 + unsigned int an_ctrl = 0, link_timer = 0, xfi_mode = 0, adapt_mode = 0;
1374 + bool mode_changed = false;
1379 + if (interface == PHY_INTERFACE_MODE_USXGMII) {
1380 + an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0x1FF) | USXGMII_AN_ENABLE;
1381 + link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x7B) |
1382 + FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x7B) |
1383 + FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x7B);
1384 + xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_RX_MODE_10G) |
1385 + FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_TX_MODE_10G);
1386 + } else if (interface == PHY_INTERFACE_MODE_10GBASER) {
1387 + an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0x1FF);
1388 + link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x7B) |
1389 + FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x7B) |
1390 + FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x7B);
1391 + xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_RX_MODE_10G) |
1392 + FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_TX_MODE_10G);
1393 + adapt_mode = USXGMII_RATE_UPDATE_MODE;
1394 + } else if (interface == PHY_INTERFACE_MODE_5GBASER) {
1395 + an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0xFF);
1396 + link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x3D) |
1397 + FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x3D) |
1398 + FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x3D);
1399 + xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_RX_MODE_5G) |
1400 + FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_TX_MODE_5G);
1401 + adapt_mode = USXGMII_RATE_UPDATE_MODE;
1406 + adapt_mode |= FIELD_PREP(USXGMII_RATE_ADAPT_MODE, USXGMII_RATE_ADAPT_MODE_X1);
1408 + if (mpcs->interface != interface) {
1409 + mpcs->interface = interface;
1410 + mode_changed = true;
1413 + mtk_xfi_pll_enable(eth);
1414 + mtk_usxgmii_reset(eth, mpcs->id);
1416 + /* Setup USXGMII AN ctrl */
1417 + regmap_update_bits(mpcs->regmap, RG_PCS_AN_CTRL0,
1418 + USXGMII_AN_SYNC_CNT | USXGMII_AN_ENABLE,
1421 + regmap_update_bits(mpcs->regmap, RG_PCS_AN_CTRL2,
1422 + USXGMII_LINK_TIMER_IDLE_DETECT |
1423 + USXGMII_LINK_TIMER_COMP_ACK_DETECT |
1424 + USXGMII_LINK_TIMER_AN_RESTART,
1427 + mpcs->mode = mode;
1429 + /* Gated MAC CK */
1430 + regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
1431 + USXGMII_MAC_CK_GATED, USXGMII_MAC_CK_GATED);
1433 + /* Enable interface force mode */
1434 + regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
1435 + USXGMII_IF_FORCE_EN, USXGMII_IF_FORCE_EN);
1437 + /* Setup USXGMII adapt mode */
1438 + regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
1439 + USXGMII_RATE_UPDATE_MODE | USXGMII_RATE_ADAPT_MODE,
1442 + /* Setup USXGMII speed */
1443 + regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
1444 + USXGMII_XFI_RX_MODE | USXGMII_XFI_TX_MODE,
1447 + usleep_range(1, 10);
1449 + /* Un-gated MAC CK */
1450 + regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
1451 + USXGMII_MAC_CK_GATED, 0);
1453 + usleep_range(1, 10);
1455 + /* Disable interface force mode for the AN mode */
1456 + if (an_ctrl & USXGMII_AN_ENABLE)
1457 + regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
1458 + USXGMII_IF_FORCE_EN, 0);
1460 + /* Setup USXGMIISYS with the determined property */
1461 + mtk_usxgmii_setup_phya(pextp, interface, mpcs->id);
1463 + return mode_changed;
1466 +static void mtk_usxgmii_pcs_get_state(struct phylink_pcs *pcs,
1467 + struct phylink_link_state *state)
1469 + struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
1470 + struct mtk_eth *eth = mpcs->eth;
1471 + struct mtk_mac *mac = eth->mac[mtk_xgmii2mac_id(eth, mpcs->id)];
1474 + regmap_read(mpcs->regmap, RG_PCS_AN_CTRL0, &val);
1475 + if (FIELD_GET(USXGMII_AN_ENABLE, val)) {
1476 + /* Refresh LPA by inverting LPA_LATCH */
1477 + regmap_read(mpcs->regmap, RG_PCS_AN_STS0, &val);
1478 + regmap_update_bits(mpcs->regmap, RG_PCS_AN_STS0,
1479 + USXGMII_LPA_LATCH,
1480 + !(val & USXGMII_LPA_LATCH));
1482 + regmap_read(mpcs->regmap, RG_PCS_AN_STS0, &val);
1484 + phylink_decode_usxgmii_word(state, FIELD_GET(USXGMII_PCS_AN_WORD,
1487 + state->interface = mpcs->interface;
1489 + val = mtk_r32(mac->hw, MTK_XGMAC_STS(mac->id));
1491 + if (mac->id == MTK_GMAC2_ID)
1494 + switch (FIELD_GET(MTK_USXGMII_PCS_MODE, val)) {
1496 + state->speed = SPEED_10000;
1499 + state->speed = SPEED_5000;
1502 + state->speed = SPEED_2500;
1505 + state->speed = SPEED_1000;
1509 + state->interface = mpcs->interface;
1510 + state->link = FIELD_GET(MTK_USXGMII_PCS_LINK, val);
1511 + state->duplex = DUPLEX_FULL;
1514 + /* Continuously repeat re-configuration sequence until link comes up */
1515 + if (state->link == 0)
1516 + mtk_usxgmii_pcs_config(pcs, mpcs->mode,
1517 + state->interface, NULL, false);
1520 +static void mtk_usxgmii_pcs_restart_an(struct phylink_pcs *pcs)
1522 + struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
1523 + unsigned int val = 0;
1525 + if (!mpcs->regmap)
1528 + regmap_read(mpcs->regmap, RG_PCS_AN_CTRL0, &val);
1529 + val |= USXGMII_AN_RESTART;
1530 + regmap_write(mpcs->regmap, RG_PCS_AN_CTRL0, val);
1533 +static void mtk_usxgmii_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
1534 + phy_interface_t interface,
1535 + int speed, int duplex)
1537 + /* Reconfiguring USXGMII to ensure the quality of the RX signal
1538 + * after the line side link up.
1540 + mtk_usxgmii_pcs_config(pcs, mode,
1541 + interface, NULL, false);
1544 +static const struct phylink_pcs_ops mtk_usxgmii_pcs_ops = {
1545 + .pcs_config = mtk_usxgmii_pcs_config,
1546 + .pcs_get_state = mtk_usxgmii_pcs_get_state,
1547 + .pcs_an_restart = mtk_usxgmii_pcs_restart_an,
1548 + .pcs_link_up = mtk_usxgmii_pcs_link_up,
1551 +int mtk_usxgmii_init(struct mtk_eth *eth)
1553 + struct device_node *r = eth->dev->of_node;
1554 + struct device *dev = eth->dev;
1555 + struct device_node *np;
1558 + for (i = 0; i < MTK_MAX_DEVS; i++) {
1559 + np = of_parse_phandle(r, "mediatek,usxgmiisys", i);
1563 + eth->usxgmii_pcs[i] = devm_kzalloc(dev, sizeof(*eth->usxgmii_pcs[i]), GFP_KERNEL);
1564 + if (!eth->usxgmii_pcs[i])
1567 + eth->usxgmii_pcs[i]->id = i;
1568 + eth->usxgmii_pcs[i]->eth = eth;
1569 + eth->usxgmii_pcs[i]->regmap = syscon_node_to_regmap(np);
1570 + if (IS_ERR(eth->usxgmii_pcs[i]->regmap))
1571 + return PTR_ERR(eth->usxgmii_pcs[i]->regmap);
1573 + eth->usxgmii_pcs[i]->pcs.ops = &mtk_usxgmii_pcs_ops;
1574 + eth->usxgmii_pcs[i]->pcs.poll = true;
1575 + eth->usxgmii_pcs[i]->interface = PHY_INTERFACE_MODE_NA;
1576 + eth->usxgmii_pcs[i]->mode = -1;
1581 + ret = mtk_xfi_pextp_init(eth);
1585 + ret = mtk_xfi_pll_init(eth);
1589 + ret = mtk_toprgu_init(eth);
1593 + return mtk_sgmii_wrapper_init(eth);
1596 +struct phylink_pcs *mtk_usxgmii_select_pcs(struct mtk_eth *eth, int mac_id)
1598 + u32 xgmii_id = mtk_mac2xgmii_id(eth, mac_id);
1600 + if (!eth->usxgmii_pcs[xgmii_id]->regmap)
1603 + return ð->usxgmii_pcs[xgmii_id]->pcs;