1 From 7d88d79c0f65b27a92754d7547f7af098b3de67b Mon Sep 17 00:00:00 2001
2 From: Daniel Golle <daniel@makrotopia.org>
3 Date: Tue, 12 Dec 2023 03:47:31 +0000
4 Subject: [PATCH 4/5] dt-bindings: net: pcs: add bindings for MediaTek USXGMII
7 MediaTek's USXGMII can be found in the MT7988 SoC. We need to access
8 it in order to configure and monitor the Ethernet SerDes link in
9 USXGMII, 10GBase-R and 5GBase-R mode. By including a wrapped
10 legacy 1000Base-X/2500Base-X/Cisco SGMII LynxI PCS as well, those
11 interface modes are also available.
13 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
15 .../bindings/net/pcs/mediatek,usxgmii.yaml | 60 +++++++++++++++++++
16 1 file changed, 60 insertions(+)
17 create mode 100644 Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml
20 +++ b/Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml
22 +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
25 +$id: http://devicetree.org/schemas/net/pcs/mediatek,usxgmii.yaml#
26 +$schema: http://devicetree.org/meta-schemas/core.yaml#
28 +title: MediaTek USXGMII PCS
31 + - Daniel Golle <daniel@makrotopia.org>
34 + The MediaTek USXGMII PCS provides physical link control and status
35 + for USXGMII, 10GBase-R and 5GBase-R links on the SerDes interfaces
36 + provided by the PEXTP PHY.
37 + In order to also support legacy 2500Base-X, 1000Base-X and Cisco
38 + SGMII an existing mediatek,*-sgmiisys LynxI PCS is wrapped to
39 + provide those interfaces modes on the same SerDes interfaces shared
40 + with the USXGMII PCS.
44 + pattern: "^pcs@[0-9a-f]+$"
47 + const: mediatek,mt7988-usxgmiisys
54 + - description: USXGMII top-level clock
58 + - description: XFI reset
66 +additionalProperties: false
70 + #include <dt-bindings/clock/mediatek,mt7988-clk.h>
71 + #define MT7988_TOPRGU_XFI0_GRST 12
73 + #address-cells = <2>;
75 + usxgmiisys0: pcs@10080000 {
76 + compatible = "mediatek,mt7988-usxgmiisys";
77 + reg = <0 0x10080000 0 0x1000>;
78 + clocks = <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>;
79 + resets = <&watchdog MT7988_TOPRGU_XFI0_GRST>;