2 * Platform driver for the Realtek RTL8366S ethernet switch
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/skbuff.h>
18 #include <linux/switch.h>
19 #include <linux/rtl8366s.h>
21 #include "rtl8366_smi.h"
23 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
24 #include <linux/debugfs.h>
27 #define RTL8366S_DRIVER_DESC "Realtek RTL8366S ethernet switch driver"
28 #define RTL8366S_DRIVER_VER "0.2.2"
30 #define RTL8366S_PHY_NO_MAX 4
31 #define RTL8366S_PHY_PAGE_MAX 7
32 #define RTL8366S_PHY_ADDR_MAX 31
34 #define RTL8366_CHIP_GLOBAL_CTRL_REG 0x0000
35 #define RTL8366_CHIP_CTRL_VLAN (1 << 13)
37 /* Switch Global Configuration register */
38 #define RTL8366_SGCR 0x0000
39 #define RTL8366_SGCR_EN_BC_STORM_CTRL BIT(0)
40 #define RTL8366_SGCR_MAX_LENGTH(_x) (_x << 4)
41 #define RTL8366_SGCR_MAX_LENGTH_MASK RTL8366_SGCR_MAX_LENGTH(0x3)
42 #define RTL8366_SGCR_MAX_LENGTH_1522 RTL8366_SGCR_MAX_LENGTH(0x0)
43 #define RTL8366_SGCR_MAX_LENGTH_1536 RTL8366_SGCR_MAX_LENGTH(0x1)
44 #define RTL8366_SGCR_MAX_LENGTH_1552 RTL8366_SGCR_MAX_LENGTH(0x2)
45 #define RTL8366_SGCR_MAX_LENGTH_16000 RTL8366_SGCR_MAX_LENGTH(0x3)
47 /* Port Enable Control register */
48 #define RTL8366_PECR 0x0001
50 /* Switch Security Control registers */
51 #define RTL8366_SSCR0 0x0002
52 #define RTL8366_SSCR1 0x0003
53 #define RTL8366_SSCR2 0x0004
54 #define RTL8366_SSCR2_DROP_UNKNOWN_DA BIT(0)
56 #define RTL8366_RESET_CTRL_REG 0x0100
57 #define RTL8366_CHIP_CTRL_RESET_HW 1
58 #define RTL8366_CHIP_CTRL_RESET_SW (1 << 1)
60 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104
61 #define RTL8366S_CHIP_VERSION_MASK 0xf
62 #define RTL8366S_CHIP_ID_REG 0x0105
63 #define RTL8366S_CHIP_ID_8366 0x8366
65 /* PHY registers control */
66 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028
67 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8029
69 #define RTL8366S_PHY_CTRL_READ 1
70 #define RTL8366S_PHY_CTRL_WRITE 0
72 #define RTL8366S_PHY_REG_MASK 0x1f
73 #define RTL8366S_PHY_PAGE_OFFSET 5
74 #define RTL8366S_PHY_PAGE_MASK (0x7 << 5)
75 #define RTL8366S_PHY_NO_OFFSET 9
76 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
78 /* LED control registers */
79 #define RTL8366_LED_BLINKRATE_REG 0x0420
80 #define RTL8366_LED_BLINKRATE_BIT 0
81 #define RTL8366_LED_BLINKRATE_MASK 0x0007
83 #define RTL8366_LED_CTRL_REG 0x0421
84 #define RTL8366_LED_0_1_CTRL_REG 0x0422
85 #define RTL8366_LED_2_3_CTRL_REG 0x0423
87 #define RTL8366S_MIB_COUNT 33
88 #define RTL8366S_GLOBAL_MIB_COUNT 1
89 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040
90 #define RTL8366S_MIB_COUNTER_BASE 0x1000
91 #define RTL8366S_MIB_COUNTER_PORT_OFFSET2 0x0008
92 #define RTL8366S_MIB_COUNTER_BASE2 0x1180
93 #define RTL8366S_MIB_CTRL_REG 0x11F0
94 #define RTL8366S_MIB_CTRL_USER_MASK 0x01FF
95 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
96 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0002
98 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
99 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
100 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
103 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058
104 #define RTL8366S_PORT_VLAN_CTRL_REG(_p) \
105 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
106 #define RTL8366S_PORT_VLAN_CTRL_MASK 0xf
107 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
110 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018B
111 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
113 #define RTL8366S_VLAN_TB_CTRL_REG 0x010F
115 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
116 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
117 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
119 #define RTL8366S_VLAN_MEMCONF_BASE 0x0016
122 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0060
123 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
124 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
125 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
126 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
127 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
128 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
131 #define RTL8366_PORT_NUM_CPU 5
132 #define RTL8366_NUM_PORTS 6
133 #define RTL8366_NUM_VLANS 16
134 #define RTL8366_NUM_LEDGROUPS 4
135 #define RTL8366_NUM_VIDS 4096
136 #define RTL8366S_PRIORITYMAX 7
137 #define RTL8366S_FIDMAX 7
140 #define RTL8366_PORT_1 (1 << 0) /* In userspace port 0 */
141 #define RTL8366_PORT_2 (1 << 1) /* In userspace port 1 */
142 #define RTL8366_PORT_3 (1 << 2) /* In userspace port 2 */
143 #define RTL8366_PORT_4 (1 << 3) /* In userspace port 3 */
145 #define RTL8366_PORT_UNKNOWN (1 << 4) /* No known connection */
146 #define RTL8366_PORT_CPU (1 << 5) /* CPU port */
148 #define RTL8366_PORT_ALL (RTL8366_PORT_1 | \
152 RTL8366_PORT_UNKNOWN | \
155 #define RTL8366_PORT_ALL_BUT_CPU (RTL8366_PORT_1 | \
159 RTL8366_PORT_UNKNOWN)
161 #define RTL8366_PORT_ALL_EXTERNAL (RTL8366_PORT_1 | \
166 #define RTL8366_PORT_ALL_INTERNAL (RTL8366_PORT_UNKNOWN | \
170 struct device
*parent
;
171 struct rtl8366_smi smi
;
172 struct switch_dev dev
;
174 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
175 struct dentry
*debugfs_root
;
179 struct rtl8366s_vlan_mc
{
190 struct rtl8366s_vlan_4k
{
200 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
211 static struct mib_counter rtl8366s_mib_counters
[RTL8366S_MIB_COUNT
] = {
212 { 0, 0, 4, "IfInOctets" },
213 { 0, 4, 4, "EtherStatsOctets" },
214 { 0, 8, 2, "EtherStatsUnderSizePkts" },
215 { 0, 10, 2, "EtherFragments" },
216 { 0, 12, 2, "EtherStatsPkts64Octets" },
217 { 0, 14, 2, "EtherStatsPkts65to127Octets" },
218 { 0, 16, 2, "EtherStatsPkts128to255Octets" },
219 { 0, 18, 2, "EtherStatsPkts256to511Octets" },
220 { 0, 20, 2, "EtherStatsPkts512to1023Octets" },
221 { 0, 22, 2, "EtherStatsPkts1024to1518Octets" },
222 { 0, 24, 2, "EtherOversizeStats" },
223 { 0, 26, 2, "EtherStatsJabbers" },
224 { 0, 28, 2, "IfInUcastPkts" },
225 { 0, 30, 2, "EtherStatsMulticastPkts" },
226 { 0, 32, 2, "EtherStatsBroadcastPkts" },
227 { 0, 34, 2, "EtherStatsDropEvents" },
228 { 0, 36, 2, "Dot3StatsFCSErrors" },
229 { 0, 38, 2, "Dot3StatsSymbolErrors" },
230 { 0, 40, 2, "Dot3InPauseFrames" },
231 { 0, 42, 2, "Dot3ControlInUnknownOpcodes" },
232 { 0, 44, 4, "IfOutOctets" },
233 { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
234 { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
235 { 0, 52, 2, "Dot3sDeferredTransmissions" },
236 { 0, 54, 2, "Dot3StatsLateCollisions" },
237 { 0, 56, 2, "EtherStatsCollisions" },
238 { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
239 { 0, 60, 2, "Dot3OutPauseFrames" },
240 { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
243 * The following counters are accessible at a different
246 { 1, 0, 2, "Dot1dTpPortInDiscards" },
247 { 1, 2, 2, "IfOutUcastPkts" },
248 { 1, 4, 2, "IfOutMulticastPkts" },
249 { 1, 6, 2, "IfOutBroadcastPkts" },
252 #define REG_WR(_smi, _reg, _val) \
254 err = rtl8366_smi_write_reg(_smi, _reg, _val); \
259 #define REG_RMW(_smi, _reg, _mask, _val) \
261 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
266 static inline struct rtl8366s
*smi_to_rtl8366s(struct rtl8366_smi
*smi
)
268 return container_of(smi
, struct rtl8366s
, smi
);
271 static inline struct rtl8366s
*sw_to_rtl8366s(struct switch_dev
*sw
)
273 return container_of(sw
, struct rtl8366s
, dev
);
276 static inline struct rtl8366_smi
*sw_to_rtl8366_smi(struct switch_dev
*sw
)
278 struct rtl8366s
*rtl
= sw_to_rtl8366s(sw
);
282 static int rtl8366s_reset_chip(struct rtl8366_smi
*smi
)
287 rtl8366_smi_write_reg(smi
, RTL8366_RESET_CTRL_REG
,
288 RTL8366_CHIP_CTRL_RESET_HW
);
291 if (rtl8366_smi_read_reg(smi
, RTL8366_RESET_CTRL_REG
, &data
))
294 if (!(data
& RTL8366_CHIP_CTRL_RESET_HW
))
299 printk("Timeout waiting for the switch to reset\n");
306 static int rtl8366s_hw_init(struct rtl8366_smi
*smi
)
310 /* set maximum packet length to 1536 bytes */
311 REG_RMW(smi
, RTL8366_SGCR
, RTL8366_SGCR_MAX_LENGTH_MASK
,
312 RTL8366_SGCR_MAX_LENGTH_1536
);
314 /* enable all ports */
315 REG_WR(smi
, RTL8366_PECR
, 0);
317 /* disable learning for all ports */
318 REG_WR(smi
, RTL8366_SSCR0
, RTL8366_PORT_ALL
);
320 /* disable auto ageing for all ports */
321 REG_WR(smi
, RTL8366_SSCR1
, RTL8366_PORT_ALL
);
323 /* don't drop packets whose DA has not been learned */
324 REG_RMW(smi
, RTL8366_SSCR2
, RTL8366_SSCR2_DROP_UNKNOWN_DA
, 0);
329 static int rtl8366s_read_phy_reg(struct rtl8366_smi
*smi
,
330 u32 phy_no
, u32 page
, u32 addr
, u32
*data
)
335 if (phy_no
> RTL8366S_PHY_NO_MAX
)
338 if (page
> RTL8366S_PHY_PAGE_MAX
)
341 if (addr
> RTL8366S_PHY_ADDR_MAX
)
344 ret
= rtl8366_smi_write_reg(smi
, RTL8366S_PHY_ACCESS_CTRL_REG
,
345 RTL8366S_PHY_CTRL_READ
);
349 reg
= 0x8000 | (1 << (phy_no
+ RTL8366S_PHY_NO_OFFSET
)) |
350 ((page
<< RTL8366S_PHY_PAGE_OFFSET
) & RTL8366S_PHY_PAGE_MASK
) |
351 (addr
& RTL8366S_PHY_REG_MASK
);
353 ret
= rtl8366_smi_write_reg(smi
, reg
, 0);
357 ret
= rtl8366_smi_read_reg(smi
, RTL8366S_PHY_ACCESS_DATA_REG
, data
);
364 static int rtl8366s_write_phy_reg(struct rtl8366_smi
*smi
,
365 u32 phy_no
, u32 page
, u32 addr
, u32 data
)
370 if (phy_no
> RTL8366S_PHY_NO_MAX
)
373 if (page
> RTL8366S_PHY_PAGE_MAX
)
376 if (addr
> RTL8366S_PHY_ADDR_MAX
)
379 ret
= rtl8366_smi_write_reg(smi
, RTL8366S_PHY_ACCESS_CTRL_REG
,
380 RTL8366S_PHY_CTRL_WRITE
);
384 reg
= 0x8000 | (1 << (phy_no
+ RTL8366S_PHY_NO_OFFSET
)) |
385 ((page
<< RTL8366S_PHY_PAGE_OFFSET
) & RTL8366S_PHY_PAGE_MASK
) |
386 (addr
& RTL8366S_PHY_REG_MASK
);
388 ret
= rtl8366_smi_write_reg(smi
, reg
, data
);
395 static int rtl8366_get_mib_counter(struct rtl8366_smi
*smi
, int counter
,
396 int port
, unsigned long long *val
)
403 if (port
> RTL8366_NUM_PORTS
|| counter
>= RTL8366S_MIB_COUNT
)
406 switch (rtl8366s_mib_counters
[counter
].base
) {
408 addr
= RTL8366S_MIB_COUNTER_BASE
+
409 RTL8366S_MIB_COUNTER_PORT_OFFSET
* port
;
413 addr
= RTL8366S_MIB_COUNTER_BASE2
+
414 RTL8366S_MIB_COUNTER_PORT_OFFSET2
* port
;
421 addr
+= rtl8366s_mib_counters
[counter
].offset
;
424 * Writing access counter address first
425 * then ASIC will prepare 64bits counter wait for being retrived
427 data
= 0; /* writing data will be discard by ASIC */
428 err
= rtl8366_smi_write_reg(smi
, addr
, data
);
432 /* read MIB control register */
433 err
= rtl8366_smi_read_reg(smi
, RTL8366S_MIB_CTRL_REG
, &data
);
437 if (data
& RTL8366S_MIB_CTRL_BUSY_MASK
)
440 if (data
& RTL8366S_MIB_CTRL_RESET_MASK
)
444 for (i
= rtl8366s_mib_counters
[counter
].length
; i
> 0; i
--) {
445 err
= rtl8366_smi_read_reg(smi
, addr
+ (i
- 1), &data
);
449 mibvalue
= (mibvalue
<< 16) | (data
& 0xFFFF);
456 static int rtl8366s_get_vlan_4k(struct rtl8366_smi
*smi
, u32 vid
,
457 struct rtl8366_vlan_4k
*vlan4k
)
459 struct rtl8366s_vlan_4k vlan4k_priv
;
464 memset(vlan4k
, '\0', sizeof(struct rtl8366_vlan_4k
));
465 vlan4k_priv
.vid
= vid
;
467 if (vid
>= RTL8366_NUM_VIDS
)
470 tableaddr
= (u16
*)&vlan4k_priv
;
474 err
= rtl8366_smi_write_reg(smi
, RTL8366S_VLAN_TABLE_WRITE_BASE
, data
);
478 /* write table access control word */
479 err
= rtl8366_smi_write_reg(smi
, RTL8366S_TABLE_ACCESS_CTRL_REG
,
480 RTL8366S_TABLE_VLAN_READ_CTRL
);
484 err
= rtl8366_smi_read_reg(smi
, RTL8366S_VLAN_TABLE_READ_BASE
, &data
);
491 err
= rtl8366_smi_read_reg(smi
, RTL8366S_VLAN_TABLE_READ_BASE
+ 1,
499 vlan4k
->untag
= vlan4k_priv
.untag
;
500 vlan4k
->member
= vlan4k_priv
.member
;
501 vlan4k
->fid
= vlan4k_priv
.fid
;
506 static int rtl8366s_set_vlan_4k(struct rtl8366_smi
*smi
,
507 const struct rtl8366_vlan_4k
*vlan4k
)
509 struct rtl8366s_vlan_4k vlan4k_priv
;
514 if (vlan4k
->vid
>= RTL8366_NUM_VIDS
||
515 vlan4k
->member
> RTL8366_PORT_ALL
||
516 vlan4k
->untag
> RTL8366_PORT_ALL
||
517 vlan4k
->fid
> RTL8366S_FIDMAX
)
520 vlan4k_priv
.vid
= vlan4k
->vid
;
521 vlan4k_priv
.untag
= vlan4k
->untag
;
522 vlan4k_priv
.member
= vlan4k
->member
;
523 vlan4k_priv
.fid
= vlan4k
->fid
;
525 tableaddr
= (u16
*)&vlan4k_priv
;
529 err
= rtl8366_smi_write_reg(smi
, RTL8366S_VLAN_TABLE_WRITE_BASE
, data
);
537 err
= rtl8366_smi_write_reg(smi
, RTL8366S_VLAN_TABLE_WRITE_BASE
+ 1,
542 /* write table access control word */
543 err
= rtl8366_smi_write_reg(smi
, RTL8366S_TABLE_ACCESS_CTRL_REG
,
544 RTL8366S_TABLE_VLAN_WRITE_CTRL
);
549 static int rtl8366s_get_vlan_mc(struct rtl8366_smi
*smi
, u32 index
,
550 struct rtl8366_vlan_mc
*vlanmc
)
552 struct rtl8366s_vlan_mc vlanmc_priv
;
558 memset(vlanmc
, '\0', sizeof(struct rtl8366_vlan_mc
));
560 if (index
>= RTL8366_NUM_VLANS
)
563 tableaddr
= (u16
*)&vlanmc_priv
;
565 addr
= RTL8366S_VLAN_MEMCONF_BASE
+ (index
<< 1);
566 err
= rtl8366_smi_read_reg(smi
, addr
, &data
);
573 addr
= RTL8366S_VLAN_MEMCONF_BASE
+ 1 + (index
<< 1);
574 err
= rtl8366_smi_read_reg(smi
, addr
, &data
);
580 vlanmc
->vid
= vlanmc_priv
.vid
;
581 vlanmc
->priority
= vlanmc_priv
.priority
;
582 vlanmc
->untag
= vlanmc_priv
.untag
;
583 vlanmc
->member
= vlanmc_priv
.member
;
584 vlanmc
->fid
= vlanmc_priv
.fid
;
589 static int rtl8366s_set_vlan_mc(struct rtl8366_smi
*smi
, u32 index
,
590 const struct rtl8366_vlan_mc
*vlanmc
)
592 struct rtl8366s_vlan_mc vlanmc_priv
;
598 if (index
>= RTL8366_NUM_VLANS
||
599 vlanmc
->vid
>= RTL8366_NUM_VIDS
||
600 vlanmc
->priority
> RTL8366S_PRIORITYMAX
||
601 vlanmc
->member
> RTL8366_PORT_ALL
||
602 vlanmc
->untag
> RTL8366_PORT_ALL
||
603 vlanmc
->fid
> RTL8366S_FIDMAX
)
606 vlanmc_priv
.vid
= vlanmc
->vid
;
607 vlanmc_priv
.priority
= vlanmc
->priority
;
608 vlanmc_priv
.untag
= vlanmc
->untag
;
609 vlanmc_priv
.member
= vlanmc
->member
;
610 vlanmc_priv
.fid
= vlanmc
->fid
;
612 addr
= RTL8366S_VLAN_MEMCONF_BASE
+ (index
<< 1);
614 tableaddr
= (u16
*)&vlanmc_priv
;
617 err
= rtl8366_smi_write_reg(smi
, addr
, data
);
621 addr
= RTL8366S_VLAN_MEMCONF_BASE
+ 1 + (index
<< 1);
626 err
= rtl8366_smi_write_reg(smi
, addr
, data
);
633 static int rtl8366s_get_port_vlan_index(struct rtl8366_smi
*smi
, int port
,
639 if (port
>= RTL8366_NUM_PORTS
)
642 err
= rtl8366_smi_read_reg(smi
, RTL8366S_PORT_VLAN_CTRL_REG(port
),
647 *val
= (data
>> RTL8366S_PORT_VLAN_CTRL_SHIFT(port
)) &
648 RTL8366S_PORT_VLAN_CTRL_MASK
;
654 static int rtl8366s_get_vlan_port_pvid(struct rtl8366_smi
*smi
, int port
,
657 struct rtl8366_vlan_mc vlanmc
;
661 err
= rtl8366s_get_port_vlan_index(smi
, port
, &index
);
665 err
= rtl8366s_get_vlan_mc(smi
, index
, &vlanmc
);
673 static int rtl8366s_set_port_vlan_index(struct rtl8366_smi
*smi
, int port
,
676 if (port
>= RTL8366_NUM_PORTS
|| index
>= RTL8366_NUM_VLANS
)
679 return rtl8366_smi_rmwr(smi
, RTL8366S_PORT_VLAN_CTRL_REG(port
),
680 RTL8366S_PORT_VLAN_CTRL_MASK
<<
681 RTL8366S_PORT_VLAN_CTRL_SHIFT(port
),
682 (index
& RTL8366S_PORT_VLAN_CTRL_MASK
) <<
683 RTL8366S_PORT_VLAN_CTRL_SHIFT(port
));
686 static int rtl8366s_set_vlan_port_pvid(struct rtl8366_smi
*smi
, int port
, int val
)
689 struct rtl8366_vlan_mc vlanmc
;
690 struct rtl8366_vlan_4k vlan4k
;
692 if (port
>= RTL8366_NUM_PORTS
|| val
>= RTL8366_NUM_VIDS
)
695 /* Updating the 4K entry; lookup it and change the port member set */
696 rtl8366s_get_vlan_4k(smi
, val
, &vlan4k
);
697 vlan4k
.member
|= ((1 << port
) | RTL8366_PORT_CPU
);
698 vlan4k
.untag
= RTL8366_PORT_ALL_BUT_CPU
;
699 rtl8366s_set_vlan_4k(smi
, &vlan4k
);
702 * For the 16 entries more work needs to be done. First see if such
703 * VID is already there and change it
705 for (i
= 0; i
< RTL8366_NUM_VLANS
; ++i
) {
706 rtl8366s_get_vlan_mc(smi
, i
, &vlanmc
);
708 /* Try to find an existing vid and update port member set */
709 if (val
== vlanmc
.vid
) {
710 vlanmc
.member
|= ((1 << port
) | RTL8366_PORT_CPU
);
711 rtl8366s_set_vlan_mc(smi
, i
, &vlanmc
);
713 /* Now update PVID register settings */
714 rtl8366s_set_port_vlan_index(smi
, port
, i
);
721 * PVID could not be found from vlan table. Replace unused (one that
722 * has no member ports) with new one
724 for (i
= 0; i
< RTL8366_NUM_VLANS
; ++i
) {
725 rtl8366s_get_vlan_mc(smi
, i
, &vlanmc
);
728 * See if this vlan member configuration is unused. It is
729 * unused if member set contains no ports or CPU port only
731 if (!vlanmc
.member
|| vlanmc
.member
== RTL8366_PORT_CPU
) {
734 vlanmc
.untag
= RTL8366_PORT_ALL_BUT_CPU
;
735 vlanmc
.member
= ((1 << port
) | RTL8366_PORT_CPU
);
738 rtl8366s_set_vlan_mc(smi
, i
, &vlanmc
);
740 /* Now update PVID register settings */
741 rtl8366s_set_port_vlan_index(smi
, port
, i
);
748 "All 16 vlan member configurations are in use\n");
754 static int rtl8366s_vlan_set_vlan(struct rtl8366_smi
*smi
, int enable
)
756 return rtl8366_smi_rmwr(smi
, RTL8366_CHIP_GLOBAL_CTRL_REG
,
757 RTL8366_CHIP_CTRL_VLAN
,
758 (enable
) ? RTL8366_CHIP_CTRL_VLAN
: 0);
761 static int rtl8366s_vlan_set_4ktable(struct rtl8366_smi
*smi
, int enable
)
763 return rtl8366_smi_rmwr(smi
, RTL8366S_VLAN_TB_CTRL_REG
,
764 1, (enable
) ? 1 : 0);
767 static int rtl8366s_reset_vlan(struct rtl8366_smi
*smi
)
769 struct rtl8366_vlan_4k vlan4k
;
770 struct rtl8366_vlan_mc vlanmc
;
774 /* clear 16 VLAN member configuration */
780 for (i
= 0; i
< RTL8366_NUM_VLANS
; i
++) {
781 err
= rtl8366s_set_vlan_mc(smi
, i
, &vlanmc
);
786 /* Set a default VLAN with vid 1 to 4K table for all ports */
788 vlan4k
.member
= RTL8366_PORT_ALL
;
789 vlan4k
.untag
= RTL8366_PORT_ALL
;
791 err
= rtl8366s_set_vlan_4k(smi
, &vlan4k
);
795 /* Set all ports PVID to default VLAN */
796 for (i
= 0; i
< RTL8366_NUM_PORTS
; i
++) {
797 err
= rtl8366s_set_vlan_port_pvid(smi
, i
, 0);
805 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
806 static int rtl8366s_debugfs_open(struct inode
*inode
, struct file
*file
)
808 file
->private_data
= inode
->i_private
;
812 static ssize_t
rtl8366s_read_debugfs_mibs(struct file
*file
,
813 char __user
*user_buf
,
814 size_t count
, loff_t
*ppos
)
816 struct rtl8366s
*rtl
= (struct rtl8366s
*)file
->private_data
;
817 struct rtl8366_smi
*smi
= &rtl
->smi
;
819 char *buf
= rtl
->buf
;
821 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
822 "%-36s %12s %12s %12s %12s %12s %12s\n",
824 "Port 0", "Port 1", "Port 2",
825 "Port 3", "Port 4", "Port 5");
827 for (i
= 0; i
< ARRAY_SIZE(rtl8366s_mib_counters
); ++i
) {
828 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
, "%-36s ",
829 rtl8366s_mib_counters
[i
].name
);
830 for (j
= 0; j
< RTL8366_NUM_PORTS
; ++j
) {
831 unsigned long long counter
= 0;
833 if (!rtl8366_get_mib_counter(smi
, i
, j
, &counter
))
834 len
+= snprintf(buf
+ len
,
835 sizeof(rtl
->buf
) - len
,
838 len
+= snprintf(buf
+ len
,
839 sizeof(rtl
->buf
) - len
,
842 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
, "\n");
845 return simple_read_from_buffer(user_buf
, count
, ppos
, buf
, len
);
848 static ssize_t
rtl8366s_read_debugfs_vlan(struct file
*file
,
849 char __user
*user_buf
,
850 size_t count
, loff_t
*ppos
)
852 struct rtl8366s
*rtl
= (struct rtl8366s
*)file
->private_data
;
853 struct rtl8366_smi
*smi
= &rtl
->smi
;
855 char *buf
= rtl
->buf
;
857 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
858 "VLAN Member Config:\n");
859 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
860 "\t id \t vid \t prio \t member \t untag \t fid "
863 for (i
= 0; i
< RTL8366_NUM_VLANS
; ++i
) {
864 struct rtl8366_vlan_mc vlanmc
;
866 rtl8366s_get_vlan_mc(smi
, i
, &vlanmc
);
868 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
869 "\t[%d] \t %d \t %d \t 0x%04x \t 0x%04x \t %d "
870 "\t", i
, vlanmc
.vid
, vlanmc
.priority
,
871 vlanmc
.member
, vlanmc
.untag
, vlanmc
.fid
);
873 for (j
= 0; j
< RTL8366_NUM_PORTS
; ++j
) {
875 if (!rtl8366s_get_port_vlan_index(smi
, j
, &index
)) {
877 len
+= snprintf(buf
+ len
,
878 sizeof(rtl
->buf
) - len
,
882 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
, "\n");
885 return simple_read_from_buffer(user_buf
, count
, ppos
, buf
, len
);
888 static ssize_t
rtl8366s_read_debugfs_reg(struct file
*file
,
889 char __user
*user_buf
,
890 size_t count
, loff_t
*ppos
)
892 struct rtl8366s
*rtl
= (struct rtl8366s
*)file
->private_data
;
893 struct rtl8366_smi
*smi
= &rtl
->smi
;
894 u32 t
, reg
= g_dbg_reg
;
896 char *buf
= rtl
->buf
;
898 memset(buf
, '\0', sizeof(rtl
->buf
));
900 err
= rtl8366_smi_read_reg(smi
, reg
, &t
);
902 len
+= snprintf(buf
, sizeof(rtl
->buf
),
903 "Read failed (reg: 0x%04x)\n", reg
);
904 return simple_read_from_buffer(user_buf
, count
, ppos
, buf
, len
);
907 len
+= snprintf(buf
, sizeof(rtl
->buf
), "reg = 0x%04x, val = 0x%04x\n",
910 return simple_read_from_buffer(user_buf
, count
, ppos
, buf
, len
);
913 static ssize_t
rtl8366s_write_debugfs_reg(struct file
*file
,
914 const char __user
*user_buf
,
915 size_t count
, loff_t
*ppos
)
917 struct rtl8366s
*rtl
= (struct rtl8366s
*)file
->private_data
;
918 struct rtl8366_smi
*smi
= &rtl
->smi
;
923 char *buf
= rtl
->buf
;
925 len
= min(count
, sizeof(rtl
->buf
) - 1);
926 if (copy_from_user(buf
, user_buf
, len
)) {
927 dev_err(rtl
->parent
, "copy from user failed\n");
932 if (len
> 0 && buf
[len
- 1] == '\n')
936 if (strict_strtoul(buf
, 16, &data
)) {
937 dev_err(rtl
->parent
, "Invalid reg value %s\n", buf
);
939 err
= rtl8366_smi_write_reg(smi
, reg
, data
);
942 "writing reg 0x%04x val 0x%04lx failed\n",
950 static const struct file_operations fops_rtl8366s_regs
= {
951 .read
= rtl8366s_read_debugfs_reg
,
952 .write
= rtl8366s_write_debugfs_reg
,
953 .open
= rtl8366s_debugfs_open
,
957 static const struct file_operations fops_rtl8366s_vlan
= {
958 .read
= rtl8366s_read_debugfs_vlan
,
959 .open
= rtl8366s_debugfs_open
,
963 static const struct file_operations fops_rtl8366s_mibs
= {
964 .read
= rtl8366s_read_debugfs_mibs
,
965 .open
= rtl8366s_debugfs_open
,
969 static void rtl8366s_debugfs_init(struct rtl8366s
*rtl
)
974 if (!rtl
->debugfs_root
)
975 rtl
->debugfs_root
= debugfs_create_dir("rtl8366s", NULL
);
977 if (!rtl
->debugfs_root
) {
978 dev_err(rtl
->parent
, "Unable to create debugfs dir\n");
981 root
= rtl
->debugfs_root
;
983 node
= debugfs_create_x16("reg", S_IRUGO
| S_IWUSR
, root
, &g_dbg_reg
);
985 dev_err(rtl
->parent
, "Creating debugfs file '%s' failed\n",
990 node
= debugfs_create_file("val", S_IRUGO
| S_IWUSR
, root
, rtl
,
991 &fops_rtl8366s_regs
);
993 dev_err(rtl
->parent
, "Creating debugfs file '%s' failed\n",
998 node
= debugfs_create_file("vlan", S_IRUSR
, root
, rtl
,
999 &fops_rtl8366s_vlan
);
1001 dev_err(rtl
->parent
, "Creating debugfs file '%s' failed\n",
1006 node
= debugfs_create_file("mibs", S_IRUSR
, root
, rtl
,
1007 &fops_rtl8366s_mibs
);
1009 dev_err(rtl
->parent
, "Creating debugfs file '%s' failed\n",
1015 static void rtl8366s_debugfs_remove(struct rtl8366s
*rtl
)
1017 if (rtl
->debugfs_root
) {
1018 debugfs_remove_recursive(rtl
->debugfs_root
);
1019 rtl
->debugfs_root
= NULL
;
1024 static inline void rtl8366s_debugfs_init(struct rtl8366s
*rtl
) {}
1025 static inline void rtl8366s_debugfs_remove(struct rtl8366s
*rtl
) {}
1026 #endif /* CONFIG_RTL8366S_PHY_DEBUG_FS */
1028 static int rtl8366s_sw_reset_mibs(struct switch_dev
*dev
,
1029 const struct switch_attr
*attr
,
1030 struct switch_val
*val
)
1032 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
1035 if (val
->value
.i
== 1)
1036 err
= rtl8366_smi_rmwr(smi
, RTL8366S_MIB_CTRL_REG
, 0, (1 << 2));
1041 static int rtl8366s_sw_get_vlan_enable(struct switch_dev
*dev
,
1042 const struct switch_attr
*attr
,
1043 struct switch_val
*val
)
1045 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
1048 if (attr
->ofs
== 1) {
1049 rtl8366_smi_read_reg(smi
, RTL8366_CHIP_GLOBAL_CTRL_REG
, &data
);
1051 if (data
& RTL8366_CHIP_CTRL_VLAN
)
1055 } else if (attr
->ofs
== 2) {
1056 rtl8366_smi_read_reg(smi
, RTL8366S_VLAN_TB_CTRL_REG
, &data
);
1067 static int rtl8366s_sw_get_blinkrate(struct switch_dev
*dev
,
1068 const struct switch_attr
*attr
,
1069 struct switch_val
*val
)
1071 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
1074 rtl8366_smi_read_reg(smi
, RTL8366_LED_BLINKRATE_REG
, &data
);
1076 val
->value
.i
= (data
& (RTL8366_LED_BLINKRATE_MASK
));
1081 static int rtl8366s_sw_set_blinkrate(struct switch_dev
*dev
,
1082 const struct switch_attr
*attr
,
1083 struct switch_val
*val
)
1085 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
1087 if (val
->value
.i
>= 6)
1090 return rtl8366_smi_rmwr(smi
, RTL8366_LED_BLINKRATE_REG
,
1091 RTL8366_LED_BLINKRATE_MASK
,
1095 static int rtl8366s_sw_set_vlan_enable(struct switch_dev
*dev
,
1096 const struct switch_attr
*attr
,
1097 struct switch_val
*val
)
1099 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
1102 return rtl8366s_vlan_set_vlan(smi
, val
->value
.i
);
1104 return rtl8366s_vlan_set_4ktable(smi
, val
->value
.i
);
1107 static const char *rtl8366s_speed_str(unsigned speed
)
1121 static int rtl8366s_sw_get_port_link(struct switch_dev
*dev
,
1122 const struct switch_attr
*attr
,
1123 struct switch_val
*val
)
1125 struct rtl8366s
*rtl
= sw_to_rtl8366s(dev
);
1126 struct rtl8366_smi
*smi
= &rtl
->smi
;
1127 u32 len
= 0, data
= 0;
1129 if (val
->port_vlan
>= RTL8366_NUM_PORTS
)
1132 memset(rtl
->buf
, '\0', sizeof(rtl
->buf
));
1133 rtl8366_smi_read_reg(smi
, RTL8366S_PORT_LINK_STATUS_BASE
+
1134 (val
->port_vlan
/ 2), &data
);
1136 if (val
->port_vlan
% 2)
1139 if (data
& RTL8366S_PORT_STATUS_LINK_MASK
) {
1140 len
= snprintf(rtl
->buf
, sizeof(rtl
->buf
),
1141 "port:%d link:up speed:%s %s-duplex %s%s%s",
1143 rtl8366s_speed_str(data
&
1144 RTL8366S_PORT_STATUS_SPEED_MASK
),
1145 (data
& RTL8366S_PORT_STATUS_DUPLEX_MASK
) ?
1147 (data
& RTL8366S_PORT_STATUS_TXPAUSE_MASK
) ?
1149 (data
& RTL8366S_PORT_STATUS_RXPAUSE_MASK
) ?
1151 (data
& RTL8366S_PORT_STATUS_AN_MASK
) ?
1154 len
= snprintf(rtl
->buf
, sizeof(rtl
->buf
), "port:%d link: down",
1158 val
->value
.s
= rtl
->buf
;
1164 static int rtl8366s_sw_get_vlan_info(struct switch_dev
*dev
,
1165 const struct switch_attr
*attr
,
1166 struct switch_val
*val
)
1170 struct rtl8366_vlan_mc vlanmc
;
1171 struct rtl8366_vlan_4k vlan4k
;
1172 struct rtl8366s
*rtl
= sw_to_rtl8366s(dev
);
1173 struct rtl8366_smi
*smi
= &rtl
->smi
;
1174 char *buf
= rtl
->buf
;
1176 if (val
->port_vlan
== 0 || val
->port_vlan
>= RTL8366_NUM_VLANS
)
1179 memset(buf
, '\0', sizeof(rtl
->buf
));
1181 rtl8366s_get_vlan_mc(smi
, val
->port_vlan
, &vlanmc
);
1182 rtl8366s_get_vlan_4k(smi
, vlanmc
.vid
, &vlan4k
);
1184 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
, "VLAN %d: Ports: ",
1187 for (i
= 0; i
< RTL8366_NUM_PORTS
; ++i
) {
1189 if (!rtl8366s_get_port_vlan_index(smi
, i
, &index
) &&
1190 index
== val
->port_vlan
)
1191 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
1194 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
, "\n");
1196 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
1197 "\t\t vid \t prio \t member \t untag \t fid\n");
1198 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
, "\tMC:\t");
1199 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
1200 "%d \t %d \t 0x%04x \t 0x%04x \t %d\n",
1201 vlanmc
.vid
, vlanmc
.priority
, vlanmc
.member
,
1202 vlanmc
.untag
, vlanmc
.fid
);
1203 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
, "\t4K:\t");
1204 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
1205 "%d \t \t 0x%04x \t 0x%04x \t %d",
1206 vlan4k
.vid
, vlan4k
.member
, vlan4k
.untag
, vlan4k
.fid
);
1214 static int rtl8366s_sw_set_port_led(struct switch_dev
*dev
,
1215 const struct switch_attr
*attr
,
1216 struct switch_val
*val
)
1218 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
1223 if (val
->port_vlan
>= RTL8366_NUM_PORTS
||
1224 (1 << val
->port_vlan
) == RTL8366_PORT_UNKNOWN
)
1227 if (val
->port_vlan
== RTL8366_PORT_NUM_CPU
) {
1228 reg
= RTL8366_LED_BLINKRATE_REG
;
1230 data
= val
->value
.i
<< 4;
1232 reg
= RTL8366_LED_CTRL_REG
;
1233 mask
= 0xF << (val
->port_vlan
* 4),
1234 data
= val
->value
.i
<< (val
->port_vlan
* 4);
1237 return rtl8366_smi_rmwr(smi
, RTL8366_LED_BLINKRATE_REG
, mask
, data
);
1240 static int rtl8366s_sw_get_port_led(struct switch_dev
*dev
,
1241 const struct switch_attr
*attr
,
1242 struct switch_val
*val
)
1244 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
1247 if (val
->port_vlan
>= RTL8366_NUM_LEDGROUPS
)
1250 rtl8366_smi_read_reg(smi
, RTL8366_LED_CTRL_REG
, &data
);
1251 val
->value
.i
= (data
>> (val
->port_vlan
* 4)) & 0x000F;
1256 static int rtl8366s_sw_reset_port_mibs(struct switch_dev
*dev
,
1257 const struct switch_attr
*attr
,
1258 struct switch_val
*val
)
1260 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
1262 if (val
->port_vlan
>= RTL8366_NUM_PORTS
)
1266 return rtl8366_smi_rmwr(smi
, RTL8366S_MIB_CTRL_REG
,
1267 0, (1 << (val
->port_vlan
+ 3)));
1270 static int rtl8366s_sw_get_port_mib(struct switch_dev
*dev
,
1271 const struct switch_attr
*attr
,
1272 struct switch_val
*val
)
1274 struct rtl8366s
*rtl
= sw_to_rtl8366s(dev
);
1275 struct rtl8366_smi
*smi
= &rtl
->smi
;
1277 unsigned long long counter
= 0;
1278 char *buf
= rtl
->buf
;
1280 if (val
->port_vlan
>= RTL8366_NUM_PORTS
)
1283 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
1284 "Port %d MIB counters\n",
1287 for (i
= 0; i
< ARRAY_SIZE(rtl8366s_mib_counters
); ++i
) {
1288 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
1289 "%-36s: ", rtl8366s_mib_counters
[i
].name
);
1290 if (!rtl8366_get_mib_counter(smi
, i
, val
->port_vlan
, &counter
))
1291 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
1294 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
1303 static int rtl8366s_sw_get_vlan_ports(struct switch_dev
*dev
,
1304 struct switch_val
*val
)
1306 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
1307 struct rtl8366_vlan_mc vlanmc
;
1308 struct switch_port
*port
;
1311 if (val
->port_vlan
== 0 || val
->port_vlan
>= RTL8366_NUM_VLANS
)
1314 rtl8366s_get_vlan_mc(smi
, val
->port_vlan
, &vlanmc
);
1316 port
= &val
->value
.ports
[0];
1318 for (i
= 0; i
< RTL8366_NUM_PORTS
; i
++) {
1319 if (!(vlanmc
.member
& BIT(i
)))
1323 port
->flags
= (vlanmc
.untag
& BIT(i
)) ?
1324 0 : BIT(SWITCH_PORT_FLAG_TAGGED
);
1331 static int rtl8366s_sw_set_vlan_ports(struct switch_dev
*dev
,
1332 struct switch_val
*val
)
1334 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
1335 struct rtl8366_vlan_mc vlanmc
;
1336 struct rtl8366_vlan_4k vlan4k
;
1337 struct switch_port
*port
;
1340 if (val
->port_vlan
== 0 || val
->port_vlan
>= RTL8366_NUM_VLANS
)
1343 rtl8366s_get_vlan_mc(smi
, val
->port_vlan
, &vlanmc
);
1344 rtl8366s_get_vlan_4k(smi
, vlanmc
.vid
, &vlan4k
);
1349 port
= &val
->value
.ports
[0];
1350 for (i
= 0; i
< val
->len
; i
++, port
++) {
1351 vlanmc
.member
|= BIT(port
->id
);
1353 if (!(port
->flags
& BIT(SWITCH_PORT_FLAG_TAGGED
)))
1354 vlanmc
.untag
|= BIT(port
->id
);
1357 vlan4k
.member
= vlanmc
.member
;
1358 vlan4k
.untag
= vlanmc
.untag
;
1360 rtl8366s_set_vlan_mc(smi
, val
->port_vlan
, &vlanmc
);
1361 rtl8366s_set_vlan_4k(smi
, &vlan4k
);
1365 static int rtl8366s_sw_get_port_pvid(struct switch_dev
*dev
, int port
, int *val
)
1367 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
1368 return rtl8366s_get_vlan_port_pvid(smi
, port
, val
);
1371 static int rtl8366s_sw_set_port_pvid(struct switch_dev
*dev
, int port
, int val
)
1373 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
1374 return rtl8366s_set_vlan_port_pvid(smi
, port
, val
);
1377 static int rtl8366s_sw_reset_switch(struct switch_dev
*dev
)
1379 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
1382 err
= rtl8366s_reset_chip(smi
);
1386 err
= rtl8366s_hw_init(smi
);
1390 return rtl8366s_reset_vlan(smi
);
1393 static struct switch_attr rtl8366s_globals
[] = {
1395 .type
= SWITCH_TYPE_INT
,
1396 .name
= "enable_vlan",
1397 .description
= "Enable VLAN mode",
1398 .set
= rtl8366s_sw_set_vlan_enable
,
1399 .get
= rtl8366s_sw_get_vlan_enable
,
1403 .type
= SWITCH_TYPE_INT
,
1404 .name
= "enable_vlan4k",
1405 .description
= "Enable VLAN 4K mode",
1406 .set
= rtl8366s_sw_set_vlan_enable
,
1407 .get
= rtl8366s_sw_get_vlan_enable
,
1411 .type
= SWITCH_TYPE_INT
,
1412 .name
= "reset_mibs",
1413 .description
= "Reset all MIB counters",
1414 .set
= rtl8366s_sw_reset_mibs
,
1418 .type
= SWITCH_TYPE_INT
,
1419 .name
= "blinkrate",
1420 .description
= "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1421 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1422 .set
= rtl8366s_sw_set_blinkrate
,
1423 .get
= rtl8366s_sw_get_blinkrate
,
1428 static struct switch_attr rtl8366s_port
[] = {
1430 .type
= SWITCH_TYPE_STRING
,
1432 .description
= "Get port link information",
1435 .get
= rtl8366s_sw_get_port_link
,
1437 .type
= SWITCH_TYPE_INT
,
1438 .name
= "reset_mib",
1439 .description
= "Reset single port MIB counters",
1441 .set
= rtl8366s_sw_reset_port_mibs
,
1444 .type
= SWITCH_TYPE_STRING
,
1446 .description
= "Get MIB counters for port",
1449 .get
= rtl8366s_sw_get_port_mib
,
1451 .type
= SWITCH_TYPE_INT
,
1453 .description
= "Get/Set port group (0 - 3) led mode (0 - 15)",
1455 .set
= rtl8366s_sw_set_port_led
,
1456 .get
= rtl8366s_sw_get_port_led
,
1460 static struct switch_attr rtl8366s_vlan
[] = {
1462 .type
= SWITCH_TYPE_STRING
,
1464 .description
= "Get vlan information",
1467 .get
= rtl8366s_sw_get_vlan_info
,
1472 static struct switch_dev rtl8366_switch_dev
= {
1474 .cpu_port
= RTL8366_PORT_NUM_CPU
,
1475 .ports
= RTL8366_NUM_PORTS
,
1476 .vlans
= RTL8366_NUM_VLANS
,
1478 .attr
= rtl8366s_globals
,
1479 .n_attr
= ARRAY_SIZE(rtl8366s_globals
),
1482 .attr
= rtl8366s_port
,
1483 .n_attr
= ARRAY_SIZE(rtl8366s_port
),
1486 .attr
= rtl8366s_vlan
,
1487 .n_attr
= ARRAY_SIZE(rtl8366s_vlan
),
1490 .get_vlan_ports
= rtl8366s_sw_get_vlan_ports
,
1491 .set_vlan_ports
= rtl8366s_sw_set_vlan_ports
,
1492 .get_port_pvid
= rtl8366s_sw_get_port_pvid
,
1493 .set_port_pvid
= rtl8366s_sw_set_port_pvid
,
1494 .reset_switch
= rtl8366s_sw_reset_switch
,
1497 static int rtl8366s_switch_init(struct rtl8366s
*rtl
)
1499 struct switch_dev
*dev
= &rtl
->dev
;
1502 memcpy(dev
, &rtl8366_switch_dev
, sizeof(struct switch_dev
));
1504 dev
->devname
= dev_name(rtl
->parent
);
1506 err
= register_switch(dev
, NULL
);
1508 dev_err(rtl
->parent
, "switch registration failed\n");
1513 static void rtl8366s_switch_cleanup(struct rtl8366s
*rtl
)
1515 unregister_switch(&rtl
->dev
);
1518 static int rtl8366s_mii_read(struct mii_bus
*bus
, int addr
, int reg
)
1520 struct rtl8366_smi
*smi
= bus
->priv
;
1524 err
= rtl8366s_read_phy_reg(smi
, addr
, 0, reg
, &val
);
1531 static int rtl8366s_mii_write(struct mii_bus
*bus
, int addr
, int reg
, u16 val
)
1533 struct rtl8366_smi
*smi
= bus
->priv
;
1537 err
= rtl8366s_write_phy_reg(smi
, addr
, 0, reg
, val
);
1539 (void) rtl8366s_read_phy_reg(smi
, addr
, 0, reg
, &t
);
1544 static int rtl8366s_mii_bus_match(struct mii_bus
*bus
)
1546 return (bus
->read
== rtl8366s_mii_read
&&
1547 bus
->write
== rtl8366s_mii_write
);
1550 static int rtl8366s_setup(struct rtl8366s
*rtl
)
1552 struct rtl8366_smi
*smi
= &rtl
->smi
;
1555 rtl8366s_debugfs_init(rtl
);
1557 ret
= rtl8366s_reset_chip(smi
);
1561 ret
= rtl8366s_hw_init(smi
);
1565 static int rtl8366s_detect(struct rtl8366_smi
*smi
)
1571 ret
= rtl8366_smi_read_reg(smi
, RTL8366S_CHIP_ID_REG
, &chip_id
);
1573 dev_err(smi
->parent
, "unable to read chip id\n");
1578 case RTL8366S_CHIP_ID_8366
:
1581 dev_err(smi
->parent
, "unknown chip id (%04x)\n", chip_id
);
1585 ret
= rtl8366_smi_read_reg(smi
, RTL8366S_CHIP_VERSION_CTRL_REG
,
1588 dev_err(smi
->parent
, "unable to read chip version\n");
1592 dev_info(smi
->parent
, "RTL%04x ver. %u chip found\n",
1593 chip_id
, chip_ver
& RTL8366S_CHIP_VERSION_MASK
);
1598 static struct rtl8366_smi_ops rtl8366s_smi_ops
= {
1599 .detect
= rtl8366s_detect
,
1600 .mii_read
= rtl8366s_mii_read
,
1601 .mii_write
= rtl8366s_mii_write
,
1604 static int __init
rtl8366s_probe(struct platform_device
*pdev
)
1606 static int rtl8366_smi_version_printed
;
1607 struct rtl8366s_platform_data
*pdata
;
1608 struct rtl8366s
*rtl
;
1609 struct rtl8366_smi
*smi
;
1612 if (!rtl8366_smi_version_printed
++)
1613 printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1614 " version " RTL8366S_DRIVER_VER
"\n");
1616 pdata
= pdev
->dev
.platform_data
;
1618 dev_err(&pdev
->dev
, "no platform data specified\n");
1623 rtl
= kzalloc(sizeof(*rtl
), GFP_KERNEL
);
1625 dev_err(&pdev
->dev
, "no memory for private data\n");
1630 rtl
->parent
= &pdev
->dev
;
1633 smi
->parent
= &pdev
->dev
;
1634 smi
->gpio_sda
= pdata
->gpio_sda
;
1635 smi
->gpio_sck
= pdata
->gpio_sck
;
1636 smi
->ops
= &rtl8366s_smi_ops
;
1638 err
= rtl8366_smi_init(smi
);
1642 platform_set_drvdata(pdev
, rtl
);
1644 err
= rtl8366s_setup(rtl
);
1646 goto err_clear_drvdata
;
1648 err
= rtl8366s_switch_init(rtl
);
1650 goto err_clear_drvdata
;
1655 platform_set_drvdata(pdev
, NULL
);
1656 rtl8366_smi_cleanup(smi
);
1663 static int rtl8366s_phy_config_init(struct phy_device
*phydev
)
1665 if (!rtl8366s_mii_bus_match(phydev
->bus
))
1671 static int rtl8366s_phy_config_aneg(struct phy_device
*phydev
)
1676 static struct phy_driver rtl8366s_phy_driver
= {
1677 .phy_id
= 0x001cc960,
1678 .name
= "Realtek RTL8366S",
1679 .phy_id_mask
= 0x1ffffff0,
1680 .features
= PHY_GBIT_FEATURES
,
1681 .config_aneg
= rtl8366s_phy_config_aneg
,
1682 .config_init
= rtl8366s_phy_config_init
,
1683 .read_status
= genphy_read_status
,
1685 .owner
= THIS_MODULE
,
1689 static int __devexit
rtl8366s_remove(struct platform_device
*pdev
)
1691 struct rtl8366s
*rtl
= platform_get_drvdata(pdev
);
1694 rtl8366s_switch_cleanup(rtl
);
1695 rtl8366s_debugfs_remove(rtl
);
1696 platform_set_drvdata(pdev
, NULL
);
1697 rtl8366_smi_cleanup(&rtl
->smi
);
1704 static struct platform_driver rtl8366s_driver
= {
1706 .name
= RTL8366S_DRIVER_NAME
,
1707 .owner
= THIS_MODULE
,
1709 .probe
= rtl8366s_probe
,
1710 .remove
= __devexit_p(rtl8366s_remove
),
1713 static int __init
rtl8366s_module_init(void)
1716 ret
= platform_driver_register(&rtl8366s_driver
);
1720 ret
= phy_driver_register(&rtl8366s_phy_driver
);
1722 goto err_platform_unregister
;
1726 err_platform_unregister
:
1727 platform_driver_unregister(&rtl8366s_driver
);
1730 module_init(rtl8366s_module_init
);
1732 static void __exit
rtl8366s_module_exit(void)
1734 phy_driver_unregister(&rtl8366s_phy_driver
);
1735 platform_driver_unregister(&rtl8366s_driver
);
1737 module_exit(rtl8366s_module_exit
);
1739 MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC
);
1740 MODULE_VERSION(RTL8366S_DRIVER_VER
);
1741 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1742 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1743 MODULE_LICENSE("GPL v2");
1744 MODULE_ALIAS("platform:" RTL8366S_DRIVER_NAME
);