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[openwrt/staging/chunkeey.git] / target / linux / generic-2.6 / files / drivers / net / phy / rtl8366s.c
1 /*
2 * Platform driver for the Realtek RTL8366S ethernet switch
3 *
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/skbuff.h>
18 #include <linux/switch.h>
19 #include <linux/rtl8366s.h>
20
21 #include "rtl8366_smi.h"
22
23 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
24 #include <linux/debugfs.h>
25 #endif
26
27 #define RTL8366S_DRIVER_DESC "Realtek RTL8366S ethernet switch driver"
28 #define RTL8366S_DRIVER_VER "0.2.2"
29
30 #define RTL8366S_PHY_NO_MAX 4
31 #define RTL8366S_PHY_PAGE_MAX 7
32 #define RTL8366S_PHY_ADDR_MAX 31
33
34 #define RTL8366_CHIP_GLOBAL_CTRL_REG 0x0000
35 #define RTL8366_CHIP_CTRL_VLAN (1 << 13)
36
37 #define RTL8366_RESET_CTRL_REG 0x0100
38 #define RTL8366_CHIP_CTRL_RESET_HW 1
39 #define RTL8366_CHIP_CTRL_RESET_SW (1 << 1)
40
41 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104
42 #define RTL8366S_CHIP_VERSION_MASK 0xf
43 #define RTL8366S_CHIP_ID_REG 0x0105
44 #define RTL8366S_CHIP_ID_8366 0x8366
45
46 /* PHY registers control */
47 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028
48 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8029
49
50 #define RTL8366S_PHY_CTRL_READ 1
51 #define RTL8366S_PHY_CTRL_WRITE 0
52
53 #define RTL8366S_PHY_REG_MASK 0x1f
54 #define RTL8366S_PHY_PAGE_OFFSET 5
55 #define RTL8366S_PHY_PAGE_MASK (0x7 << 5)
56 #define RTL8366S_PHY_NO_OFFSET 9
57 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
58
59 /* LED control registers */
60 #define RTL8366_LED_BLINKRATE_REG 0x0420
61 #define RTL8366_LED_BLINKRATE_BIT 0
62 #define RTL8366_LED_BLINKRATE_MASK 0x0007
63
64 #define RTL8366_LED_CTRL_REG 0x0421
65 #define RTL8366_LED_0_1_CTRL_REG 0x0422
66 #define RTL8366_LED_2_3_CTRL_REG 0x0423
67
68 #define RTL8366S_MIB_COUNT 33
69 #define RTL8366S_GLOBAL_MIB_COUNT 1
70 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040
71 #define RTL8366S_MIB_COUNTER_BASE 0x1000
72 #define RTL8366S_MIB_CTRL_REG 0x11F0
73 #define RTL8366S_MIB_CTRL_USER_MASK 0x01FF
74 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
75 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0002
76
77 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
78 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
79 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
80
81
82 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058
83 #define RTL8366S_PORT_VLAN_CTRL_REG(_p) \
84 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
85 #define RTL8366S_PORT_VLAN_CTRL_MASK 0xf
86 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
87
88
89 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018B
90 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
91
92 #define RTL8366S_VLAN_TB_CTRL_REG 0x010F
93
94 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
95 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
96 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
97
98 #define RTL8366S_VLAN_MEMCONF_BASE 0x0016
99
100
101 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0060
102 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
103 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
104 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
105 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
106 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
107 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
108
109
110 #define RTL8366_PORT_NUM_CPU 5
111 #define RTL8366_NUM_PORTS 6
112 #define RTL8366_NUM_VLANS 16
113 #define RTL8366_NUM_LEDGROUPS 4
114 #define RTL8366_NUM_VIDS 4096
115 #define RTL8366S_PRIORITYMAX 7
116 #define RTL8366S_FIDMAX 7
117
118
119 #define RTL8366_PORT_1 (1 << 0) /* In userspace port 0 */
120 #define RTL8366_PORT_2 (1 << 1) /* In userspace port 1 */
121 #define RTL8366_PORT_3 (1 << 2) /* In userspace port 2 */
122 #define RTL8366_PORT_4 (1 << 3) /* In userspace port 3 */
123
124 #define RTL8366_PORT_UNKNOWN (1 << 4) /* No known connection */
125 #define RTL8366_PORT_CPU (1 << 5) /* CPU port */
126
127 #define RTL8366_PORT_ALL (RTL8366_PORT_1 | \
128 RTL8366_PORT_2 | \
129 RTL8366_PORT_3 | \
130 RTL8366_PORT_4 | \
131 RTL8366_PORT_UNKNOWN | \
132 RTL8366_PORT_CPU)
133
134 #define RTL8366_PORT_ALL_BUT_CPU (RTL8366_PORT_1 | \
135 RTL8366_PORT_2 | \
136 RTL8366_PORT_3 | \
137 RTL8366_PORT_4 | \
138 RTL8366_PORT_UNKNOWN)
139
140 #define RTL8366_PORT_ALL_EXTERNAL (RTL8366_PORT_1 | \
141 RTL8366_PORT_2 | \
142 RTL8366_PORT_3 | \
143 RTL8366_PORT_4)
144
145 #define RTL8366_PORT_ALL_INTERNAL (RTL8366_PORT_UNKNOWN | \
146 RTL8366_PORT_CPU)
147
148 struct rtl8366s {
149 struct device *parent;
150 struct rtl8366_smi smi;
151 struct switch_dev dev;
152 char buf[4096];
153 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
154 struct dentry *debugfs_root;
155 #endif
156 };
157
158 struct rtl8366s_vlan_mc {
159 u16 reserved2:1;
160 u16 priority:3;
161 u16 vid:12;
162
163 u16 reserved1:1;
164 u16 fid:3;
165 u16 untag:6;
166 u16 member:6;
167 };
168
169 struct rtl8366s_vlan_4k {
170 u16 reserved1:4;
171 u16 vid:12;
172
173 u16 reserved2:1;
174 u16 fid:3;
175 u16 untag:6;
176 u16 member:6;
177 };
178
179 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
180 u16 g_dbg_reg;
181 #endif
182
183 struct mib_counter {
184 unsigned offset;
185 unsigned length;
186 const char *name;
187 };
188
189 static struct mib_counter rtl8366s_mib_counters[RTL8366S_MIB_COUNT] = {
190 { 0, 4, "IfInOctets " },
191 { 4, 4, "EtherStatsOctets " },
192 { 8, 2, "EtherStatsUnderSizePkts " },
193 { 10, 2, "EtherFregament " },
194 { 12, 2, "EtherStatsPkts64Octets " },
195 { 14, 2, "EtherStatsPkts65to127Octets " },
196 { 16, 2, "EtherStatsPkts128to255Octets " },
197 { 18, 2, "EtherStatsPkts256to511Octets " },
198 { 20, 2, "EtherStatsPkts512to1023Octets " },
199 { 22, 2, "EtherStatsPkts1024to1518Octets " },
200 { 24, 2, "EtherOversizeStats " },
201 { 26, 2, "EtherStatsJabbers " },
202 { 28, 2, "IfInUcastPkts " },
203 { 30, 2, "EtherStatsMulticastPkts " },
204 { 32, 2, "EtherStatsBroadcastPkts " },
205 { 34, 2, "EtherStatsDropEvents " },
206 { 36, 2, "Dot3StatsFCSErrors " },
207 { 38, 2, "Dot3StatsSymbolErrors " },
208 { 40, 2, "Dot3InPauseFrames " },
209 { 42, 2, "Dot3ControlInUnknownOpcodes " },
210 { 44, 4, "IfOutOctets " },
211 { 48, 2, "Dot3StatsSingleCollisionFrames " },
212 { 50, 2, "Dot3StatMultipleCollisionFrames " },
213 { 52, 2, "Dot3sDeferredTransmissions " },
214 { 54, 2, "Dot3StatsLateCollisions " },
215 { 56, 2, "EtherStatsCollisions " },
216 { 58, 2, "Dot3StatsExcessiveCollisions " },
217 { 60, 2, "Dot3OutPauseFrames " },
218 { 62, 2, "Dot1dBasePortDelayExceededDiscards" },
219 { 64, 2, "Dot1dTpPortInDiscards " },
220 { 66, 2, "IfOutUcastPkts " },
221 { 68, 2, "IfOutMulticastPkts " },
222 { 70, 2, "IfOutBroadcastPkts " },
223 };
224
225 static inline struct rtl8366s *smi_to_rtl8366s(struct rtl8366_smi *smi)
226 {
227 return container_of(smi, struct rtl8366s, smi);
228 }
229
230 static inline struct rtl8366s *sw_to_rtl8366s(struct switch_dev *sw)
231 {
232 return container_of(sw, struct rtl8366s, dev);
233 }
234
235 static int rtl8366s_reset_chip(struct rtl8366s *rtl)
236 {
237 struct rtl8366_smi *smi = &rtl->smi;
238 int timeout = 10;
239 u32 data;
240
241 rtl8366_smi_write_reg(smi, RTL8366_RESET_CTRL_REG,
242 RTL8366_CHIP_CTRL_RESET_HW);
243 do {
244 msleep(1);
245 if (rtl8366_smi_read_reg(smi, RTL8366_RESET_CTRL_REG, &data))
246 return -EIO;
247
248 if (!(data & RTL8366_CHIP_CTRL_RESET_HW))
249 break;
250 } while (--timeout);
251
252 if (!timeout) {
253 printk("Timeout waiting for the switch to reset\n");
254 return -EIO;
255 }
256
257 return 0;
258 }
259
260 static int rtl8366s_read_phy_reg(struct rtl8366_smi *smi,
261 u32 phy_no, u32 page, u32 addr, u32 *data)
262 {
263 u32 reg;
264 int ret;
265
266 if (phy_no > RTL8366S_PHY_NO_MAX)
267 return -EINVAL;
268
269 if (page > RTL8366S_PHY_PAGE_MAX)
270 return -EINVAL;
271
272 if (addr > RTL8366S_PHY_ADDR_MAX)
273 return -EINVAL;
274
275 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
276 RTL8366S_PHY_CTRL_READ);
277 if (ret)
278 return ret;
279
280 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
281 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
282 (addr & RTL8366S_PHY_REG_MASK);
283
284 ret = rtl8366_smi_write_reg(smi, reg, 0);
285 if (ret)
286 return ret;
287
288 ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
289 if (ret)
290 return ret;
291
292 return 0;
293 }
294
295 static int rtl8366s_write_phy_reg(struct rtl8366_smi *smi,
296 u32 phy_no, u32 page, u32 addr, u32 data)
297 {
298 u32 reg;
299 int ret;
300
301 if (phy_no > RTL8366S_PHY_NO_MAX)
302 return -EINVAL;
303
304 if (page > RTL8366S_PHY_PAGE_MAX)
305 return -EINVAL;
306
307 if (addr > RTL8366S_PHY_ADDR_MAX)
308 return -EINVAL;
309
310 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
311 RTL8366S_PHY_CTRL_WRITE);
312 if (ret)
313 return ret;
314
315 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
316 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
317 (addr & RTL8366S_PHY_REG_MASK);
318
319 ret = rtl8366_smi_write_reg(smi, reg, data);
320 if (ret)
321 return ret;
322
323 return 0;
324 }
325
326 static int rtl8366_get_mib_counter(struct rtl8366s *rtl, int counter,
327 int port, unsigned long long *val)
328 {
329 struct rtl8366_smi *smi = &rtl->smi;
330 int i;
331 int err;
332 u32 addr, data;
333 u64 mibvalue;
334
335 if (port > RTL8366_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
336 return -EINVAL;
337
338 addr = RTL8366S_MIB_COUNTER_BASE +
339 RTL8366S_MIB_COUNTER_PORT_OFFSET * (port) +
340 rtl8366s_mib_counters[counter].offset;
341
342 /*
343 * Writing access counter address first
344 * then ASIC will prepare 64bits counter wait for being retrived
345 */
346 data = 0; /* writing data will be discard by ASIC */
347 err = rtl8366_smi_write_reg(smi, addr, data);
348 if (err)
349 return err;
350
351 /* read MIB control register */
352 err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
353 if (err)
354 return err;
355
356 if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
357 return -EBUSY;
358
359 if (data & RTL8366S_MIB_CTRL_RESET_MASK)
360 return -EIO;
361
362 mibvalue = 0;
363 for (i = rtl8366s_mib_counters[counter].length; i > 0; i--) {
364 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
365 if (err)
366 return err;
367
368 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
369 }
370
371 *val = mibvalue;
372 return 0;
373 }
374
375 static int rtl8366s_get_vlan_4k(struct rtl8366s *rtl, u32 vid,
376 struct rtl8366_vlan_4k *vlan4k)
377 {
378 struct rtl8366_smi *smi = &rtl->smi;
379 struct rtl8366s_vlan_4k vlan4k_priv;
380 int err;
381 u32 data;
382 u16 *tableaddr;
383
384 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
385 vlan4k_priv.vid = vid;
386
387 if (vid >= RTL8366_NUM_VIDS)
388 return -EINVAL;
389
390 tableaddr = (u16 *)&vlan4k_priv;
391
392 /* write VID */
393 data = *tableaddr;
394 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
395 if (err)
396 return err;
397
398 /* write table access control word */
399 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
400 RTL8366S_TABLE_VLAN_READ_CTRL);
401 if (err)
402 return err;
403
404 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE, &data);
405 if (err)
406 return err;
407
408 *tableaddr = data;
409 tableaddr++;
410
411 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 1,
412 &data);
413 if (err)
414 return err;
415
416 *tableaddr = data;
417
418 vlan4k->vid = vid;
419 vlan4k->untag = vlan4k_priv.untag;
420 vlan4k->member = vlan4k_priv.member;
421 vlan4k->fid = vlan4k_priv.fid;
422
423 return 0;
424 }
425
426 static int rtl8366s_set_vlan_4k(struct rtl8366s *rtl,
427 const struct rtl8366_vlan_4k *vlan4k)
428 {
429 struct rtl8366_smi *smi = &rtl->smi;
430 struct rtl8366s_vlan_4k vlan4k_priv;
431 int err;
432 u32 data;
433 u16 *tableaddr;
434
435 if (vlan4k->vid >= RTL8366_NUM_VIDS ||
436 vlan4k->member > RTL8366_PORT_ALL ||
437 vlan4k->untag > RTL8366_PORT_ALL ||
438 vlan4k->fid > RTL8366S_FIDMAX)
439 return -EINVAL;
440
441 vlan4k_priv.vid = vlan4k->vid;
442 vlan4k_priv.untag = vlan4k->untag;
443 vlan4k_priv.member = vlan4k->member;
444 vlan4k_priv.fid = vlan4k->fid;
445
446 tableaddr = (u16 *)&vlan4k_priv;
447
448 data = *tableaddr;
449
450 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
451 if (err)
452 return err;
453
454 tableaddr++;
455
456 data = *tableaddr;
457
458 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 1,
459 data);
460 if (err)
461 return err;
462
463 /* write table access control word */
464 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
465 RTL8366S_TABLE_VLAN_WRITE_CTRL);
466
467 return err;
468 }
469
470 static int rtl8366s_get_vlan_mc(struct rtl8366s *rtl, u32 index,
471 struct rtl8366_vlan_mc *vlanmc)
472 {
473 struct rtl8366_smi *smi = &rtl->smi;
474 struct rtl8366s_vlan_mc vlanmc_priv;
475 int err;
476 u32 addr;
477 u32 data;
478 u16 *tableaddr;
479
480 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
481
482 if (index >= RTL8366_NUM_VLANS)
483 return -EINVAL;
484
485 tableaddr = (u16 *)&vlanmc_priv;
486
487 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
488 err = rtl8366_smi_read_reg(smi, addr, &data);
489 if (err)
490 return err;
491
492 *tableaddr = data;
493 tableaddr++;
494
495 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
496 err = rtl8366_smi_read_reg(smi, addr, &data);
497 if (err)
498 return err;
499
500 *tableaddr = data;
501
502 vlanmc->vid = vlanmc_priv.vid;
503 vlanmc->priority = vlanmc_priv.priority;
504 vlanmc->untag = vlanmc_priv.untag;
505 vlanmc->member = vlanmc_priv.member;
506 vlanmc->fid = vlanmc_priv.fid;
507
508 return 0;
509 }
510
511 static int rtl8366s_set_vlan_mc(struct rtl8366s *rtl, u32 index,
512 const struct rtl8366_vlan_mc *vlanmc)
513 {
514 struct rtl8366_smi *smi = &rtl->smi;
515 struct rtl8366s_vlan_mc vlanmc_priv;
516 int err;
517 u32 addr;
518 u32 data;
519 u16 *tableaddr;
520
521 if (index >= RTL8366_NUM_VLANS ||
522 vlanmc->vid >= RTL8366_NUM_VIDS ||
523 vlanmc->priority > RTL8366S_PRIORITYMAX ||
524 vlanmc->member > RTL8366_PORT_ALL ||
525 vlanmc->untag > RTL8366_PORT_ALL ||
526 vlanmc->fid > RTL8366S_FIDMAX)
527 return -EINVAL;
528
529 vlanmc_priv.vid = vlanmc->vid;
530 vlanmc_priv.priority = vlanmc->priority;
531 vlanmc_priv.untag = vlanmc->untag;
532 vlanmc_priv.member = vlanmc->member;
533 vlanmc_priv.fid = vlanmc->fid;
534
535 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
536
537 tableaddr = (u16 *)&vlanmc_priv;
538 data = *tableaddr;
539
540 err = rtl8366_smi_write_reg(smi, addr, data);
541 if (err)
542 return err;
543
544 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
545
546 tableaddr++;
547 data = *tableaddr;
548
549 err = rtl8366_smi_write_reg(smi, addr, data);
550 if (err)
551 return err;
552
553 return 0;
554 }
555
556 static int rtl8366s_get_port_vlan_index(struct rtl8366s *rtl, int port,
557 int *val)
558 {
559 struct rtl8366_smi *smi = &rtl->smi;
560 u32 data;
561 int err;
562
563 if (port >= RTL8366_NUM_PORTS)
564 return -EINVAL;
565
566 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
567 &data);
568 if (err)
569 return err;
570
571 *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &
572 RTL8366S_PORT_VLAN_CTRL_MASK;
573
574 return 0;
575
576 }
577
578 static int rtl8366s_get_vlan_port_pvid(struct rtl8366s *rtl, int port,
579 int *val)
580 {
581 struct rtl8366_vlan_mc vlanmc;
582 int err;
583 int index;
584
585 err = rtl8366s_get_port_vlan_index(rtl, port, &index);
586 if (err)
587 return err;
588
589 err = rtl8366s_get_vlan_mc(rtl, index, &vlanmc);
590 if (err)
591 return err;
592
593 *val = vlanmc.vid;
594 return 0;
595 }
596
597 static int rtl8366s_set_port_vlan_index(struct rtl8366s *rtl, int port,
598 int index)
599 {
600 struct rtl8366_smi *smi = &rtl->smi;
601 u32 data;
602 int err;
603
604 if (port >= RTL8366_NUM_PORTS || index >= RTL8366_NUM_VLANS)
605 return -EINVAL;
606
607 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
608 &data);
609 if (err)
610 return err;
611
612 data &= ~(RTL8366S_PORT_VLAN_CTRL_MASK <<
613 RTL8366S_PORT_VLAN_CTRL_SHIFT(port));
614 data |= (index & RTL8366S_PORT_VLAN_CTRL_MASK) <<
615 RTL8366S_PORT_VLAN_CTRL_SHIFT(port);
616
617 err = rtl8366_smi_write_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
618 data);
619 return err;
620 }
621
622 static int rtl8366s_set_vlan_port_pvid(struct rtl8366s *rtl, int port, int val)
623 {
624 int i;
625 struct rtl8366_vlan_mc vlanmc;
626 struct rtl8366_vlan_4k vlan4k;
627
628 if (port >= RTL8366_NUM_PORTS || val >= RTL8366_NUM_VIDS)
629 return -EINVAL;
630
631 /* Updating the 4K entry; lookup it and change the port member set */
632 rtl8366s_get_vlan_4k(rtl, val, &vlan4k);
633 vlan4k.member |= ((1 << port) | RTL8366_PORT_CPU);
634 vlan4k.untag = RTL8366_PORT_ALL_BUT_CPU;
635 rtl8366s_set_vlan_4k(rtl, &vlan4k);
636
637 /*
638 * For the 16 entries more work needs to be done. First see if such
639 * VID is already there and change it
640 */
641 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
642 rtl8366s_get_vlan_mc(rtl, i, &vlanmc);
643
644 /* Try to find an existing vid and update port member set */
645 if (val == vlanmc.vid) {
646 vlanmc.member |= ((1 << port) | RTL8366_PORT_CPU);
647 rtl8366s_set_vlan_mc(rtl, i, &vlanmc);
648
649 /* Now update PVID register settings */
650 rtl8366s_set_port_vlan_index(rtl, port, i);
651
652 return 0;
653 }
654 }
655
656 /*
657 * PVID could not be found from vlan table. Replace unused (one that
658 * has no member ports) with new one
659 */
660 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
661 rtl8366s_get_vlan_mc(rtl, i, &vlanmc);
662
663 /*
664 * See if this vlan member configuration is unused. It is
665 * unused if member set contains no ports or CPU port only
666 */
667 if (!vlanmc.member || vlanmc.member == RTL8366_PORT_CPU) {
668 vlanmc.vid = val;
669 vlanmc.priority = 0;
670 vlanmc.untag = RTL8366_PORT_ALL_BUT_CPU;
671 vlanmc.member = ((1 << port) | RTL8366_PORT_CPU);
672 vlanmc.fid = 0;
673
674 rtl8366s_set_vlan_mc(rtl, i, &vlanmc);
675
676 /* Now update PVID register settings */
677 rtl8366s_set_port_vlan_index(rtl, port, i);
678
679 return 0;
680 }
681 }
682
683 dev_err(rtl->parent,
684 "All 16 vlan member configurations are in use\n");
685
686 return -EINVAL;
687 }
688
689
690 static int rtl8366s_vlan_set_vlan(struct rtl8366s *rtl, int enable)
691 {
692 struct rtl8366_smi *smi = &rtl->smi;
693 u32 data = 0;
694
695 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
696
697 if (enable)
698 data |= RTL8366_CHIP_CTRL_VLAN;
699 else
700 data &= ~RTL8366_CHIP_CTRL_VLAN;
701
702 return rtl8366_smi_write_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, data);
703 }
704
705 static int rtl8366s_vlan_set_4ktable(struct rtl8366s *rtl, int enable)
706 {
707 struct rtl8366_smi *smi = &rtl->smi;
708 u32 data = 0;
709
710 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
711
712 if (enable)
713 data |= 1;
714 else
715 data &= ~1;
716
717 return rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, data);
718 }
719
720 static int rtl8366s_reset_vlan(struct rtl8366s *rtl)
721 {
722 struct rtl8366_vlan_4k vlan4k;
723 struct rtl8366_vlan_mc vlanmc;
724 int err;
725 int i;
726
727 /* clear 16 VLAN member configuration */
728 vlanmc.vid = 0;
729 vlanmc.priority = 0;
730 vlanmc.member = 0;
731 vlanmc.untag = 0;
732 vlanmc.fid = 0;
733 for (i = 0; i < RTL8366_NUM_VLANS; i++) {
734 err = rtl8366s_set_vlan_mc(rtl, i, &vlanmc);
735 if (err)
736 return err;
737 }
738
739 /* Set a default VLAN with vid 1 to 4K table for all ports */
740 vlan4k.vid = 1;
741 vlan4k.member = RTL8366_PORT_ALL;
742 vlan4k.untag = RTL8366_PORT_ALL;
743 vlan4k.fid = 0;
744 err = rtl8366s_set_vlan_4k(rtl, &vlan4k);
745 if (err)
746 return err;
747
748 /* Set all ports PVID to default VLAN */
749 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
750 err = rtl8366s_set_vlan_port_pvid(rtl, i, 0);
751 if (err)
752 return err;
753 }
754
755 return 0;
756 }
757
758 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
759 static int rtl8366s_debugfs_open(struct inode *inode, struct file *file)
760 {
761 file->private_data = inode->i_private;
762 return 0;
763 }
764
765 static ssize_t rtl8366s_read_debugfs_mibs(struct file *file,
766 char __user *user_buf,
767 size_t count, loff_t *ppos)
768 {
769 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
770 int i, j, len = 0;
771 char *buf = rtl->buf;
772
773 len += snprintf(buf + len, sizeof(rtl->buf) - len, "MIB Counters:\n");
774 len += snprintf(buf + len, sizeof(rtl->buf) - len, "Counter"
775 " "
776 "Port 0 \t\t Port 1 \t\t Port 2 \t\t Port 3 \t\t "
777 "Port 4\n");
778
779 for (i = 0; i < 33; ++i) {
780 len += snprintf(buf + len, sizeof(rtl->buf) - len, "%d:%s ",
781 i, rtl8366s_mib_counters[i].name);
782 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
783 unsigned long long counter = 0;
784
785 if (!rtl8366_get_mib_counter(rtl, i, j, &counter))
786 len += snprintf(buf + len,
787 sizeof(rtl->buf) - len,
788 "[%llu]", counter);
789 else
790 len += snprintf(buf + len,
791 sizeof(rtl->buf) - len,
792 "[error]");
793
794 if (j != RTL8366_NUM_PORTS - 1) {
795 if (counter < 100000)
796 len += snprintf(buf + len,
797 sizeof(rtl->buf) - len,
798 "\t");
799
800 len += snprintf(buf + len,
801 sizeof(rtl->buf) - len,
802 "\t");
803 }
804 }
805 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
806 }
807
808 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
809
810 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
811 }
812
813 static ssize_t rtl8366s_read_debugfs_vlan(struct file *file,
814 char __user *user_buf,
815 size_t count, loff_t *ppos)
816 {
817 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
818 int i, j, len = 0;
819 char *buf = rtl->buf;
820
821 len += snprintf(buf + len, sizeof(rtl->buf) - len,
822 "VLAN Member Config:\n");
823 len += snprintf(buf + len, sizeof(rtl->buf) - len,
824 "\t id \t vid \t prio \t member \t untag \t fid "
825 "\tports\n");
826
827 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
828 struct rtl8366_vlan_mc vlanmc;
829
830 rtl8366s_get_vlan_mc(rtl, i, &vlanmc);
831
832 len += snprintf(buf + len, sizeof(rtl->buf) - len,
833 "\t[%d] \t %d \t %d \t 0x%04x \t 0x%04x \t %d "
834 "\t", i, vlanmc.vid, vlanmc.priority,
835 vlanmc.member, vlanmc.untag, vlanmc.fid);
836
837 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
838 int index = 0;
839 if (!rtl8366s_get_port_vlan_index(rtl, j, &index)) {
840 if (index == i)
841 len += snprintf(buf + len,
842 sizeof(rtl->buf) - len,
843 "%d", j);
844 }
845 }
846 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
847 }
848
849 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
850 }
851
852 static ssize_t rtl8366s_read_debugfs_reg(struct file *file,
853 char __user *user_buf,
854 size_t count, loff_t *ppos)
855 {
856 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
857 struct rtl8366_smi *smi = &rtl->smi;
858 u32 t, reg = g_dbg_reg;
859 int err, len = 0;
860 char *buf = rtl->buf;
861
862 memset(buf, '\0', sizeof(rtl->buf));
863
864 err = rtl8366_smi_read_reg(smi, reg, &t);
865 if (err) {
866 len += snprintf(buf, sizeof(rtl->buf),
867 "Read failed (reg: 0x%04x)\n", reg);
868 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
869 }
870
871 len += snprintf(buf, sizeof(rtl->buf), "reg = 0x%04x, val = 0x%04x\n",
872 reg, t);
873
874 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
875 }
876
877 static ssize_t rtl8366s_write_debugfs_reg(struct file *file,
878 const char __user *user_buf,
879 size_t count, loff_t *ppos)
880 {
881 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
882 struct rtl8366_smi *smi = &rtl->smi;
883 unsigned long data;
884 u32 reg = g_dbg_reg;
885 int err;
886 size_t len;
887 char *buf = rtl->buf;
888
889 len = min(count, sizeof(rtl->buf) - 1);
890 if (copy_from_user(buf, user_buf, len)) {
891 dev_err(rtl->parent, "copy from user failed\n");
892 return -EFAULT;
893 }
894
895 buf[len] = '\0';
896 if (len > 0 && buf[len - 1] == '\n')
897 buf[len - 1] = '\0';
898
899
900 if (strict_strtoul(buf, 16, &data)) {
901 dev_err(rtl->parent, "Invalid reg value %s\n", buf);
902 } else {
903 err = rtl8366_smi_write_reg(smi, reg, data);
904 if (err) {
905 dev_err(rtl->parent,
906 "writing reg 0x%04x val 0x%04lx failed\n",
907 reg, data);
908 }
909 }
910
911 return count;
912 }
913
914 static const struct file_operations fops_rtl8366s_regs = {
915 .read = rtl8366s_read_debugfs_reg,
916 .write = rtl8366s_write_debugfs_reg,
917 .open = rtl8366s_debugfs_open,
918 .owner = THIS_MODULE
919 };
920
921 static const struct file_operations fops_rtl8366s_vlan = {
922 .read = rtl8366s_read_debugfs_vlan,
923 .open = rtl8366s_debugfs_open,
924 .owner = THIS_MODULE
925 };
926
927 static const struct file_operations fops_rtl8366s_mibs = {
928 .read = rtl8366s_read_debugfs_mibs,
929 .open = rtl8366s_debugfs_open,
930 .owner = THIS_MODULE
931 };
932
933 static void rtl8366s_debugfs_init(struct rtl8366s *rtl)
934 {
935 struct dentry *node;
936 struct dentry *root;
937
938 if (!rtl->debugfs_root)
939 rtl->debugfs_root = debugfs_create_dir("rtl8366s", NULL);
940
941 if (!rtl->debugfs_root) {
942 dev_err(rtl->parent, "Unable to create debugfs dir\n");
943 return;
944 }
945 root = rtl->debugfs_root;
946
947 node = debugfs_create_x16("reg", S_IRUGO | S_IWUSR, root, &g_dbg_reg);
948 if (!node) {
949 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
950 "reg");
951 return;
952 }
953
954 node = debugfs_create_file("val", S_IRUGO | S_IWUSR, root, rtl,
955 &fops_rtl8366s_regs);
956 if (!node) {
957 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
958 "val");
959 return;
960 }
961
962 node = debugfs_create_file("vlan", S_IRUSR, root, rtl,
963 &fops_rtl8366s_vlan);
964 if (!node) {
965 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
966 "vlan");
967 return;
968 }
969
970 node = debugfs_create_file("mibs", S_IRUSR, root, rtl,
971 &fops_rtl8366s_mibs);
972 if (!node) {
973 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
974 "mibs");
975 return;
976 }
977 }
978
979 static void rtl8366s_debugfs_remove(struct rtl8366s *rtl)
980 {
981 if (rtl->debugfs_root) {
982 debugfs_remove_recursive(rtl->debugfs_root);
983 rtl->debugfs_root = NULL;
984 }
985 }
986
987 #else
988 static inline void rtl8366s_debugfs_init(struct rtl8366s *rtl) {}
989 static inline void rtl8366s_debugfs_remove(struct rtl8366s *rtl) {}
990 #endif /* CONFIG_RTL8366S_PHY_DEBUG_FS */
991
992 static int rtl8366s_sw_reset_mibs(struct switch_dev *dev,
993 const struct switch_attr *attr,
994 struct switch_val *val)
995 {
996 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
997 struct rtl8366_smi *smi = &rtl->smi;
998 u32 data = 0;
999
1000 if (val->value.i == 1) {
1001 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1002 data |= (1 << 2);
1003 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1004 }
1005
1006 return 0;
1007 }
1008
1009 static int rtl8366s_sw_get_vlan_enable(struct switch_dev *dev,
1010 const struct switch_attr *attr,
1011 struct switch_val *val)
1012 {
1013 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1014 struct rtl8366_smi *smi = &rtl->smi;
1015 u32 data;
1016
1017 if (attr->ofs == 1) {
1018 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
1019
1020 if (data & RTL8366_CHIP_CTRL_VLAN)
1021 val->value.i = 1;
1022 else
1023 val->value.i = 0;
1024 } else if (attr->ofs == 2) {
1025 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
1026
1027 if (data & 0x0001)
1028 val->value.i = 1;
1029 else
1030 val->value.i = 0;
1031 }
1032
1033 return 0;
1034 }
1035
1036 static int rtl8366s_sw_get_blinkrate(struct switch_dev *dev,
1037 const struct switch_attr *attr,
1038 struct switch_val *val)
1039 {
1040 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1041 struct rtl8366_smi *smi = &rtl->smi;
1042 u32 data;
1043
1044 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1045
1046 val->value.i = (data & (RTL8366_LED_BLINKRATE_MASK));
1047
1048 return 0;
1049 }
1050
1051 static int rtl8366s_sw_set_blinkrate(struct switch_dev *dev,
1052 const struct switch_attr *attr,
1053 struct switch_val *val)
1054 {
1055 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1056 struct rtl8366_smi *smi = &rtl->smi;
1057 u32 data;
1058
1059 if (val->value.i >= 6)
1060 return -EINVAL;
1061
1062 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1063
1064 data &= ~RTL8366_LED_BLINKRATE_MASK;
1065 data |= val->value.i;
1066
1067 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1068
1069 return 0;
1070 }
1071
1072 static int rtl8366s_sw_set_vlan_enable(struct switch_dev *dev,
1073 const struct switch_attr *attr,
1074 struct switch_val *val)
1075 {
1076 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1077
1078 if (attr->ofs == 1)
1079 return rtl8366s_vlan_set_vlan(rtl, val->value.i);
1080 else
1081 return rtl8366s_vlan_set_4ktable(rtl, val->value.i);
1082 }
1083
1084 static const char *rtl8366s_speed_str(unsigned speed)
1085 {
1086 switch (speed) {
1087 case 0:
1088 return "10baseT";
1089 case 1:
1090 return "100baseT";
1091 case 2:
1092 return "1000baseT";
1093 }
1094
1095 return "unknown";
1096 }
1097
1098 static int rtl8366s_sw_get_port_link(struct switch_dev *dev,
1099 const struct switch_attr *attr,
1100 struct switch_val *val)
1101 {
1102 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1103 struct rtl8366_smi *smi = &rtl->smi;
1104 u32 len = 0, data = 0;
1105
1106 if (val->port_vlan >= RTL8366_NUM_PORTS)
1107 return -EINVAL;
1108
1109 memset(rtl->buf, '\0', sizeof(rtl->buf));
1110 rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
1111 (val->port_vlan / 2), &data);
1112
1113 if (val->port_vlan % 2)
1114 data = data >> 8;
1115
1116 if (data & RTL8366S_PORT_STATUS_LINK_MASK) {
1117 len = snprintf(rtl->buf, sizeof(rtl->buf),
1118 "port:%d link:up speed:%s %s-duplex %s%s%s",
1119 val->port_vlan,
1120 rtl8366s_speed_str(data &
1121 RTL8366S_PORT_STATUS_SPEED_MASK),
1122 (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) ?
1123 "full" : "half",
1124 (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) ?
1125 "tx-pause ": "",
1126 (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) ?
1127 "rx-pause " : "",
1128 (data & RTL8366S_PORT_STATUS_AN_MASK) ?
1129 "nway ": "");
1130 } else {
1131 len = snprintf(rtl->buf, sizeof(rtl->buf), "port:%d link: down",
1132 val->port_vlan);
1133 }
1134
1135 val->value.s = rtl->buf;
1136 val->len = len;
1137
1138 return 0;
1139 }
1140
1141 static int rtl8366s_sw_get_vlan_info(struct switch_dev *dev,
1142 const struct switch_attr *attr,
1143 struct switch_val *val)
1144 {
1145 int i;
1146 u32 len = 0;
1147 struct rtl8366_vlan_mc vlanmc;
1148 struct rtl8366_vlan_4k vlan4k;
1149 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1150 char *buf = rtl->buf;
1151
1152 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1153 return -EINVAL;
1154
1155 memset(buf, '\0', sizeof(rtl->buf));
1156
1157 rtl8366s_get_vlan_mc(rtl, val->port_vlan, &vlanmc);
1158 rtl8366s_get_vlan_4k(rtl, vlanmc.vid, &vlan4k);
1159
1160 len += snprintf(buf + len, sizeof(rtl->buf) - len, "VLAN %d: Ports: ",
1161 val->port_vlan);
1162
1163 for (i = 0; i < RTL8366_NUM_PORTS; ++i) {
1164 int index = 0;
1165 if (!rtl8366s_get_port_vlan_index(rtl, i, &index) &&
1166 index == val->port_vlan)
1167 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1168 "%d", i);
1169 }
1170 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
1171
1172 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1173 "\t\t vid \t prio \t member \t untag \t fid\n");
1174 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\tMC:\t");
1175 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1176 "%d \t %d \t 0x%04x \t 0x%04x \t %d\n",
1177 vlanmc.vid, vlanmc.priority, vlanmc.member,
1178 vlanmc.untag, vlanmc.fid);
1179 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\t4K:\t");
1180 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1181 "%d \t \t 0x%04x \t 0x%04x \t %d",
1182 vlan4k.vid, vlan4k.member, vlan4k.untag, vlan4k.fid);
1183
1184 val->value.s = buf;
1185 val->len = len;
1186
1187 return 0;
1188 }
1189
1190 static int rtl8366s_sw_set_port_led(struct switch_dev *dev,
1191 const struct switch_attr *attr,
1192 struct switch_val *val)
1193 {
1194 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1195 struct rtl8366_smi *smi = &rtl->smi;
1196 u32 data = 0;
1197
1198 if (val->port_vlan >= RTL8366_NUM_PORTS ||
1199 (1 << val->port_vlan) == RTL8366_PORT_UNKNOWN)
1200 return -EINVAL;
1201
1202 if (val->port_vlan == RTL8366_PORT_NUM_CPU) {
1203 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1204 data = (data & (~(0xF << 4))) | (val->value.i << 4);
1205 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1206 } else {
1207 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1208 data = (data & (~(0xF << (val->port_vlan * 4)))) |
1209 (val->value.i << (val->port_vlan * 4));
1210 rtl8366_smi_write_reg(smi, RTL8366_LED_CTRL_REG, data);
1211 }
1212
1213 return 0;
1214 }
1215
1216 static int rtl8366s_sw_get_port_led(struct switch_dev *dev,
1217 const struct switch_attr *attr,
1218 struct switch_val *val)
1219 {
1220 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1221 struct rtl8366_smi *smi = &rtl->smi;
1222 u32 data = 0;
1223
1224 if (val->port_vlan >= RTL8366_NUM_LEDGROUPS)
1225 return -EINVAL;
1226
1227 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1228 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
1229
1230 return 0;
1231 }
1232
1233 static int rtl8366s_sw_reset_port_mibs(struct switch_dev *dev,
1234 const struct switch_attr *attr,
1235 struct switch_val *val)
1236 {
1237 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1238 struct rtl8366_smi *smi = &rtl->smi;
1239 u32 data = 0;
1240
1241 if (val->port_vlan >= RTL8366_NUM_PORTS)
1242 return -EINVAL;
1243
1244 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1245 data |= (1 << (val->port_vlan + 3));
1246 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1247
1248 return 0;
1249 }
1250
1251 static int rtl8366s_sw_get_port_mib(struct switch_dev *dev,
1252 const struct switch_attr *attr,
1253 struct switch_val *val)
1254 {
1255 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1256 int i, len = 0;
1257 unsigned long long counter = 0;
1258 char *buf = rtl->buf;
1259
1260 if (val->port_vlan >= RTL8366_NUM_PORTS)
1261 return -EINVAL;
1262
1263 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1264 "Port %d MIB counters\n",
1265 val->port_vlan);
1266
1267 for (i = 0; i < RTL8366S_MIB_COUNT; ++i) {
1268 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1269 "%d:%s\t", i, rtl8366s_mib_counters[i].name);
1270 if (!rtl8366_get_mib_counter(rtl, i, val->port_vlan, &counter))
1271 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1272 "[%llu]\n", counter);
1273 else
1274 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1275 "[error]\n");
1276 }
1277
1278 val->value.s = buf;
1279 val->len = len;
1280 return 0;
1281 }
1282
1283 static int rtl8366s_sw_get_vlan_ports(struct switch_dev *dev,
1284 struct switch_val *val)
1285 {
1286 struct rtl8366_vlan_mc vlanmc;
1287 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1288 struct switch_port *port;
1289 int i;
1290
1291 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1292 return -EINVAL;
1293
1294 rtl8366s_get_vlan_mc(rtl, val->port_vlan, &vlanmc);
1295
1296 port = &val->value.ports[0];
1297 val->len = 0;
1298 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
1299 if (!(vlanmc.member & BIT(i)))
1300 continue;
1301
1302 port->id = i;
1303 port->flags = (vlanmc.untag & BIT(i)) ?
1304 0 : BIT(SWITCH_PORT_FLAG_TAGGED);
1305 val->len++;
1306 port++;
1307 }
1308 return 0;
1309 }
1310
1311 static int rtl8366s_sw_set_vlan_ports(struct switch_dev *dev,
1312 struct switch_val *val)
1313 {
1314 struct rtl8366_vlan_mc vlanmc;
1315 struct rtl8366_vlan_4k vlan4k;
1316 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1317 struct switch_port *port;
1318 int i;
1319
1320 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1321 return -EINVAL;
1322
1323 rtl8366s_get_vlan_mc(rtl, val->port_vlan, &vlanmc);
1324 rtl8366s_get_vlan_4k(rtl, vlanmc.vid, &vlan4k);
1325
1326 vlanmc.untag = 0;
1327 vlanmc.member = 0;
1328
1329 port = &val->value.ports[0];
1330 for (i = 0; i < val->len; i++, port++) {
1331 vlanmc.member |= BIT(port->id);
1332
1333 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
1334 vlanmc.untag |= BIT(port->id);
1335 }
1336
1337 vlan4k.member = vlanmc.member;
1338 vlan4k.untag = vlanmc.untag;
1339
1340 rtl8366s_set_vlan_mc(rtl, val->port_vlan, &vlanmc);
1341 rtl8366s_set_vlan_4k(rtl, &vlan4k);
1342 return 0;
1343 }
1344
1345 static int rtl8366s_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1346 {
1347 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1348 return rtl8366s_get_vlan_port_pvid(rtl, port, val);
1349 }
1350
1351 static int rtl8366s_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
1352 {
1353 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1354 return rtl8366s_set_vlan_port_pvid(rtl, port, val);
1355 }
1356
1357 static int rtl8366s_sw_reset_switch(struct switch_dev *dev)
1358 {
1359 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1360 int err;
1361
1362 err = rtl8366s_reset_chip(rtl);
1363 if (err)
1364 return err;
1365
1366 return rtl8366s_reset_vlan(rtl);
1367 }
1368
1369 static struct switch_attr rtl8366s_globals[] = {
1370 {
1371 .type = SWITCH_TYPE_INT,
1372 .name = "enable_vlan",
1373 .description = "Enable VLAN mode",
1374 .set = rtl8366s_sw_set_vlan_enable,
1375 .get = rtl8366s_sw_get_vlan_enable,
1376 .max = 1,
1377 .ofs = 1
1378 }, {
1379 .type = SWITCH_TYPE_INT,
1380 .name = "enable_vlan4k",
1381 .description = "Enable VLAN 4K mode",
1382 .set = rtl8366s_sw_set_vlan_enable,
1383 .get = rtl8366s_sw_get_vlan_enable,
1384 .max = 1,
1385 .ofs = 2
1386 }, {
1387 .type = SWITCH_TYPE_INT,
1388 .name = "reset_mibs",
1389 .description = "Reset all MIB counters",
1390 .set = rtl8366s_sw_reset_mibs,
1391 .get = NULL,
1392 .max = 1
1393 }, {
1394 .type = SWITCH_TYPE_INT,
1395 .name = "blinkrate",
1396 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1397 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1398 .set = rtl8366s_sw_set_blinkrate,
1399 .get = rtl8366s_sw_get_blinkrate,
1400 .max = 5
1401 },
1402 };
1403
1404 static struct switch_attr rtl8366s_port[] = {
1405 {
1406 .type = SWITCH_TYPE_STRING,
1407 .name = "link",
1408 .description = "Get port link information",
1409 .max = 1,
1410 .set = NULL,
1411 .get = rtl8366s_sw_get_port_link,
1412 }, {
1413 .type = SWITCH_TYPE_INT,
1414 .name = "reset_mib",
1415 .description = "Reset single port MIB counters",
1416 .max = 1,
1417 .set = rtl8366s_sw_reset_port_mibs,
1418 .get = NULL,
1419 }, {
1420 .type = SWITCH_TYPE_STRING,
1421 .name = "mib",
1422 .description = "Get MIB counters for port",
1423 .max = 33,
1424 .set = NULL,
1425 .get = rtl8366s_sw_get_port_mib,
1426 }, {
1427 .type = SWITCH_TYPE_INT,
1428 .name = "led",
1429 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1430 .max = 15,
1431 .set = rtl8366s_sw_set_port_led,
1432 .get = rtl8366s_sw_get_port_led,
1433 },
1434 };
1435
1436 static struct switch_attr rtl8366s_vlan[] = {
1437 {
1438 .type = SWITCH_TYPE_STRING,
1439 .name = "info",
1440 .description = "Get vlan information",
1441 .max = 1,
1442 .set = NULL,
1443 .get = rtl8366s_sw_get_vlan_info,
1444 },
1445 };
1446
1447 /* template */
1448 static struct switch_dev rtl8366_switch_dev = {
1449 .name = "RTL8366S",
1450 .cpu_port = RTL8366_PORT_NUM_CPU,
1451 .ports = RTL8366_NUM_PORTS,
1452 .vlans = RTL8366_NUM_VLANS,
1453 .attr_global = {
1454 .attr = rtl8366s_globals,
1455 .n_attr = ARRAY_SIZE(rtl8366s_globals),
1456 },
1457 .attr_port = {
1458 .attr = rtl8366s_port,
1459 .n_attr = ARRAY_SIZE(rtl8366s_port),
1460 },
1461 .attr_vlan = {
1462 .attr = rtl8366s_vlan,
1463 .n_attr = ARRAY_SIZE(rtl8366s_vlan),
1464 },
1465
1466 .get_vlan_ports = rtl8366s_sw_get_vlan_ports,
1467 .set_vlan_ports = rtl8366s_sw_set_vlan_ports,
1468 .get_port_pvid = rtl8366s_sw_get_port_pvid,
1469 .set_port_pvid = rtl8366s_sw_set_port_pvid,
1470 .reset_switch = rtl8366s_sw_reset_switch,
1471 };
1472
1473 static int rtl8366s_switch_init(struct rtl8366s *rtl)
1474 {
1475 struct switch_dev *dev = &rtl->dev;
1476 int err;
1477
1478 memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev));
1479 dev->priv = rtl;
1480 dev->devname = dev_name(rtl->parent);
1481
1482 err = register_switch(dev, NULL);
1483 if (err)
1484 dev_err(rtl->parent, "switch registration failed\n");
1485
1486 return err;
1487 }
1488
1489 static void rtl8366s_switch_cleanup(struct rtl8366s *rtl)
1490 {
1491 unregister_switch(&rtl->dev);
1492 }
1493
1494 static int rtl8366s_mii_read(struct mii_bus *bus, int addr, int reg)
1495 {
1496 struct rtl8366_smi *smi = bus->priv;
1497 u32 val = 0;
1498 int err;
1499
1500 err = rtl8366s_read_phy_reg(smi, addr, 0, reg, &val);
1501 if (err)
1502 return 0xffff;
1503
1504 return val;
1505 }
1506
1507 static int rtl8366s_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1508 {
1509 struct rtl8366_smi *smi = bus->priv;
1510 u32 t;
1511 int err;
1512
1513 err = rtl8366s_write_phy_reg(smi, addr, 0, reg, val);
1514 /* flush write */
1515 (void) rtl8366s_read_phy_reg(smi, addr, 0, reg, &t);
1516
1517 return err;
1518 }
1519
1520 static int rtl8366s_mii_bus_match(struct mii_bus *bus)
1521 {
1522 return (bus->read == rtl8366s_mii_read &&
1523 bus->write == rtl8366s_mii_write);
1524 }
1525
1526 static int rtl8366s_setup(struct rtl8366s *rtl)
1527 {
1528 int ret;
1529
1530 ret = rtl8366s_reset_chip(rtl);
1531 if (ret)
1532 return ret;
1533
1534 rtl8366s_debugfs_init(rtl);
1535 return 0;
1536 }
1537
1538 static int rtl8366s_detect(struct rtl8366_smi *smi)
1539 {
1540 u32 chip_id = 0;
1541 u32 chip_ver = 0;
1542 int ret;
1543
1544 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1545 if (ret) {
1546 dev_err(smi->parent, "unable to read chip id\n");
1547 return ret;
1548 }
1549
1550 switch (chip_id) {
1551 case RTL8366S_CHIP_ID_8366:
1552 break;
1553 default:
1554 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1555 return -ENODEV;
1556 }
1557
1558 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1559 &chip_ver);
1560 if (ret) {
1561 dev_err(smi->parent, "unable to read chip version\n");
1562 return ret;
1563 }
1564
1565 dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1566 chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1567
1568 return 0;
1569 }
1570
1571 static struct rtl8366_smi_ops rtl8366s_smi_ops = {
1572 .detect = rtl8366s_detect,
1573 .mii_read = rtl8366s_mii_read,
1574 .mii_write = rtl8366s_mii_write,
1575 };
1576
1577 static int __init rtl8366s_probe(struct platform_device *pdev)
1578 {
1579 static int rtl8366_smi_version_printed;
1580 struct rtl8366s_platform_data *pdata;
1581 struct rtl8366s *rtl;
1582 struct rtl8366_smi *smi;
1583 int err;
1584
1585 if (!rtl8366_smi_version_printed++)
1586 printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1587 " version " RTL8366S_DRIVER_VER"\n");
1588
1589 pdata = pdev->dev.platform_data;
1590 if (!pdata) {
1591 dev_err(&pdev->dev, "no platform data specified\n");
1592 err = -EINVAL;
1593 goto err_out;
1594 }
1595
1596 rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1597 if (!rtl) {
1598 dev_err(&pdev->dev, "no memory for private data\n");
1599 err = -ENOMEM;
1600 goto err_out;
1601 }
1602
1603 rtl->parent = &pdev->dev;
1604
1605 smi = &rtl->smi;
1606 smi->parent = &pdev->dev;
1607 smi->gpio_sda = pdata->gpio_sda;
1608 smi->gpio_sck = pdata->gpio_sck;
1609 smi->ops = &rtl8366s_smi_ops;
1610
1611 err = rtl8366_smi_init(smi);
1612 if (err)
1613 goto err_free_rtl;
1614
1615 platform_set_drvdata(pdev, rtl);
1616
1617 err = rtl8366s_setup(rtl);
1618 if (err)
1619 goto err_clear_drvdata;
1620
1621 err = rtl8366s_switch_init(rtl);
1622 if (err)
1623 goto err_clear_drvdata;
1624
1625 return 0;
1626
1627 err_clear_drvdata:
1628 platform_set_drvdata(pdev, NULL);
1629 rtl8366_smi_cleanup(smi);
1630 err_free_rtl:
1631 kfree(rtl);
1632 err_out:
1633 return err;
1634 }
1635
1636 static int rtl8366s_phy_config_init(struct phy_device *phydev)
1637 {
1638 if (!rtl8366s_mii_bus_match(phydev->bus))
1639 return -EINVAL;
1640
1641 return 0;
1642 }
1643
1644 static int rtl8366s_phy_config_aneg(struct phy_device *phydev)
1645 {
1646 return 0;
1647 }
1648
1649 static struct phy_driver rtl8366s_phy_driver = {
1650 .phy_id = 0x001cc960,
1651 .name = "Realtek RTL8366S",
1652 .phy_id_mask = 0x1ffffff0,
1653 .features = PHY_GBIT_FEATURES,
1654 .config_aneg = rtl8366s_phy_config_aneg,
1655 .config_init = rtl8366s_phy_config_init,
1656 .read_status = genphy_read_status,
1657 .driver = {
1658 .owner = THIS_MODULE,
1659 },
1660 };
1661
1662 static int __devexit rtl8366s_remove(struct platform_device *pdev)
1663 {
1664 struct rtl8366s *rtl = platform_get_drvdata(pdev);
1665
1666 if (rtl) {
1667 rtl8366s_switch_cleanup(rtl);
1668 rtl8366s_debugfs_remove(rtl);
1669 platform_set_drvdata(pdev, NULL);
1670 rtl8366_smi_cleanup(&rtl->smi);
1671 kfree(rtl);
1672 }
1673
1674 return 0;
1675 }
1676
1677 static struct platform_driver rtl8366s_driver = {
1678 .driver = {
1679 .name = RTL8366S_DRIVER_NAME,
1680 .owner = THIS_MODULE,
1681 },
1682 .probe = rtl8366s_probe,
1683 .remove = __devexit_p(rtl8366s_remove),
1684 };
1685
1686 static int __init rtl8366s_module_init(void)
1687 {
1688 int ret;
1689 ret = platform_driver_register(&rtl8366s_driver);
1690 if (ret)
1691 return ret;
1692
1693 ret = phy_driver_register(&rtl8366s_phy_driver);
1694 if (ret)
1695 goto err_platform_unregister;
1696
1697 return 0;
1698
1699 err_platform_unregister:
1700 platform_driver_unregister(&rtl8366s_driver);
1701 return ret;
1702 }
1703 module_init(rtl8366s_module_init);
1704
1705 static void __exit rtl8366s_module_exit(void)
1706 {
1707 phy_driver_unregister(&rtl8366s_phy_driver);
1708 platform_driver_unregister(&rtl8366s_driver);
1709 }
1710 module_exit(rtl8366s_module_exit);
1711
1712 MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC);
1713 MODULE_VERSION(RTL8366S_DRIVER_VER);
1714 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1715 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1716 MODULE_LICENSE("GPL v2");
1717 MODULE_ALIAS("platform:" RTL8366S_DRIVER_NAME);
Staging tree of Christian Lamparter