2 * Platform driver for the Realtek RTL8366S ethernet switch
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/skbuff.h>
18 #include <linux/switch.h>
19 #include <linux/rtl8366s.h>
21 #include "rtl8366_smi.h"
23 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
24 #include <linux/debugfs.h>
27 #define RTL8366S_DRIVER_DESC "Realtek RTL8366S ethernet switch driver"
28 #define RTL8366S_DRIVER_VER "0.2.2"
30 #define RTL8366S_PHY_NO_MAX 4
31 #define RTL8366S_PHY_PAGE_MAX 7
32 #define RTL8366S_PHY_ADDR_MAX 31
34 #define RTL8366_CHIP_GLOBAL_CTRL_REG 0x0000
35 #define RTL8366_CHIP_CTRL_VLAN (1 << 13)
37 #define RTL8366_RESET_CTRL_REG 0x0100
38 #define RTL8366_CHIP_CTRL_RESET_HW 1
39 #define RTL8366_CHIP_CTRL_RESET_SW (1 << 1)
41 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104
42 #define RTL8366S_CHIP_VERSION_MASK 0xf
43 #define RTL8366S_CHIP_ID_REG 0x0105
44 #define RTL8366S_CHIP_ID_8366 0x8366
46 /* PHY registers control */
47 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028
48 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8029
50 #define RTL8366S_PHY_CTRL_READ 1
51 #define RTL8366S_PHY_CTRL_WRITE 0
53 #define RTL8366S_PHY_REG_MASK 0x1f
54 #define RTL8366S_PHY_PAGE_OFFSET 5
55 #define RTL8366S_PHY_PAGE_MASK (0x7 << 5)
56 #define RTL8366S_PHY_NO_OFFSET 9
57 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
59 /* LED control registers */
60 #define RTL8366_LED_BLINKRATE_REG 0x0420
61 #define RTL8366_LED_BLINKRATE_BIT 0
62 #define RTL8366_LED_BLINKRATE_MASK 0x0007
64 #define RTL8366_LED_CTRL_REG 0x0421
65 #define RTL8366_LED_0_1_CTRL_REG 0x0422
66 #define RTL8366_LED_2_3_CTRL_REG 0x0423
68 #define RTL8366S_MIB_COUNT 33
69 #define RTL8366S_GLOBAL_MIB_COUNT 1
70 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040
71 #define RTL8366S_MIB_COUNTER_BASE 0x1000
72 #define RTL8366S_MIB_CTRL_REG 0x11F0
73 #define RTL8366S_MIB_CTRL_USER_MASK 0x01FF
74 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
75 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0002
77 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
78 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
79 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
82 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058
83 #define RTL8366S_PORT_VLAN_CTRL_REG(_p) \
84 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
85 #define RTL8366S_PORT_VLAN_CTRL_MASK 0xf
86 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
89 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018B
90 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
92 #define RTL8366S_VLAN_TB_CTRL_REG 0x010F
94 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
95 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
96 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
98 #define RTL8366S_VLAN_MEMCONF_BASE 0x0016
101 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0060
102 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
103 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
104 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
105 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
106 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
107 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
110 #define RTL8366_PORT_NUM_CPU 5
111 #define RTL8366_NUM_PORTS 6
112 #define RTL8366_NUM_VLANS 16
113 #define RTL8366_NUM_LEDGROUPS 4
114 #define RTL8366_NUM_VIDS 4096
115 #define RTL8366S_PRIORITYMAX 7
116 #define RTL8366S_FIDMAX 7
119 #define RTL8366_PORT_1 (1 << 0) /* In userspace port 0 */
120 #define RTL8366_PORT_2 (1 << 1) /* In userspace port 1 */
121 #define RTL8366_PORT_3 (1 << 2) /* In userspace port 2 */
122 #define RTL8366_PORT_4 (1 << 3) /* In userspace port 3 */
124 #define RTL8366_PORT_UNKNOWN (1 << 4) /* No known connection */
125 #define RTL8366_PORT_CPU (1 << 5) /* CPU port */
127 #define RTL8366_PORT_ALL (RTL8366_PORT_1 | \
131 RTL8366_PORT_UNKNOWN | \
134 #define RTL8366_PORT_ALL_BUT_CPU (RTL8366_PORT_1 | \
138 RTL8366_PORT_UNKNOWN)
140 #define RTL8366_PORT_ALL_EXTERNAL (RTL8366_PORT_1 | \
145 #define RTL8366_PORT_ALL_INTERNAL (RTL8366_PORT_UNKNOWN | \
149 struct device
*parent
;
150 struct rtl8366_smi smi
;
151 struct switch_dev dev
;
153 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
154 struct dentry
*debugfs_root
;
158 struct rtl8366s_vlan_mc
{
169 struct rtl8366s_vlan_4k
{
179 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
189 static struct mib_counter rtl8366s_mib_counters
[RTL8366S_MIB_COUNT
] = {
190 { 0, 4, "IfInOctets " },
191 { 4, 4, "EtherStatsOctets " },
192 { 8, 2, "EtherStatsUnderSizePkts " },
193 { 10, 2, "EtherFregament " },
194 { 12, 2, "EtherStatsPkts64Octets " },
195 { 14, 2, "EtherStatsPkts65to127Octets " },
196 { 16, 2, "EtherStatsPkts128to255Octets " },
197 { 18, 2, "EtherStatsPkts256to511Octets " },
198 { 20, 2, "EtherStatsPkts512to1023Octets " },
199 { 22, 2, "EtherStatsPkts1024to1518Octets " },
200 { 24, 2, "EtherOversizeStats " },
201 { 26, 2, "EtherStatsJabbers " },
202 { 28, 2, "IfInUcastPkts " },
203 { 30, 2, "EtherStatsMulticastPkts " },
204 { 32, 2, "EtherStatsBroadcastPkts " },
205 { 34, 2, "EtherStatsDropEvents " },
206 { 36, 2, "Dot3StatsFCSErrors " },
207 { 38, 2, "Dot3StatsSymbolErrors " },
208 { 40, 2, "Dot3InPauseFrames " },
209 { 42, 2, "Dot3ControlInUnknownOpcodes " },
210 { 44, 4, "IfOutOctets " },
211 { 48, 2, "Dot3StatsSingleCollisionFrames " },
212 { 50, 2, "Dot3StatMultipleCollisionFrames " },
213 { 52, 2, "Dot3sDeferredTransmissions " },
214 { 54, 2, "Dot3StatsLateCollisions " },
215 { 56, 2, "EtherStatsCollisions " },
216 { 58, 2, "Dot3StatsExcessiveCollisions " },
217 { 60, 2, "Dot3OutPauseFrames " },
218 { 62, 2, "Dot1dBasePortDelayExceededDiscards" },
219 { 64, 2, "Dot1dTpPortInDiscards " },
220 { 66, 2, "IfOutUcastPkts " },
221 { 68, 2, "IfOutMulticastPkts " },
222 { 70, 2, "IfOutBroadcastPkts " },
225 static inline struct rtl8366s
*smi_to_rtl8366s(struct rtl8366_smi
*smi
)
227 return container_of(smi
, struct rtl8366s
, smi
);
230 static inline struct rtl8366s
*sw_to_rtl8366s(struct switch_dev
*sw
)
232 return container_of(sw
, struct rtl8366s
, dev
);
235 static int rtl8366s_reset_chip(struct rtl8366s
*rtl
)
237 struct rtl8366_smi
*smi
= &rtl
->smi
;
241 rtl8366_smi_write_reg(smi
, RTL8366_RESET_CTRL_REG
,
242 RTL8366_CHIP_CTRL_RESET_HW
);
245 if (rtl8366_smi_read_reg(smi
, RTL8366_RESET_CTRL_REG
, &data
))
248 if (!(data
& RTL8366_CHIP_CTRL_RESET_HW
))
253 printk("Timeout waiting for the switch to reset\n");
260 static int rtl8366s_read_phy_reg(struct rtl8366_smi
*smi
,
261 u32 phy_no
, u32 page
, u32 addr
, u32
*data
)
266 if (phy_no
> RTL8366S_PHY_NO_MAX
)
269 if (page
> RTL8366S_PHY_PAGE_MAX
)
272 if (addr
> RTL8366S_PHY_ADDR_MAX
)
275 ret
= rtl8366_smi_write_reg(smi
, RTL8366S_PHY_ACCESS_CTRL_REG
,
276 RTL8366S_PHY_CTRL_READ
);
280 reg
= 0x8000 | (1 << (phy_no
+ RTL8366S_PHY_NO_OFFSET
)) |
281 ((page
<< RTL8366S_PHY_PAGE_OFFSET
) & RTL8366S_PHY_PAGE_MASK
) |
282 (addr
& RTL8366S_PHY_REG_MASK
);
284 ret
= rtl8366_smi_write_reg(smi
, reg
, 0);
288 ret
= rtl8366_smi_read_reg(smi
, RTL8366S_PHY_ACCESS_DATA_REG
, data
);
295 static int rtl8366s_write_phy_reg(struct rtl8366_smi
*smi
,
296 u32 phy_no
, u32 page
, u32 addr
, u32 data
)
301 if (phy_no
> RTL8366S_PHY_NO_MAX
)
304 if (page
> RTL8366S_PHY_PAGE_MAX
)
307 if (addr
> RTL8366S_PHY_ADDR_MAX
)
310 ret
= rtl8366_smi_write_reg(smi
, RTL8366S_PHY_ACCESS_CTRL_REG
,
311 RTL8366S_PHY_CTRL_WRITE
);
315 reg
= 0x8000 | (1 << (phy_no
+ RTL8366S_PHY_NO_OFFSET
)) |
316 ((page
<< RTL8366S_PHY_PAGE_OFFSET
) & RTL8366S_PHY_PAGE_MASK
) |
317 (addr
& RTL8366S_PHY_REG_MASK
);
319 ret
= rtl8366_smi_write_reg(smi
, reg
, data
);
326 static int rtl8366_get_mib_counter(struct rtl8366s
*rtl
, int counter
,
327 int port
, unsigned long long *val
)
329 struct rtl8366_smi
*smi
= &rtl
->smi
;
335 if (port
> RTL8366_NUM_PORTS
|| counter
>= RTL8366S_MIB_COUNT
)
338 addr
= RTL8366S_MIB_COUNTER_BASE
+
339 RTL8366S_MIB_COUNTER_PORT_OFFSET
* (port
) +
340 rtl8366s_mib_counters
[counter
].offset
;
343 * Writing access counter address first
344 * then ASIC will prepare 64bits counter wait for being retrived
346 data
= 0; /* writing data will be discard by ASIC */
347 err
= rtl8366_smi_write_reg(smi
, addr
, data
);
351 /* read MIB control register */
352 err
= rtl8366_smi_read_reg(smi
, RTL8366S_MIB_CTRL_REG
, &data
);
356 if (data
& RTL8366S_MIB_CTRL_BUSY_MASK
)
359 if (data
& RTL8366S_MIB_CTRL_RESET_MASK
)
363 for (i
= rtl8366s_mib_counters
[counter
].length
; i
> 0; i
--) {
364 err
= rtl8366_smi_read_reg(smi
, addr
+ (i
- 1), &data
);
368 mibvalue
= (mibvalue
<< 16) | (data
& 0xFFFF);
375 static int rtl8366s_get_vlan_4k(struct rtl8366s
*rtl
, u32 vid
,
376 struct rtl8366s_vlan_4k
*vlan4k
)
378 struct rtl8366_smi
*smi
= &rtl
->smi
;
383 memset(vlan4k
, '\0', sizeof(struct rtl8366s_vlan_4k
));
386 if (vid
>= RTL8366_NUM_VIDS
)
389 tableaddr
= (u16
*)vlan4k
;
393 err
= rtl8366_smi_write_reg(smi
, RTL8366S_VLAN_TABLE_WRITE_BASE
, data
);
397 /* write table access control word */
398 err
= rtl8366_smi_write_reg(smi
, RTL8366S_TABLE_ACCESS_CTRL_REG
,
399 RTL8366S_TABLE_VLAN_READ_CTRL
);
403 err
= rtl8366_smi_read_reg(smi
, RTL8366S_VLAN_TABLE_READ_BASE
, &data
);
410 err
= rtl8366_smi_read_reg(smi
, RTL8366S_VLAN_TABLE_READ_BASE
+ 1,
421 static int rtl8366s_set_vlan_4k(struct rtl8366s
*rtl
,
422 const struct rtl8366s_vlan_4k
*vlan4k
)
424 struct rtl8366_smi
*smi
= &rtl
->smi
;
429 if (vlan4k
->vid
>= RTL8366_NUM_VIDS
||
430 vlan4k
->member
> RTL8366_PORT_ALL
||
431 vlan4k
->untag
> RTL8366_PORT_ALL
||
432 vlan4k
->fid
> RTL8366S_FIDMAX
)
435 tableaddr
= (u16
*)vlan4k
;
439 err
= rtl8366_smi_write_reg(smi
, RTL8366S_VLAN_TABLE_WRITE_BASE
, data
);
447 err
= rtl8366_smi_write_reg(smi
, RTL8366S_VLAN_TABLE_WRITE_BASE
+ 1,
452 /* write table access control word */
453 err
= rtl8366_smi_write_reg(smi
, RTL8366S_TABLE_ACCESS_CTRL_REG
,
454 RTL8366S_TABLE_VLAN_WRITE_CTRL
);
459 static int rtl8366s_get_vlan_mc(struct rtl8366s
*rtl
, u32 index
,
460 struct rtl8366_vlan_mc
*vlanmc
)
462 struct rtl8366_smi
*smi
= &rtl
->smi
;
463 struct rtl8366s_vlan_mc vlanmc_priv
;
469 memset(vlanmc
, '\0', sizeof(struct rtl8366_vlan_mc
));
471 if (index
>= RTL8366_NUM_VLANS
)
474 tableaddr
= (u16
*)&vlanmc_priv
;
476 addr
= RTL8366S_VLAN_MEMCONF_BASE
+ (index
<< 1);
477 err
= rtl8366_smi_read_reg(smi
, addr
, &data
);
484 addr
= RTL8366S_VLAN_MEMCONF_BASE
+ 1 + (index
<< 1);
485 err
= rtl8366_smi_read_reg(smi
, addr
, &data
);
491 vlanmc
->vid
= vlanmc_priv
.vid
;
492 vlanmc
->priority
= vlanmc_priv
.priority
;
493 vlanmc
->untag
= vlanmc_priv
.untag
;
494 vlanmc
->member
= vlanmc_priv
.member
;
495 vlanmc
->fid
= vlanmc_priv
.fid
;
500 static int rtl8366s_set_vlan_mc(struct rtl8366s
*rtl
, u32 index
,
501 const struct rtl8366_vlan_mc
*vlanmc
)
503 struct rtl8366_smi
*smi
= &rtl
->smi
;
504 struct rtl8366s_vlan_mc vlanmc_priv
;
510 if (index
>= RTL8366_NUM_VLANS
||
511 vlanmc
->vid
>= RTL8366_NUM_VIDS
||
512 vlanmc
->priority
> RTL8366S_PRIORITYMAX
||
513 vlanmc
->member
> RTL8366_PORT_ALL
||
514 vlanmc
->untag
> RTL8366_PORT_ALL
||
515 vlanmc
->fid
> RTL8366S_FIDMAX
)
518 vlanmc_priv
.vid
= vlanmc
->vid
;
519 vlanmc_priv
.priority
= vlanmc
->priority
;
520 vlanmc_priv
.untag
= vlanmc
->untag
;
521 vlanmc_priv
.member
= vlanmc
->member
;
522 vlanmc_priv
.fid
= vlanmc
->fid
;
524 addr
= RTL8366S_VLAN_MEMCONF_BASE
+ (index
<< 1);
526 tableaddr
= (u16
*)&vlanmc_priv
;
529 err
= rtl8366_smi_write_reg(smi
, addr
, data
);
533 addr
= RTL8366S_VLAN_MEMCONF_BASE
+ 1 + (index
<< 1);
538 err
= rtl8366_smi_write_reg(smi
, addr
, data
);
545 static int rtl8366s_get_port_vlan_index(struct rtl8366s
*rtl
, int port
,
548 struct rtl8366_smi
*smi
= &rtl
->smi
;
552 if (port
>= RTL8366_NUM_PORTS
)
555 err
= rtl8366_smi_read_reg(smi
, RTL8366S_PORT_VLAN_CTRL_REG(port
),
560 *val
= (data
>> RTL8366S_PORT_VLAN_CTRL_SHIFT(port
)) &
561 RTL8366S_PORT_VLAN_CTRL_MASK
;
567 static int rtl8366s_get_vlan_port_pvid(struct rtl8366s
*rtl
, int port
,
570 struct rtl8366_vlan_mc vlanmc
;
574 err
= rtl8366s_get_port_vlan_index(rtl
, port
, &index
);
578 err
= rtl8366s_get_vlan_mc(rtl
, index
, &vlanmc
);
586 static int rtl8366s_set_port_vlan_index(struct rtl8366s
*rtl
, int port
,
589 struct rtl8366_smi
*smi
= &rtl
->smi
;
593 if (port
>= RTL8366_NUM_PORTS
|| index
>= RTL8366_NUM_VLANS
)
596 err
= rtl8366_smi_read_reg(smi
, RTL8366S_PORT_VLAN_CTRL_REG(port
),
601 data
&= ~(RTL8366S_PORT_VLAN_CTRL_MASK
<<
602 RTL8366S_PORT_VLAN_CTRL_SHIFT(port
));
603 data
|= (index
& RTL8366S_PORT_VLAN_CTRL_MASK
) <<
604 RTL8366S_PORT_VLAN_CTRL_SHIFT(port
);
606 err
= rtl8366_smi_write_reg(smi
, RTL8366S_PORT_VLAN_CTRL_REG(port
),
611 static int rtl8366s_set_vlan_port_pvid(struct rtl8366s
*rtl
, int port
, int val
)
614 struct rtl8366_vlan_mc vlanmc
;
615 struct rtl8366s_vlan_4k vlan4k
;
617 if (port
>= RTL8366_NUM_PORTS
|| val
>= RTL8366_NUM_VIDS
)
620 /* Updating the 4K entry; lookup it and change the port member set */
621 rtl8366s_get_vlan_4k(rtl
, val
, &vlan4k
);
622 vlan4k
.member
|= ((1 << port
) | RTL8366_PORT_CPU
);
623 vlan4k
.untag
= RTL8366_PORT_ALL_BUT_CPU
;
624 rtl8366s_set_vlan_4k(rtl
, &vlan4k
);
627 * For the 16 entries more work needs to be done. First see if such
628 * VID is already there and change it
630 for (i
= 0; i
< RTL8366_NUM_VLANS
; ++i
) {
631 rtl8366s_get_vlan_mc(rtl
, i
, &vlanmc
);
633 /* Try to find an existing vid and update port member set */
634 if (val
== vlanmc
.vid
) {
635 vlanmc
.member
|= ((1 << port
) | RTL8366_PORT_CPU
);
636 rtl8366s_set_vlan_mc(rtl
, i
, &vlanmc
);
638 /* Now update PVID register settings */
639 rtl8366s_set_port_vlan_index(rtl
, port
, i
);
646 * PVID could not be found from vlan table. Replace unused (one that
647 * has no member ports) with new one
649 for (i
= 0; i
< RTL8366_NUM_VLANS
; ++i
) {
650 rtl8366s_get_vlan_mc(rtl
, i
, &vlanmc
);
653 * See if this vlan member configuration is unused. It is
654 * unused if member set contains no ports or CPU port only
656 if (!vlanmc
.member
|| vlanmc
.member
== RTL8366_PORT_CPU
) {
659 vlanmc
.untag
= RTL8366_PORT_ALL_BUT_CPU
;
660 vlanmc
.member
= ((1 << port
) | RTL8366_PORT_CPU
);
663 rtl8366s_set_vlan_mc(rtl
, i
, &vlanmc
);
665 /* Now update PVID register settings */
666 rtl8366s_set_port_vlan_index(rtl
, port
, i
);
673 "All 16 vlan member configurations are in use\n");
679 static int rtl8366s_vlan_set_vlan(struct rtl8366s
*rtl
, int enable
)
681 struct rtl8366_smi
*smi
= &rtl
->smi
;
684 rtl8366_smi_read_reg(smi
, RTL8366_CHIP_GLOBAL_CTRL_REG
, &data
);
687 data
|= RTL8366_CHIP_CTRL_VLAN
;
689 data
&= ~RTL8366_CHIP_CTRL_VLAN
;
691 return rtl8366_smi_write_reg(smi
, RTL8366_CHIP_GLOBAL_CTRL_REG
, data
);
694 static int rtl8366s_vlan_set_4ktable(struct rtl8366s
*rtl
, int enable
)
696 struct rtl8366_smi
*smi
= &rtl
->smi
;
699 rtl8366_smi_read_reg(smi
, RTL8366S_VLAN_TB_CTRL_REG
, &data
);
706 return rtl8366_smi_write_reg(smi
, RTL8366S_VLAN_TB_CTRL_REG
, data
);
709 static int rtl8366s_reset_vlan(struct rtl8366s
*rtl
)
711 struct rtl8366s_vlan_4k vlan4k
;
712 struct rtl8366_vlan_mc vlanmc
;
716 /* clear 16 VLAN member configuration */
722 for (i
= 0; i
< RTL8366_NUM_VLANS
; i
++) {
723 err
= rtl8366s_set_vlan_mc(rtl
, i
, &vlanmc
);
728 /* Set a default VLAN with vid 1 to 4K table for all ports */
730 vlan4k
.member
= RTL8366_PORT_ALL
;
731 vlan4k
.untag
= RTL8366_PORT_ALL
;
733 err
= rtl8366s_set_vlan_4k(rtl
, &vlan4k
);
737 /* Set all ports PVID to default VLAN */
738 for (i
= 0; i
< RTL8366_NUM_PORTS
; i
++) {
739 err
= rtl8366s_set_vlan_port_pvid(rtl
, i
, 0);
747 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
748 static int rtl8366s_debugfs_open(struct inode
*inode
, struct file
*file
)
750 file
->private_data
= inode
->i_private
;
754 static ssize_t
rtl8366s_read_debugfs_mibs(struct file
*file
,
755 char __user
*user_buf
,
756 size_t count
, loff_t
*ppos
)
758 struct rtl8366s
*rtl
= (struct rtl8366s
*)file
->private_data
;
760 char *buf
= rtl
->buf
;
762 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
, "MIB Counters:\n");
763 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
, "Counter"
765 "Port 0 \t\t Port 1 \t\t Port 2 \t\t Port 3 \t\t "
768 for (i
= 0; i
< 33; ++i
) {
769 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
, "%d:%s ",
770 i
, rtl8366s_mib_counters
[i
].name
);
771 for (j
= 0; j
< RTL8366_NUM_PORTS
; ++j
) {
772 unsigned long long counter
= 0;
774 if (!rtl8366_get_mib_counter(rtl
, i
, j
, &counter
))
775 len
+= snprintf(buf
+ len
,
776 sizeof(rtl
->buf
) - len
,
779 len
+= snprintf(buf
+ len
,
780 sizeof(rtl
->buf
) - len
,
783 if (j
!= RTL8366_NUM_PORTS
- 1) {
784 if (counter
< 100000)
785 len
+= snprintf(buf
+ len
,
786 sizeof(rtl
->buf
) - len
,
789 len
+= snprintf(buf
+ len
,
790 sizeof(rtl
->buf
) - len
,
794 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
, "\n");
797 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
, "\n");
799 return simple_read_from_buffer(user_buf
, count
, ppos
, buf
, len
);
802 static ssize_t
rtl8366s_read_debugfs_vlan(struct file
*file
,
803 char __user
*user_buf
,
804 size_t count
, loff_t
*ppos
)
806 struct rtl8366s
*rtl
= (struct rtl8366s
*)file
->private_data
;
808 char *buf
= rtl
->buf
;
810 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
811 "VLAN Member Config:\n");
812 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
813 "\t id \t vid \t prio \t member \t untag \t fid "
816 for (i
= 0; i
< RTL8366_NUM_VLANS
; ++i
) {
817 struct rtl8366_vlan_mc vlanmc
;
819 rtl8366s_get_vlan_mc(rtl
, i
, &vlanmc
);
821 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
822 "\t[%d] \t %d \t %d \t 0x%04x \t 0x%04x \t %d "
823 "\t", i
, vlanmc
.vid
, vlanmc
.priority
,
824 vlanmc
.member
, vlanmc
.untag
, vlanmc
.fid
);
826 for (j
= 0; j
< RTL8366_NUM_PORTS
; ++j
) {
828 if (!rtl8366s_get_port_vlan_index(rtl
, j
, &index
)) {
830 len
+= snprintf(buf
+ len
,
831 sizeof(rtl
->buf
) - len
,
835 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
, "\n");
838 return simple_read_from_buffer(user_buf
, count
, ppos
, buf
, len
);
841 static ssize_t
rtl8366s_read_debugfs_reg(struct file
*file
,
842 char __user
*user_buf
,
843 size_t count
, loff_t
*ppos
)
845 struct rtl8366s
*rtl
= (struct rtl8366s
*)file
->private_data
;
846 struct rtl8366_smi
*smi
= &rtl
->smi
;
847 u32 t
, reg
= g_dbg_reg
;
849 char *buf
= rtl
->buf
;
851 memset(buf
, '\0', sizeof(rtl
->buf
));
853 err
= rtl8366_smi_read_reg(smi
, reg
, &t
);
855 len
+= snprintf(buf
, sizeof(rtl
->buf
),
856 "Read failed (reg: 0x%04x)\n", reg
);
857 return simple_read_from_buffer(user_buf
, count
, ppos
, buf
, len
);
860 len
+= snprintf(buf
, sizeof(rtl
->buf
), "reg = 0x%04x, val = 0x%04x\n",
863 return simple_read_from_buffer(user_buf
, count
, ppos
, buf
, len
);
866 static ssize_t
rtl8366s_write_debugfs_reg(struct file
*file
,
867 const char __user
*user_buf
,
868 size_t count
, loff_t
*ppos
)
870 struct rtl8366s
*rtl
= (struct rtl8366s
*)file
->private_data
;
871 struct rtl8366_smi
*smi
= &rtl
->smi
;
876 char *buf
= rtl
->buf
;
878 len
= min(count
, sizeof(rtl
->buf
) - 1);
879 if (copy_from_user(buf
, user_buf
, len
)) {
880 dev_err(rtl
->parent
, "copy from user failed\n");
885 if (len
> 0 && buf
[len
- 1] == '\n')
889 if (strict_strtoul(buf
, 16, &data
)) {
890 dev_err(rtl
->parent
, "Invalid reg value %s\n", buf
);
892 err
= rtl8366_smi_write_reg(smi
, reg
, data
);
895 "writing reg 0x%04x val 0x%04lx failed\n",
903 static const struct file_operations fops_rtl8366s_regs
= {
904 .read
= rtl8366s_read_debugfs_reg
,
905 .write
= rtl8366s_write_debugfs_reg
,
906 .open
= rtl8366s_debugfs_open
,
910 static const struct file_operations fops_rtl8366s_vlan
= {
911 .read
= rtl8366s_read_debugfs_vlan
,
912 .open
= rtl8366s_debugfs_open
,
916 static const struct file_operations fops_rtl8366s_mibs
= {
917 .read
= rtl8366s_read_debugfs_mibs
,
918 .open
= rtl8366s_debugfs_open
,
922 static void rtl8366s_debugfs_init(struct rtl8366s
*rtl
)
927 if (!rtl
->debugfs_root
)
928 rtl
->debugfs_root
= debugfs_create_dir("rtl8366s", NULL
);
930 if (!rtl
->debugfs_root
) {
931 dev_err(rtl
->parent
, "Unable to create debugfs dir\n");
934 root
= rtl
->debugfs_root
;
936 node
= debugfs_create_x16("reg", S_IRUGO
| S_IWUSR
, root
, &g_dbg_reg
);
938 dev_err(rtl
->parent
, "Creating debugfs file '%s' failed\n",
943 node
= debugfs_create_file("val", S_IRUGO
| S_IWUSR
, root
, rtl
,
944 &fops_rtl8366s_regs
);
946 dev_err(rtl
->parent
, "Creating debugfs file '%s' failed\n",
951 node
= debugfs_create_file("vlan", S_IRUSR
, root
, rtl
,
952 &fops_rtl8366s_vlan
);
954 dev_err(rtl
->parent
, "Creating debugfs file '%s' failed\n",
959 node
= debugfs_create_file("mibs", S_IRUSR
, root
, rtl
,
960 &fops_rtl8366s_mibs
);
962 dev_err(rtl
->parent
, "Creating debugfs file '%s' failed\n",
968 static void rtl8366s_debugfs_remove(struct rtl8366s
*rtl
)
970 if (rtl
->debugfs_root
) {
971 debugfs_remove_recursive(rtl
->debugfs_root
);
972 rtl
->debugfs_root
= NULL
;
977 static inline void rtl8366s_debugfs_init(struct rtl8366s
*rtl
) {}
978 static inline void rtl8366s_debugfs_remove(struct rtl8366s
*rtl
) {}
979 #endif /* CONFIG_RTL8366S_PHY_DEBUG_FS */
981 static int rtl8366s_sw_reset_mibs(struct switch_dev
*dev
,
982 const struct switch_attr
*attr
,
983 struct switch_val
*val
)
985 struct rtl8366s
*rtl
= sw_to_rtl8366s(dev
);
986 struct rtl8366_smi
*smi
= &rtl
->smi
;
989 if (val
->value
.i
== 1) {
990 rtl8366_smi_read_reg(smi
, RTL8366S_MIB_CTRL_REG
, &data
);
992 rtl8366_smi_write_reg(smi
, RTL8366S_MIB_CTRL_REG
, data
);
998 static int rtl8366s_sw_get_vlan_enable(struct switch_dev
*dev
,
999 const struct switch_attr
*attr
,
1000 struct switch_val
*val
)
1002 struct rtl8366s
*rtl
= sw_to_rtl8366s(dev
);
1003 struct rtl8366_smi
*smi
= &rtl
->smi
;
1006 if (attr
->ofs
== 1) {
1007 rtl8366_smi_read_reg(smi
, RTL8366_CHIP_GLOBAL_CTRL_REG
, &data
);
1009 if (data
& RTL8366_CHIP_CTRL_VLAN
)
1013 } else if (attr
->ofs
== 2) {
1014 rtl8366_smi_read_reg(smi
, RTL8366S_VLAN_TB_CTRL_REG
, &data
);
1025 static int rtl8366s_sw_get_blinkrate(struct switch_dev
*dev
,
1026 const struct switch_attr
*attr
,
1027 struct switch_val
*val
)
1029 struct rtl8366s
*rtl
= sw_to_rtl8366s(dev
);
1030 struct rtl8366_smi
*smi
= &rtl
->smi
;
1033 rtl8366_smi_read_reg(smi
, RTL8366_LED_BLINKRATE_REG
, &data
);
1035 val
->value
.i
= (data
& (RTL8366_LED_BLINKRATE_MASK
));
1040 static int rtl8366s_sw_set_blinkrate(struct switch_dev
*dev
,
1041 const struct switch_attr
*attr
,
1042 struct switch_val
*val
)
1044 struct rtl8366s
*rtl
= sw_to_rtl8366s(dev
);
1045 struct rtl8366_smi
*smi
= &rtl
->smi
;
1048 if (val
->value
.i
>= 6)
1051 rtl8366_smi_read_reg(smi
, RTL8366_LED_BLINKRATE_REG
, &data
);
1053 data
&= ~RTL8366_LED_BLINKRATE_MASK
;
1054 data
|= val
->value
.i
;
1056 rtl8366_smi_write_reg(smi
, RTL8366_LED_BLINKRATE_REG
, data
);
1061 static int rtl8366s_sw_set_vlan_enable(struct switch_dev
*dev
,
1062 const struct switch_attr
*attr
,
1063 struct switch_val
*val
)
1065 struct rtl8366s
*rtl
= sw_to_rtl8366s(dev
);
1068 return rtl8366s_vlan_set_vlan(rtl
, val
->value
.i
);
1070 return rtl8366s_vlan_set_4ktable(rtl
, val
->value
.i
);
1073 static const char *rtl8366s_speed_str(unsigned speed
)
1087 static int rtl8366s_sw_get_port_link(struct switch_dev
*dev
,
1088 const struct switch_attr
*attr
,
1089 struct switch_val
*val
)
1091 struct rtl8366s
*rtl
= sw_to_rtl8366s(dev
);
1092 struct rtl8366_smi
*smi
= &rtl
->smi
;
1093 u32 len
= 0, data
= 0;
1095 if (val
->port_vlan
>= RTL8366_NUM_PORTS
)
1098 memset(rtl
->buf
, '\0', sizeof(rtl
->buf
));
1099 rtl8366_smi_read_reg(smi
, RTL8366S_PORT_LINK_STATUS_BASE
+
1100 (val
->port_vlan
/ 2), &data
);
1102 if (val
->port_vlan
% 2)
1105 if (data
& RTL8366S_PORT_STATUS_LINK_MASK
) {
1106 len
= snprintf(rtl
->buf
, sizeof(rtl
->buf
),
1107 "port:%d link:up speed:%s %s-duplex %s%s%s",
1109 rtl8366s_speed_str(data
&
1110 RTL8366S_PORT_STATUS_SPEED_MASK
),
1111 (data
& RTL8366S_PORT_STATUS_DUPLEX_MASK
) ?
1113 (data
& RTL8366S_PORT_STATUS_TXPAUSE_MASK
) ?
1115 (data
& RTL8366S_PORT_STATUS_RXPAUSE_MASK
) ?
1117 (data
& RTL8366S_PORT_STATUS_AN_MASK
) ?
1120 len
= snprintf(rtl
->buf
, sizeof(rtl
->buf
), "port:%d link: down",
1124 val
->value
.s
= rtl
->buf
;
1130 static int rtl8366s_sw_get_vlan_info(struct switch_dev
*dev
,
1131 const struct switch_attr
*attr
,
1132 struct switch_val
*val
)
1136 struct rtl8366_vlan_mc vlanmc
;
1137 struct rtl8366s_vlan_4k vlan4k
;
1138 struct rtl8366s
*rtl
= sw_to_rtl8366s(dev
);
1139 char *buf
= rtl
->buf
;
1141 if (val
->port_vlan
== 0 || val
->port_vlan
>= RTL8366_NUM_VLANS
)
1144 memset(buf
, '\0', sizeof(rtl
->buf
));
1146 rtl8366s_get_vlan_mc(rtl
, val
->port_vlan
, &vlanmc
);
1147 rtl8366s_get_vlan_4k(rtl
, vlanmc
.vid
, &vlan4k
);
1149 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
, "VLAN %d: Ports: ",
1152 for (i
= 0; i
< RTL8366_NUM_PORTS
; ++i
) {
1154 if (!rtl8366s_get_port_vlan_index(rtl
, i
, &index
) &&
1155 index
== val
->port_vlan
)
1156 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
1159 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
, "\n");
1161 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
1162 "\t\t vid \t prio \t member \t untag \t fid\n");
1163 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
, "\tMC:\t");
1164 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
1165 "%d \t %d \t 0x%04x \t 0x%04x \t %d\n",
1166 vlanmc
.vid
, vlanmc
.priority
, vlanmc
.member
,
1167 vlanmc
.untag
, vlanmc
.fid
);
1168 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
, "\t4K:\t");
1169 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
1170 "%d \t \t 0x%04x \t 0x%04x \t %d",
1171 vlan4k
.vid
, vlan4k
.member
, vlan4k
.untag
, vlan4k
.fid
);
1179 static int rtl8366s_sw_set_port_led(struct switch_dev
*dev
,
1180 const struct switch_attr
*attr
,
1181 struct switch_val
*val
)
1183 struct rtl8366s
*rtl
= sw_to_rtl8366s(dev
);
1184 struct rtl8366_smi
*smi
= &rtl
->smi
;
1187 if (val
->port_vlan
>= RTL8366_NUM_PORTS
||
1188 (1 << val
->port_vlan
) == RTL8366_PORT_UNKNOWN
)
1191 if (val
->port_vlan
== RTL8366_PORT_NUM_CPU
) {
1192 rtl8366_smi_read_reg(smi
, RTL8366_LED_BLINKRATE_REG
, &data
);
1193 data
= (data
& (~(0xF << 4))) | (val
->value
.i
<< 4);
1194 rtl8366_smi_write_reg(smi
, RTL8366_LED_BLINKRATE_REG
, data
);
1196 rtl8366_smi_read_reg(smi
, RTL8366_LED_CTRL_REG
, &data
);
1197 data
= (data
& (~(0xF << (val
->port_vlan
* 4)))) |
1198 (val
->value
.i
<< (val
->port_vlan
* 4));
1199 rtl8366_smi_write_reg(smi
, RTL8366_LED_CTRL_REG
, data
);
1205 static int rtl8366s_sw_get_port_led(struct switch_dev
*dev
,
1206 const struct switch_attr
*attr
,
1207 struct switch_val
*val
)
1209 struct rtl8366s
*rtl
= sw_to_rtl8366s(dev
);
1210 struct rtl8366_smi
*smi
= &rtl
->smi
;
1213 if (val
->port_vlan
>= RTL8366_NUM_LEDGROUPS
)
1216 rtl8366_smi_read_reg(smi
, RTL8366_LED_CTRL_REG
, &data
);
1217 val
->value
.i
= (data
>> (val
->port_vlan
* 4)) & 0x000F;
1222 static int rtl8366s_sw_reset_port_mibs(struct switch_dev
*dev
,
1223 const struct switch_attr
*attr
,
1224 struct switch_val
*val
)
1226 struct rtl8366s
*rtl
= sw_to_rtl8366s(dev
);
1227 struct rtl8366_smi
*smi
= &rtl
->smi
;
1230 if (val
->port_vlan
>= RTL8366_NUM_PORTS
)
1233 rtl8366_smi_read_reg(smi
, RTL8366S_MIB_CTRL_REG
, &data
);
1234 data
|= (1 << (val
->port_vlan
+ 3));
1235 rtl8366_smi_write_reg(smi
, RTL8366S_MIB_CTRL_REG
, data
);
1240 static int rtl8366s_sw_get_port_mib(struct switch_dev
*dev
,
1241 const struct switch_attr
*attr
,
1242 struct switch_val
*val
)
1244 struct rtl8366s
*rtl
= sw_to_rtl8366s(dev
);
1246 unsigned long long counter
= 0;
1247 char *buf
= rtl
->buf
;
1249 if (val
->port_vlan
>= RTL8366_NUM_PORTS
)
1252 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
1253 "Port %d MIB counters\n",
1256 for (i
= 0; i
< RTL8366S_MIB_COUNT
; ++i
) {
1257 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
1258 "%d:%s\t", i
, rtl8366s_mib_counters
[i
].name
);
1259 if (!rtl8366_get_mib_counter(rtl
, i
, val
->port_vlan
, &counter
))
1260 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
1261 "[%llu]\n", counter
);
1263 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
1272 static int rtl8366s_sw_get_vlan_ports(struct switch_dev
*dev
,
1273 struct switch_val
*val
)
1275 struct rtl8366_vlan_mc vlanmc
;
1276 struct rtl8366s
*rtl
= sw_to_rtl8366s(dev
);
1277 struct switch_port
*port
;
1280 if (val
->port_vlan
== 0 || val
->port_vlan
>= RTL8366_NUM_VLANS
)
1283 rtl8366s_get_vlan_mc(rtl
, val
->port_vlan
, &vlanmc
);
1285 port
= &val
->value
.ports
[0];
1287 for (i
= 0; i
< RTL8366_NUM_PORTS
; i
++) {
1288 if (!(vlanmc
.member
& BIT(i
)))
1292 port
->flags
= (vlanmc
.untag
& BIT(i
)) ?
1293 0 : BIT(SWITCH_PORT_FLAG_TAGGED
);
1300 static int rtl8366s_sw_set_vlan_ports(struct switch_dev
*dev
,
1301 struct switch_val
*val
)
1303 struct rtl8366_vlan_mc vlanmc
;
1304 struct rtl8366s_vlan_4k vlan4k
;
1305 struct rtl8366s
*rtl
= sw_to_rtl8366s(dev
);
1306 struct switch_port
*port
;
1309 if (val
->port_vlan
== 0 || val
->port_vlan
>= RTL8366_NUM_VLANS
)
1312 rtl8366s_get_vlan_mc(rtl
, val
->port_vlan
, &vlanmc
);
1313 rtl8366s_get_vlan_4k(rtl
, vlanmc
.vid
, &vlan4k
);
1318 port
= &val
->value
.ports
[0];
1319 for (i
= 0; i
< val
->len
; i
++, port
++) {
1320 vlanmc
.member
|= BIT(port
->id
);
1322 if (!(port
->flags
& BIT(SWITCH_PORT_FLAG_TAGGED
)))
1323 vlanmc
.untag
|= BIT(port
->id
);
1326 vlan4k
.member
= vlanmc
.member
;
1327 vlan4k
.untag
= vlanmc
.untag
;
1329 rtl8366s_set_vlan_mc(rtl
, val
->port_vlan
, &vlanmc
);
1330 rtl8366s_set_vlan_4k(rtl
, &vlan4k
);
1334 static int rtl8366s_sw_get_port_pvid(struct switch_dev
*dev
, int port
, int *val
)
1336 struct rtl8366s
*rtl
= sw_to_rtl8366s(dev
);
1337 return rtl8366s_get_vlan_port_pvid(rtl
, port
, val
);
1340 static int rtl8366s_sw_set_port_pvid(struct switch_dev
*dev
, int port
, int val
)
1342 struct rtl8366s
*rtl
= sw_to_rtl8366s(dev
);
1343 return rtl8366s_set_vlan_port_pvid(rtl
, port
, val
);
1346 static int rtl8366s_sw_reset_switch(struct switch_dev
*dev
)
1348 struct rtl8366s
*rtl
= sw_to_rtl8366s(dev
);
1351 err
= rtl8366s_reset_chip(rtl
);
1355 return rtl8366s_reset_vlan(rtl
);
1358 static struct switch_attr rtl8366s_globals
[] = {
1360 .type
= SWITCH_TYPE_INT
,
1361 .name
= "enable_vlan",
1362 .description
= "Enable VLAN mode",
1363 .set
= rtl8366s_sw_set_vlan_enable
,
1364 .get
= rtl8366s_sw_get_vlan_enable
,
1368 .type
= SWITCH_TYPE_INT
,
1369 .name
= "enable_vlan4k",
1370 .description
= "Enable VLAN 4K mode",
1371 .set
= rtl8366s_sw_set_vlan_enable
,
1372 .get
= rtl8366s_sw_get_vlan_enable
,
1376 .type
= SWITCH_TYPE_INT
,
1377 .name
= "reset_mibs",
1378 .description
= "Reset all MIB counters",
1379 .set
= rtl8366s_sw_reset_mibs
,
1383 .type
= SWITCH_TYPE_INT
,
1384 .name
= "blinkrate",
1385 .description
= "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1386 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1387 .set
= rtl8366s_sw_set_blinkrate
,
1388 .get
= rtl8366s_sw_get_blinkrate
,
1393 static struct switch_attr rtl8366s_port
[] = {
1395 .type
= SWITCH_TYPE_STRING
,
1397 .description
= "Get port link information",
1400 .get
= rtl8366s_sw_get_port_link
,
1402 .type
= SWITCH_TYPE_INT
,
1403 .name
= "reset_mib",
1404 .description
= "Reset single port MIB counters",
1406 .set
= rtl8366s_sw_reset_port_mibs
,
1409 .type
= SWITCH_TYPE_STRING
,
1411 .description
= "Get MIB counters for port",
1414 .get
= rtl8366s_sw_get_port_mib
,
1416 .type
= SWITCH_TYPE_INT
,
1418 .description
= "Get/Set port group (0 - 3) led mode (0 - 15)",
1420 .set
= rtl8366s_sw_set_port_led
,
1421 .get
= rtl8366s_sw_get_port_led
,
1425 static struct switch_attr rtl8366s_vlan
[] = {
1427 .type
= SWITCH_TYPE_STRING
,
1429 .description
= "Get vlan information",
1432 .get
= rtl8366s_sw_get_vlan_info
,
1437 static struct switch_dev rtl8366_switch_dev
= {
1439 .cpu_port
= RTL8366_PORT_NUM_CPU
,
1440 .ports
= RTL8366_NUM_PORTS
,
1441 .vlans
= RTL8366_NUM_VLANS
,
1443 .attr
= rtl8366s_globals
,
1444 .n_attr
= ARRAY_SIZE(rtl8366s_globals
),
1447 .attr
= rtl8366s_port
,
1448 .n_attr
= ARRAY_SIZE(rtl8366s_port
),
1451 .attr
= rtl8366s_vlan
,
1452 .n_attr
= ARRAY_SIZE(rtl8366s_vlan
),
1455 .get_vlan_ports
= rtl8366s_sw_get_vlan_ports
,
1456 .set_vlan_ports
= rtl8366s_sw_set_vlan_ports
,
1457 .get_port_pvid
= rtl8366s_sw_get_port_pvid
,
1458 .set_port_pvid
= rtl8366s_sw_set_port_pvid
,
1459 .reset_switch
= rtl8366s_sw_reset_switch
,
1462 static int rtl8366s_switch_init(struct rtl8366s
*rtl
)
1464 struct switch_dev
*dev
= &rtl
->dev
;
1467 memcpy(dev
, &rtl8366_switch_dev
, sizeof(struct switch_dev
));
1469 dev
->devname
= dev_name(rtl
->parent
);
1471 err
= register_switch(dev
, NULL
);
1473 dev_err(rtl
->parent
, "switch registration failed\n");
1478 static void rtl8366s_switch_cleanup(struct rtl8366s
*rtl
)
1480 unregister_switch(&rtl
->dev
);
1483 static int rtl8366s_mii_read(struct mii_bus
*bus
, int addr
, int reg
)
1485 struct rtl8366_smi
*smi
= bus
->priv
;
1489 err
= rtl8366s_read_phy_reg(smi
, addr
, 0, reg
, &val
);
1496 static int rtl8366s_mii_write(struct mii_bus
*bus
, int addr
, int reg
, u16 val
)
1498 struct rtl8366_smi
*smi
= bus
->priv
;
1502 err
= rtl8366s_write_phy_reg(smi
, addr
, 0, reg
, val
);
1504 (void) rtl8366s_read_phy_reg(smi
, addr
, 0, reg
, &t
);
1509 static int rtl8366s_mii_bus_match(struct mii_bus
*bus
)
1511 return (bus
->read
== rtl8366s_mii_read
&&
1512 bus
->write
== rtl8366s_mii_write
);
1515 static int rtl8366s_setup(struct rtl8366s
*rtl
)
1519 ret
= rtl8366s_reset_chip(rtl
);
1523 rtl8366s_debugfs_init(rtl
);
1527 static int rtl8366s_detect(struct rtl8366_smi
*smi
)
1533 ret
= rtl8366_smi_read_reg(smi
, RTL8366S_CHIP_ID_REG
, &chip_id
);
1535 dev_err(smi
->parent
, "unable to read chip id\n");
1540 case RTL8366S_CHIP_ID_8366
:
1543 dev_err(smi
->parent
, "unknown chip id (%04x)\n", chip_id
);
1547 ret
= rtl8366_smi_read_reg(smi
, RTL8366S_CHIP_VERSION_CTRL_REG
,
1550 dev_err(smi
->parent
, "unable to read chip version\n");
1554 dev_info(smi
->parent
, "RTL%04x ver. %u chip found\n",
1555 chip_id
, chip_ver
& RTL8366S_CHIP_VERSION_MASK
);
1560 static struct rtl8366_smi_ops rtl8366s_smi_ops
= {
1561 .detect
= rtl8366s_detect
,
1562 .mii_read
= rtl8366s_mii_read
,
1563 .mii_write
= rtl8366s_mii_write
,
1566 static int __init
rtl8366s_probe(struct platform_device
*pdev
)
1568 static int rtl8366_smi_version_printed
;
1569 struct rtl8366s_platform_data
*pdata
;
1570 struct rtl8366s
*rtl
;
1571 struct rtl8366_smi
*smi
;
1574 if (!rtl8366_smi_version_printed
++)
1575 printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1576 " version " RTL8366S_DRIVER_VER
"\n");
1578 pdata
= pdev
->dev
.platform_data
;
1580 dev_err(&pdev
->dev
, "no platform data specified\n");
1585 rtl
= kzalloc(sizeof(*rtl
), GFP_KERNEL
);
1587 dev_err(&pdev
->dev
, "no memory for private data\n");
1592 rtl
->parent
= &pdev
->dev
;
1595 smi
->parent
= &pdev
->dev
;
1596 smi
->gpio_sda
= pdata
->gpio_sda
;
1597 smi
->gpio_sck
= pdata
->gpio_sck
;
1598 smi
->ops
= &rtl8366s_smi_ops
;
1600 err
= rtl8366_smi_init(smi
);
1604 platform_set_drvdata(pdev
, rtl
);
1606 err
= rtl8366s_setup(rtl
);
1608 goto err_clear_drvdata
;
1610 err
= rtl8366s_switch_init(rtl
);
1612 goto err_clear_drvdata
;
1617 platform_set_drvdata(pdev
, NULL
);
1618 rtl8366_smi_cleanup(smi
);
1625 static int rtl8366s_phy_config_init(struct phy_device
*phydev
)
1627 if (!rtl8366s_mii_bus_match(phydev
->bus
))
1633 static int rtl8366s_phy_config_aneg(struct phy_device
*phydev
)
1638 static struct phy_driver rtl8366s_phy_driver
= {
1639 .phy_id
= 0x001cc960,
1640 .name
= "Realtek RTL8366S",
1641 .phy_id_mask
= 0x1ffffff0,
1642 .features
= PHY_GBIT_FEATURES
,
1643 .config_aneg
= rtl8366s_phy_config_aneg
,
1644 .config_init
= rtl8366s_phy_config_init
,
1645 .read_status
= genphy_read_status
,
1647 .owner
= THIS_MODULE
,
1651 static int __devexit
rtl8366s_remove(struct platform_device
*pdev
)
1653 struct rtl8366s
*rtl
= platform_get_drvdata(pdev
);
1656 rtl8366s_switch_cleanup(rtl
);
1657 rtl8366s_debugfs_remove(rtl
);
1658 platform_set_drvdata(pdev
, NULL
);
1659 rtl8366_smi_cleanup(&rtl
->smi
);
1666 static struct platform_driver rtl8366s_driver
= {
1668 .name
= RTL8366S_DRIVER_NAME
,
1669 .owner
= THIS_MODULE
,
1671 .probe
= rtl8366s_probe
,
1672 .remove
= __devexit_p(rtl8366s_remove
),
1675 static int __init
rtl8366s_module_init(void)
1678 ret
= platform_driver_register(&rtl8366s_driver
);
1682 ret
= phy_driver_register(&rtl8366s_phy_driver
);
1684 goto err_platform_unregister
;
1688 err_platform_unregister
:
1689 platform_driver_unregister(&rtl8366s_driver
);
1692 module_init(rtl8366s_module_init
);
1694 static void __exit
rtl8366s_module_exit(void)
1696 phy_driver_unregister(&rtl8366s_phy_driver
);
1697 platform_driver_unregister(&rtl8366s_driver
);
1699 module_exit(rtl8366s_module_exit
);
1701 MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC
);
1702 MODULE_VERSION(RTL8366S_DRIVER_VER
);
1703 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1704 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1705 MODULE_LICENSE("GPL v2");
1706 MODULE_ALIAS("platform:" RTL8366S_DRIVER_NAME
);