target/linux/hifiveu/patches-5.10/0006-dt-bindings-riscv-Update-DT-binding-docs-to-support-.patch

   1 From 34d032292a2b6db16fc60e7c6706b1b508c2d932 Mon Sep 17 00:00:00 2001
   2 From: Yash Shah <yash.shah@sifive.com>
   3 Date: Tue, 8 Dec 2020 10:25:33 +0530
   4 Subject: [PATCH 06/29] dt-bindings: riscv: Update DT binding docs to support
   5  SiFive FU740 SoC
   6
   7 Add new compatible strings in cpus.yaml to support the E71 and U74 CPU
   8 cores ("harts") that are present on FU740-C000 SoC.
   9
  10 Signed-off-by: Yash Shah <yash.shah@sifive.com>
  11 Reviewed-by: Rob Herring <robh@kernel.org>
  12 Reviewed-by: Bin Meng <bin.meng@windriver.com>
  13 ---
  14  Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++
  15  1 file changed, 6 insertions(+)
  16
  17 diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
  18 index c6925e0..eb6843f 100644
  19 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
  20 +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
  21 @@ -28,11 +28,17 @@ properties:
  22        - items:
  23            - enum:
  24                - sifive,rocket0
  25 +              - sifive,bullet0
  26                - sifive,e5
  27 +              - sifive,e7
  28                - sifive,e51
  29 +              - sifive,e71
  30                - sifive,u54-mc
  31 +              - sifive,u74-mc
  32                - sifive,u54
  33 +              - sifive,u74
  34                - sifive,u5
  35 +              - sifive,u7
  36            - const: riscv
  37        - const: riscv    # Simulator only
  38      description:
  39 --
  40 2.7.4
  41