target/linux/hifiveu/patches-5.10/0012-riscv-dts-add-initial-support-for-the-SiFive-FU740-C.patch

   1 From 7d2e730f1281b5530e55ebca1b0d9165e0298c00 Mon Sep 17 00:00:00 2001
   2 From: Yash Shah <yash.shah@sifive.com>
   3 Date: Tue, 8 Dec 2020 10:25:39 +0530
   4 Subject: [PATCH 12/29] riscv: dts: add initial support for the SiFive
   5  FU740-C000 SoC
   6
   7 Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is built
   8 around the SiFIve U7 Core Complex and a TileLink interconnect.
   9
  10 This file is expected to grow as more device drivers are added to the
  11 kernel.
  12
  13 Signed-off-by: Yash Shah <yash.shah@sifive.com>
  14 ---
  15  arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293 +++++++++++++++++++++++++++++
  16  1 file changed, 293 insertions(+)
  17  create mode 100644 arch/riscv/boot/dts/sifive/fu740-c000.dtsi
  18
  19 diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
  20 new file mode 100644
  21 index 00000000..eeb4f8c3
  22 --- /dev/null
  23 +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
  24 @@ -0,0 +1,293 @@
  25 +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
  26 +/* Copyright (c) 2020 SiFive, Inc */
  27 +
  28 +/dts-v1/;
  29 +
  30 +#include <dt-bindings/clock/sifive-fu740-prci.h>
  31 +
  32 +/ {
  33 +       #address-cells = <2>;
  34 +       #size-cells = <2>;
  35 +       compatible = "sifive,fu740-c000", "sifive,fu740";
  36 +
  37 +       aliases {
  38 +               serial0 = &uart0;
  39 +               serial1 = &uart1;
  40 +               ethernet0 = &eth0;
  41 +       };
  42 +
  43 +       chosen {
  44 +       };
  45 +
  46 +       cpus {
  47 +               #address-cells = <1>;
  48 +               #size-cells = <0>;
  49 +               cpu0: cpu@0 {
  50 +                       compatible = "sifive,bullet0", "riscv";
  51 +                       device_type = "cpu";
  52 +                       i-cache-block-size = <64>;
  53 +                       i-cache-sets = <128>;
  54 +                       i-cache-size = <16384>;
  55 +                       next-level-cache = <&ccache>;
  56 +                       reg = <0x0>;
  57 +                       riscv,isa = "rv64imac";
  58 +                       status = "disabled";
  59 +                       cpu0_intc: interrupt-controller {
  60 +                               #interrupt-cells = <1>;
  61 +                               compatible = "riscv,cpu-intc";
  62 +                               interrupt-controller;
  63 +                       };
  64 +               };
  65 +               cpu1: cpu@1 {
  66 +                       compatible = "sifive,bullet0", "riscv";
  67 +                       d-cache-block-size = <64>;
  68 +                       d-cache-sets = <64>;
  69 +                       d-cache-size = <32768>;
  70 +                       d-tlb-sets = <1>;
  71 +                       d-tlb-size = <40>;
  72 +                       device_type = "cpu";
  73 +                       i-cache-block-size = <64>;
  74 +                       i-cache-sets = <128>;
  75 +                       i-cache-size = <32768>;
  76 +                       i-tlb-sets = <1>;
  77 +                       i-tlb-size = <40>;
  78 +                       mmu-type = "riscv,sv39";
  79 +                       next-level-cache = <&ccache>;
  80 +                       reg = <0x1>;
  81 +                       riscv,isa = "rv64imafdc";
  82 +                       tlb-split;
  83 +                       cpu1_intc: interrupt-controller {
  84 +                               #interrupt-cells = <1>;
  85 +                               compatible = "riscv,cpu-intc";
  86 +                               interrupt-controller;
  87 +                       };
  88 +               };
  89 +               cpu2: cpu@2 {
  90 +                       compatible = "sifive,bullet0", "riscv";
  91 +                       d-cache-block-size = <64>;
  92 +                       d-cache-sets = <64>;
  93 +                       d-cache-size = <32768>;
  94 +                       d-tlb-sets = <1>;
  95 +                       d-tlb-size = <40>;
  96 +                       device_type = "cpu";
  97 +                       i-cache-block-size = <64>;
  98 +                       i-cache-sets = <128>;
  99 +                       i-cache-size = <32768>;
 100 +                       i-tlb-sets = <1>;
 101 +                       i-tlb-size = <40>;
 102 +                       mmu-type = "riscv,sv39";
 103 +                       next-level-cache = <&ccache>;
 104 +                       reg = <0x2>;
 105 +                       riscv,isa = "rv64imafdc";
 106 +                       tlb-split;
 107 +                       cpu2_intc: interrupt-controller {
 108 +                               #interrupt-cells = <1>;
 109 +                               compatible = "riscv,cpu-intc";
 110 +                               interrupt-controller;
 111 +                       };
 112 +               };
 113 +               cpu3: cpu@3 {
 114 +                       compatible = "sifive,bullet0", "riscv";
 115 +                       d-cache-block-size = <64>;
 116 +                       d-cache-sets = <64>;
 117 +                       d-cache-size = <32768>;
 118 +                       d-tlb-sets = <1>;
 119 +                       d-tlb-size = <40>;
 120 +                       device_type = "cpu";
 121 +                       i-cache-block-size = <64>;
 122 +                       i-cache-sets = <128>;
 123 +                       i-cache-size = <32768>;
 124 +                       i-tlb-sets = <1>;
 125 +                       i-tlb-size = <40>;
 126 +                       mmu-type = "riscv,sv39";
 127 +                       next-level-cache = <&ccache>;
 128 +                       reg = <0x3>;
 129 +                       riscv,isa = "rv64imafdc";
 130 +                       tlb-split;
 131 +                       cpu3_intc: interrupt-controller {
 132 +                               #interrupt-cells = <1>;
 133 +                               compatible = "riscv,cpu-intc";
 134 +                               interrupt-controller;
 135 +                       };
 136 +               };
 137 +               cpu4: cpu@4 {
 138 +                       compatible = "sifive,bullet0", "riscv";
 139 +                       d-cache-block-size = <64>;
 140 +                       d-cache-sets = <64>;
 141 +                       d-cache-size = <32768>;
 142 +                       d-tlb-sets = <1>;
 143 +                       d-tlb-size = <40>;
 144 +                       device_type = "cpu";
 145 +                       i-cache-block-size = <64>;
 146 +                       i-cache-sets = <128>;
 147 +                       i-cache-size = <32768>;
 148 +                       i-tlb-sets = <1>;
 149 +                       i-tlb-size = <40>;
 150 +                       mmu-type = "riscv,sv39";
 151 +                       next-level-cache = <&ccache>;
 152 +                       reg = <0x4>;
 153 +                       riscv,isa = "rv64imafdc";
 154 +                       tlb-split;
 155 +                       cpu4_intc: interrupt-controller {
 156 +                               #interrupt-cells = <1>;
 157 +                               compatible = "riscv,cpu-intc";
 158 +                               interrupt-controller;
 159 +                       };
 160 +               };
 161 +       };
 162 +       soc {
 163 +               #address-cells = <2>;
 164 +               #size-cells = <2>;
 165 +               compatible = "simple-bus";
 166 +               ranges;
 167 +               plic0: interrupt-controller@c000000 {
 168 +                       #interrupt-cells = <1>;
 169 +                       #address-cells = <0>;
 170 +                       compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
 171 +                       reg = <0x0 0xc000000 0x0 0x4000000>;
 172 +                       riscv,ndev = <69>;
 173 +                       interrupt-controller;
 174 +                       interrupts-extended = <
 175 +                               &cpu0_intc 0xffffffff
 176 +                               &cpu1_intc 0xffffffff &cpu1_intc 9
 177 +                               &cpu2_intc 0xffffffff &cpu2_intc 9
 178 +                               &cpu3_intc 0xffffffff &cpu3_intc 9
 179 +                               &cpu4_intc 0xffffffff &cpu4_intc 9>;
 180 +               };
 181 +               prci: clock-controller@10000000 {
 182 +                       compatible = "sifive,fu740-c000-prci";
 183 +                       reg = <0x0 0x10000000 0x0 0x1000>;
 184 +                       clocks = <&hfclk>, <&rtcclk>;
 185 +                       #clock-cells = <1>;
 186 +               };
 187 +               uart0: serial@10010000 {
 188 +                       compatible = "sifive,fu740-c000-uart", "sifive,uart0";
 189 +                       reg = <0x0 0x10010000 0x0 0x1000>;
 190 +                       interrupt-parent = <&plic0>;
 191 +                       interrupts = <39>;
 192 +                       clocks = <&prci PRCI_CLK_PCLK>;
 193 +                       status = "disabled";
 194 +               };
 195 +               uart1: serial@10011000 {
 196 +                       compatible = "sifive,fu740-c000-uart", "sifive,uart0";
 197 +                       reg = <0x0 0x10011000 0x0 0x1000>;
 198 +                       interrupt-parent = <&plic0>;
 199 +                       interrupts = <40>;
 200 +                       clocks = <&prci PRCI_CLK_PCLK>;
 201 +                       status = "disabled";
 202 +               };
 203 +               i2c0: i2c@10030000 {
 204 +                       compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
 205 +                       reg = <0x0 0x10030000 0x0 0x1000>;
 206 +                       interrupt-parent = <&plic0>;
 207 +                       interrupts = <52>;
 208 +                       clocks = <&prci PRCI_CLK_PCLK>;
 209 +                       reg-shift = <2>;
 210 +                       reg-io-width = <1>;
 211 +                       #address-cells = <1>;
 212 +                       #size-cells = <0>;
 213 +                       status = "disabled";
 214 +               };
 215 +               i2c1: i2c@10031000 {
 216 +                       compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
 217 +                       reg = <0x0 0x10031000 0x0 0x1000>;
 218 +                       interrupt-parent = <&plic0>;
 219 +                       interrupts = <53>;
 220 +                       clocks = <&prci PRCI_CLK_PCLK>;
 221 +                       reg-shift = <2>;
 222 +                       reg-io-width = <1>;
 223 +                       #address-cells = <1>;
 224 +                       #size-cells = <0>;
 225 +                       status = "disabled";
 226 +               };
 227 +               qspi0: spi@10040000 {
 228 +                       compatible = "sifive,fu740-c000-spi", "sifive,spi0";
 229 +                       reg = <0x0 0x10040000 0x0 0x1000>,
 230 +                             <0x0 0x20000000 0x0 0x10000000>;
 231 +                       interrupt-parent = <&plic0>;
 232 +                       interrupts = <41>;
 233 +                       clocks = <&prci PRCI_CLK_PCLK>;
 234 +                       #address-cells = <1>;
 235 +                       #size-cells = <0>;
 236 +                       status = "disabled";
 237 +               };
 238 +               qspi1: spi@10041000 {
 239 +                       compatible = "sifive,fu740-c000-spi", "sifive,spi0";
 240 +                       reg = <0x0 0x10041000 0x0 0x1000>,
 241 +                             <0x0 0x30000000 0x0 0x10000000>;
 242 +                       interrupt-parent = <&plic0>;
 243 +                       interrupts = <42>;
 244 +                       clocks = <&prci PRCI_CLK_PCLK>;
 245 +                       #address-cells = <1>;
 246 +                       #size-cells = <0>;
 247 +                       status = "disabled";
 248 +               };
 249 +               spi0: spi@10050000 {
 250 +                       compatible = "sifive,fu740-c000-spi", "sifive,spi0";
 251 +                       reg = <0x0 0x10050000 0x0 0x1000>;
 252 +                       interrupt-parent = <&plic0>;
 253 +                       interrupts = <43>;
 254 +                       clocks = <&prci PRCI_CLK_PCLK>;
 255 +                       #address-cells = <1>;
 256 +                       #size-cells = <0>;
 257 +                       status = "disabled";
 258 +               };
 259 +               eth0: ethernet@10090000 {
 260 +                       compatible = "sifive,fu540-c000-gem";
 261 +                       interrupt-parent = <&plic0>;
 262 +                       interrupts = <55>;
 263 +                       reg = <0x0 0x10090000 0x0 0x2000>,
 264 +                             <0x0 0x100a0000 0x0 0x1000>;
 265 +                       local-mac-address = [00 00 00 00 00 00];
 266 +                       clock-names = "pclk", "hclk";
 267 +                       clocks = <&prci PRCI_CLK_GEMGXLPLL>,
 268 +                                <&prci PRCI_CLK_GEMGXLPLL>;
 269 +                       #address-cells = <1>;
 270 +                       #size-cells = <0>;
 271 +                       status = "disabled";
 272 +               };
 273 +               pwm0: pwm@10020000 {
 274 +                       compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
 275 +                       reg = <0x0 0x10020000 0x0 0x1000>;
 276 +                       interrupt-parent = <&plic0>;
 277 +                       interrupts = <44>, <45>, <46>, <47>;
 278 +                       clocks = <&prci PRCI_CLK_PCLK>;
 279 +                       #pwm-cells = <3>;
 280 +                       status = "disabled";
 281 +               };
 282 +               pwm1: pwm@10021000 {
 283 +                       compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
 284 +                       reg = <0x0 0x10021000 0x0 0x1000>;
 285 +                       interrupt-parent = <&plic0>;
 286 +                       interrupts = <48>, <49>, <50>, <51>;
 287 +                       clocks = <&prci PRCI_CLK_PCLK>;
 288 +                       #pwm-cells = <3>;
 289 +                       status = "disabled";
 290 +               };
 291 +               ccache: cache-controller@2010000 {
 292 +                       compatible = "sifive,fu740-c000-ccache", "cache";
 293 +                       cache-block-size = <64>;
 294 +                       cache-level = <2>;
 295 +                       cache-sets = <2048>;
 296 +                       cache-size = <2097152>;
 297 +                       cache-unified;
 298 +                       interrupt-parent = <&plic0>;
 299 +                       interrupts = <19 20 21 22>;
 300 +                       reg = <0x0 0x2010000 0x0 0x1000>;
 301 +               };
 302 +               gpio: gpio@10060000 {
 303 +                       compatible = "sifive,fu740-c000-gpio", "sifive,gpio0";
 304 +                       interrupt-parent = <&plic0>;
 305 +                       interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
 306 +                                    <30>, <31>, <32>, <33>, <34>, <35>, <36>,
 307 +                                    <37>, <38>;
 308 +                       reg = <0x0 0x10060000 0x0 0x1000>;
 309 +                       gpio-controller;
 310 +                       #gpio-cells = <2>;
 311 +                       interrupt-controller;
 312 +                       #interrupt-cells = <2>;
 313 +                       clocks = <&prci PRCI_CLK_PCLK>;
 314 +                       status = "disabled";
 315 +               };
 316 +       };
 317 +};
 318 --
 319 2.7.4
 320