19b6c307d0f4e8029477f1f8f5a0cb3a0b6d757d
2 * arch/mips/ifxmips/setup.c
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
18 * Copyright (C) 2004 peng.liu@infineon.com
20 * Rewrite of Infineon IFXMips code, thanks to infineon for the support,
21 * software and hardware
23 * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
27 #include <linux/init.h>
30 #include <asm/traps.h>
33 #include <asm/ifxmips/ifxmips.h>
34 #include <asm/ifxmips/ifxmips_irq.h>
35 #include <asm/ifxmips/ifxmips_pmu.h>
37 static unsigned int r4k_offset
; /* Amount to increment compare reg each time */
38 static unsigned int r4k_cur
; /* What counter should be at next timer irq */
40 extern void ifxmips_reboot_setup (void);
41 void prom_printf (const char * fmt
, ...);
44 __init
bus_error_init (void)
50 ifxmips_get_ddr_hz (void)
52 switch (ifxmips_r32(IFXMIPS_CGU_SYS
) & 0x3)
63 EXPORT_SYMBOL(ifxmips_get_ddr_hz
);
66 ifxmips_get_cpu_hz (void)
68 unsigned int ddr_clock
= ifxmips_get_ddr_hz();
69 switch (ifxmips_r32(IFXMIPS_CGU_SYS
) & 0xc)
76 return ddr_clock
<< 1;
78 EXPORT_SYMBOL(ifxmips_get_cpu_hz
);
81 ifxmips_get_fpi_hz (void)
83 unsigned int ddr_clock
= ifxmips_get_ddr_hz();
84 if (ifxmips_r32(IFXMIPS_CGU_SYS
) & 0x40)
86 return ddr_clock
>> 1;
90 EXPORT_SYMBOL(ifxmips_get_fpi_hz
);
93 ifxmips_get_cpu_ver (void)
95 return ifxmips_r32(IFXMIPS_MCD_CHIPID
) & 0xFFFFF000;
97 EXPORT_SYMBOL(ifxmips_get_cpu_ver
);
99 static __inline__ u32
get_counter_resolution(void)
102 __asm__
__volatile__(
112 instruction_hazard();
117 ifxmips_be_handler(struct pt_regs
*regs
, int is_fixup
)
120 printk(KERN_ERR
"TODO: BUS error\n");
122 return MIPS_BE_FATAL
;
126 plat_time_init (void)
128 mips_hpt_frequency
= ifxmips_get_cpu_hz()/get_counter_resolution();
129 r4k_cur
= (read_c0_count() + r4k_offset
);
130 write_c0_compare(r4k_cur
);
131 ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_GPT
| IFXMIPS_PMU_PWDCR_FPI
);
133 ifxmips_w32(0x100, IFXMIPS_GPTU_GPT_CLC
);
135 ifxmips_w32(0xffff, IFXMIPS_GPTU_GPT_CAPREL
);
136 ifxmips_w32(0x80C0, IFXMIPS_GPTU_GPT_T6CON
);
139 extern const char* get_system_type (void);
141 //void (*board_time_init)(void);
143 plat_mem_setup (void)
146 prom_printf("This %s has a cpu rev of 0x%X\n", get_system_type(), ifxmips_get_cpu_ver());
150 status
= read_c0_status();
151 status
&= (~(1<<25));
152 write_c0_status(status
);
154 ifxmips_reboot_setup();
155 // board_time_init = ifxmips_time_init;
156 board_be_handler
= &ifxmips_be_handler
;
158 ioport_resource
.start
= IOPORT_RESOURCE_START
;
159 ioport_resource
.end
= IOPORT_RESOURCE_END
;
160 iomem_resource
.start
= IOMEM_RESOURCE_START
;
161 iomem_resource
.end
= IOMEM_RESOURCE_END
;