1 #include <linux/kernel.h>
2 #include <linux/module.h>
3 #include <linux/version.h>
4 #include <linux/types.h>
6 #include <linux/miscdevice.h>
7 #include <linux/init.h>
8 #include <asm/uaccess.h>
9 #include <asm/unistd.h>
11 #include <asm/div64.h>
12 #include <linux/errno.h>
13 #include <linux/interrupt.h>
15 #include <asm/ifxmips/ifxmips.h>
16 #include <asm/ifxmips/ifxmips_irq.h>
17 #include <asm/ifxmips/ifxmips_cgu.h>
18 #include <asm/ifxmips/ifxmips_gptu.h>
19 #include <asm/ifxmips/ifxmips_pmu.h>
21 #define MAX_NUM_OF_32BIT_TIMER_BLOCKS 6
24 #define FIRST_TIMER TIMER1A
30 * GPTC divider is set or not.
32 #define GPTU_CLC_RMC_IS_SET 0
35 * Timer Interrupt (IRQ)
37 #define TIMER_INTERRUPT INT_NUM_IM3_IRL0 + 22 // Must be adjusted when ICU driver is available
42 #define GET_BITS(x, msb, lsb) (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
43 #define SET_BITS(x, msb, lsb, value) (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
46 * GPTU Register Mapping
48 #define IFXMIPS_GPTU (KSEG1 + 0x1E100A00)
49 #define IFXMIPS_GPTU_CLC ((volatile u32*)(IFXMIPS_GPTU + 0x0000))
50 #define IFXMIPS_GPTU_ID ((volatile u32*)(IFXMIPS_GPTU + 0x0008))
51 #define IFXMIPS_GPTU_CON(n, X) ((volatile u32*)(IFXMIPS_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020)) // X must be either A or B
52 #define IFXMIPS_GPTU_RUN(n, X) ((volatile u32*)(IFXMIPS_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020)) // X must be either A or B
53 #define IFXMIPS_GPTU_RELOAD(n, X) ((volatile u32*)(IFXMIPS_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020)) // X must be either A or B
54 #define IFXMIPS_GPTU_COUNT(n, X) ((volatile u32*)(IFXMIPS_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020)) // X must be either A or B
55 #define IFXMIPS_GPTU_IRNEN ((volatile u32*)(IFXMIPS_GPTU + 0x00F4))
56 #define IFXMIPS_GPTU_IRNICR ((volatile u32*)(IFXMIPS_GPTU + 0x00F8))
57 #define IFXMIPS_GPTU_IRNCR ((volatile u32*)(IFXMIPS_GPTU + 0x00FC))
60 * Clock Control Register
62 #define GPTU_CLC_SMC GET_BITS(*IFXMIPS_GPTU_CLC, 23, 16)
63 #define GPTU_CLC_RMC GET_BITS(*IFXMIPS_GPTU_CLC, 15, 8)
64 #define GPTU_CLC_FSOE (*IFXMIPS_GPTU_CLC & (1 << 5))
65 #define GPTU_CLC_EDIS (*IFXMIPS_GPTU_CLC & (1 << 3))
66 #define GPTU_CLC_SPEN (*IFXMIPS_GPTU_CLC & (1 << 2))
67 #define GPTU_CLC_DISS (*IFXMIPS_GPTU_CLC & (1 << 1))
68 #define GPTU_CLC_DISR (*IFXMIPS_GPTU_CLC & (1 << 0))
70 #define GPTU_CLC_SMC_SET(value) SET_BITS(0, 23, 16, (value))
71 #define GPTU_CLC_RMC_SET(value) SET_BITS(0, 15, 8, (value))
72 #define GPTU_CLC_FSOE_SET(value) ((value) ? (1 << 5) : 0)
73 #define GPTU_CLC_SBWE_SET(value) ((value) ? (1 << 4) : 0)
74 #define GPTU_CLC_EDIS_SET(value) ((value) ? (1 << 3) : 0)
75 #define GPTU_CLC_SPEN_SET(value) ((value) ? (1 << 2) : 0)
76 #define GPTU_CLC_DISR_SET(value) ((value) ? (1 << 0) : 0)
81 #define GPTU_ID_ID GET_BITS(*IFXMIPS_GPTU_ID, 15, 8)
82 #define GPTU_ID_CFG GET_BITS(*IFXMIPS_GPTU_ID, 7, 5)
83 #define GPTU_ID_REV GET_BITS(*IFXMIPS_GPTU_ID, 4, 0)
86 * Control Register of Timer/Counter nX
87 * n is the index of block (1 based index)
90 #define GPTU_CON_SRC_EG(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 10))
91 #define GPTU_CON_SRC_EXT(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 9))
92 #define GPTU_CON_SYNC(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 8))
93 #define GPTU_CON_EDGE(n, X) GET_BITS(*IFXMIPS_GPTU_CON(n, X), 7, 6)
94 #define GPTU_CON_INV(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 5))
95 #define GPTU_CON_EXT(n, X) (*IFXMIPS_GPTU_CON(n, A) & (1 << 4)) // Timer/Counter B does not have this bit
96 #define GPTU_CON_STP(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 3))
97 #define GPTU_CON_CNT(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 2))
98 #define GPTU_CON_DIR(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 1))
99 #define GPTU_CON_EN(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 0))
101 #define GPTU_CON_SRC_EG_SET(value) ((value) ? 0 : (1 << 10))
102 #define GPTU_CON_SRC_EXT_SET(value) ((value) ? (1 << 9) : 0)
103 #define GPTU_CON_SYNC_SET(value) ((value) ? (1 << 8) : 0)
104 #define GPTU_CON_EDGE_SET(value) SET_BITS(0, 7, 6, (value))
105 #define GPTU_CON_INV_SET(value) ((value) ? (1 << 5) : 0)
106 #define GPTU_CON_EXT_SET(value) ((value) ? (1 << 4) : 0)
107 #define GPTU_CON_STP_SET(value) ((value) ? (1 << 3) : 0)
108 #define GPTU_CON_CNT_SET(value) ((value) ? (1 << 2) : 0)
109 #define GPTU_CON_DIR_SET(value) ((value) ? (1 << 1) : 0)
111 #define GPTU_RUN_RL_SET(value) ((value) ? (1 << 2) : 0)
112 #define GPTU_RUN_CEN_SET(value) ((value) ? (1 << 1) : 0)
113 #define GPTU_RUN_SEN_SET(value) ((value) ? (1 << 0) : 0)
115 #define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
116 #define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
118 #define TIMER_FLAG_MASK_SIZE(x) (x & 0x0001)
119 #define TIMER_FLAG_MASK_TYPE(x) (x & 0x0002)
120 #define TIMER_FLAG_MASK_STOP(x) (x & 0x0004)
121 #define TIMER_FLAG_MASK_DIR(x) (x & 0x0008)
122 #define TIMER_FLAG_NONE_EDGE 0x0000
123 #define TIMER_FLAG_MASK_EDGE(x) (x & 0x0030)
124 #define TIMER_FLAG_REAL 0x0000
125 #define TIMER_FLAG_INVERT 0x0040
126 #define TIMER_FLAG_MASK_INVERT(x) (x & 0x0040)
127 #define TIMER_FLAG_MASK_TRIGGER(x) (x & 0x0070)
128 #define TIMER_FLAG_MASK_SYNC(x) (x & 0x0080)
129 #define TIMER_FLAG_CALLBACK_IN_HB 0x0200
130 #define TIMER_FLAG_MASK_HANDLE(x) (x & 0x0300)
131 #define TIMER_FLAG_MASK_SRC(x) (x & 0x1000)
133 struct timer_dev_timer
{
134 unsigned int f_irq_on
;
142 struct mutex gptu_mutex
;
143 unsigned int number_of_timers
;
144 unsigned int occupation
;
145 unsigned int f_gptu_on
;
146 struct timer_dev_timer timer
[MAX_NUM_OF_32BIT_TIMER_BLOCKS
* 2];
149 static int gptu_ioctl(struct inode
*, struct file
*, unsigned int, unsigned long);
150 static int gptu_open(struct inode
*, struct file
*);
151 static int gptu_release(struct inode
*, struct file
*);
153 static struct file_operations gptu_fops
= {
154 .owner
= THIS_MODULE
,
157 .release
= gptu_release
160 static struct miscdevice gptu_miscdev
= {
161 .minor
= MISC_DYNAMIC_MINOR
,
166 static struct timer_dev timer_dev
;
170 timer_irq_handler(int irq
, void *p
)
174 struct timer_dev_timer
*dev_timer
= (struct timer_dev_timer
*) p
;
176 timer
= irq
- TIMER_INTERRUPT
;
177 if(timer
< timer_dev
.number_of_timers
&& dev_timer
== &timer_dev
.timer
[timer
])
179 /* Clear interrupt. */
180 ifxmips_w32(1 << timer
, IFXMIPS_GPTU_IRNCR
);
182 /* Call user hanler or signal. */
183 flag
= dev_timer
->flag
;
184 if (!(timer
& 0x01) || TIMER_FLAG_MASK_SIZE (flag
) == TIMER_FLAG_16BIT
)
185 { /* 16-bit timer or timer A of 32-bit timer */
186 switch(TIMER_FLAG_MASK_HANDLE (flag
))
188 case TIMER_FLAG_CALLBACK_IN_IRQ
:
189 case TIMER_FLAG_CALLBACK_IN_HB
:
191 (*(timer_callback
) dev_timer
->arg1
) (dev_timer
->arg2
);
193 case TIMER_FLAG_SIGNAL
:
194 send_sig ((int) dev_timer
->arg2
, (struct task_struct
*) dev_timer
->arg1
, 0);
203 ifxmips_enable_gptu(void)
205 ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_GPT
);
207 /* Set divider as 1, disable write protection for SPEN, enable module. */
209 GPTU_CLC_SMC_SET(0x00) | GPTU_CLC_RMC_SET(0x01) | GPTU_CLC_FSOE_SET(0) |
210 GPTU_CLC_SBWE_SET(1) | GPTU_CLC_EDIS_SET(0) | GPTU_CLC_SPEN_SET(0) | GPTU_CLC_DISR_SET(0);
214 ifxmips_disable_gptu(void)
216 ifxmips_w32(0x00, IFXMIPS_GPTU_IRNEN
);
217 ifxmips_w32(0xfff, IFXMIPS_GPTU_IRNCR
);
219 /* Set divider as 0, enable write protection for SPEN, disable module. */
221 GPTU_CLC_SMC_SET (0x00) | GPTU_CLC_RMC_SET (0x00) | GPTU_CLC_FSOE_SET (0) |
222 GPTU_CLC_SBWE_SET (0) | GPTU_CLC_EDIS_SET (0) | GPTU_CLC_SPEN_SET (0) | GPTU_CLC_DISR_SET (1);
224 ifxmips_pmu_disable(IFXMIPS_PMU_PWDCR_GPT
);
228 ifxmips_request_timer(unsigned int timer
, unsigned int flag
, unsigned long value
,
229 unsigned long arg1
, unsigned long arg2
)
232 unsigned int con_reg
, irnen_reg
;
235 if(timer
>= FIRST_TIMER
+ timer_dev
.number_of_timers
)
238 printk(KERN_INFO
"request_timer(%d, 0x%08X, %lu)...", (u32
)timer
, (u32
)flag
, value
);
240 if(TIMER_FLAG_MASK_SIZE(flag
) == TIMER_FLAG_16BIT
)
245 mutex_lock(&timer_dev
.gptu_mutex
);
250 if (timer
< FIRST_TIMER
) {
253 unsigned int offset
= TIMER2A
;/* This takes care of TIMER1B which is the only choice for Voice TAPI system */
256 * Pick up a free timer.
258 if (TIMER_FLAG_MASK_SIZE (flag
) == TIMER_FLAG_16BIT
) {
267 timer
< offset
+ timer_dev
.number_of_timers
;
268 timer
+= shift
, mask
<<= shift
)
269 if (!(timer_dev
.occupation
& mask
)) {
270 timer_dev
.occupation
|= mask
;
273 if (timer
>= offset
+ timer_dev
.number_of_timers
) {
274 printk("failed![%d]\n", __LINE__
);
275 mutex_unlock(&timer_dev
.gptu_mutex
);
282 register unsigned int mask
;
285 * Check if the requested timer is free.
287 mask
= (TIMER_FLAG_MASK_SIZE (flag
) == TIMER_FLAG_16BIT
? 1 : 3) << timer
;
288 if ((timer_dev
.occupation
& mask
)) {
289 printk("failed![%d] mask %#x, timer_dev.occupation %#x\n", __LINE__
, mask
, timer_dev
.occupation
);
290 mutex_unlock(&timer_dev
.gptu_mutex
);
294 timer_dev
.occupation
|= mask
;
300 * Prepare control register value.
302 switch (TIMER_FLAG_MASK_EDGE (flag
)) {
304 case TIMER_FLAG_NONE_EDGE
:
305 con_reg
= GPTU_CON_EDGE_SET (0x00);
307 case TIMER_FLAG_RISE_EDGE
:
308 con_reg
= GPTU_CON_EDGE_SET (0x01);
310 case TIMER_FLAG_FALL_EDGE
:
311 con_reg
= GPTU_CON_EDGE_SET (0x02);
313 case TIMER_FLAG_ANY_EDGE
:
314 con_reg
= GPTU_CON_EDGE_SET (0x03);
317 if (TIMER_FLAG_MASK_TYPE (flag
) == TIMER_FLAG_TIMER
)
319 TIMER_FLAG_MASK_SRC (flag
) ==
320 TIMER_FLAG_EXT_SRC
? GPTU_CON_SRC_EXT_SET (1) :
321 GPTU_CON_SRC_EXT_SET (0);
324 TIMER_FLAG_MASK_SRC (flag
) ==
325 TIMER_FLAG_EXT_SRC
? GPTU_CON_SRC_EG_SET (1) :
326 GPTU_CON_SRC_EG_SET (0);
328 TIMER_FLAG_MASK_SYNC (flag
) ==
329 TIMER_FLAG_UNSYNC
? GPTU_CON_SYNC_SET (0) :
330 GPTU_CON_SYNC_SET (1);
332 TIMER_FLAG_MASK_INVERT (flag
) ==
333 TIMER_FLAG_REAL
? GPTU_CON_INV_SET (0) : GPTU_CON_INV_SET (1);
335 TIMER_FLAG_MASK_SIZE (flag
) ==
336 TIMER_FLAG_16BIT
? GPTU_CON_EXT_SET (0) :
337 GPTU_CON_EXT_SET (1);
339 TIMER_FLAG_MASK_STOP (flag
) ==
340 TIMER_FLAG_ONCE
? GPTU_CON_STP_SET (1) : GPTU_CON_STP_SET (0);
342 TIMER_FLAG_MASK_TYPE (flag
) ==
343 TIMER_FLAG_TIMER
? GPTU_CON_CNT_SET (0) :
344 GPTU_CON_CNT_SET (1);
346 TIMER_FLAG_MASK_DIR (flag
) ==
347 TIMER_FLAG_UP
? GPTU_CON_DIR_SET (1) : GPTU_CON_DIR_SET (0);
350 * Fill up running data.
352 timer_dev
.timer
[timer
- FIRST_TIMER
].flag
= flag
;
353 timer_dev
.timer
[timer
- FIRST_TIMER
].arg1
= arg1
;
354 timer_dev
.timer
[timer
- FIRST_TIMER
].arg2
= arg2
;
355 if (TIMER_FLAG_MASK_SIZE (flag
) != TIMER_FLAG_16BIT
)
356 timer_dev
.timer
[timer
- FIRST_TIMER
+ 1].flag
= flag
;
359 * Enable GPTU module.
361 if (!timer_dev
.f_gptu_on
) {
362 ifxmips_enable_gptu ();
363 timer_dev
.f_gptu_on
= 1;
369 if (TIMER_FLAG_MASK_HANDLE (flag
) != TIMER_FLAG_NO_HANDLE
) {
370 if (TIMER_FLAG_MASK_HANDLE (flag
) == TIMER_FLAG_SIGNAL
)
371 timer_dev
.timer
[timer
- FIRST_TIMER
].arg1
=
372 (unsigned long) find_task_by_pid ((int) arg1
);
374 irnen_reg
= 1 << (timer
- FIRST_TIMER
);
376 if (TIMER_FLAG_MASK_HANDLE (flag
) == TIMER_FLAG_SIGNAL
377 || (TIMER_FLAG_MASK_HANDLE (flag
) ==
378 TIMER_FLAG_CALLBACK_IN_IRQ
379 && timer_dev
.timer
[timer
- FIRST_TIMER
].arg1
)) {
380 enable_irq (timer_dev
.timer
[timer
- FIRST_TIMER
].irq
);
381 timer_dev
.timer
[timer
- FIRST_TIMER
].f_irq_on
= 1;
388 * Write config register, reload value and enable interrupt.
392 *IFXMIPS_GPTU_CON (n
, X
) = con_reg
;
393 *IFXMIPS_GPTU_RELOAD (n
, X
) = value
;
394 // printk("reload value = %d\n", (u32)value);
395 *IFXMIPS_GPTU_IRNEN
|= irnen_reg
;
397 mutex_unlock(&timer_dev
.gptu_mutex
);
398 printk("successful!\n");
403 ifxmips_free_timer(unsigned int timer
)
409 if(!timer_dev
.f_gptu_on
)
412 if(timer
< FIRST_TIMER
|| timer
>= FIRST_TIMER
+ timer_dev
.number_of_timers
)
415 mutex_lock(&timer_dev
.gptu_mutex
);
417 flag
= timer_dev
.timer
[timer
- FIRST_TIMER
].flag
;
418 if(TIMER_FLAG_MASK_SIZE (flag
) != TIMER_FLAG_16BIT
)
421 mask
= (TIMER_FLAG_MASK_SIZE (flag
) == TIMER_FLAG_16BIT
? 1 : 3) << timer
;
422 if(((timer_dev
.occupation
& mask
) ^ mask
))
424 mutex_unlock(&timer_dev
.gptu_mutex
);
431 if(GPTU_CON_EN (n
, X
))
432 *IFXMIPS_GPTU_RUN (n
, X
) = GPTU_RUN_CEN_SET (1);
434 *IFXMIPS_GPTU_IRNEN
&= ~GPTU_IRNEN_TC_SET (n
, X
, 1);
435 *IFXMIPS_GPTU_IRNCR
|= GPTU_IRNCR_TC_SET (n
, X
, 1);
437 if(timer_dev
.timer
[timer
- FIRST_TIMER
].f_irq_on
) {
438 disable_irq (timer_dev
.timer
[timer
- FIRST_TIMER
].irq
);
439 timer_dev
.timer
[timer
- FIRST_TIMER
].f_irq_on
= 0;
442 timer_dev
.occupation
&= ~mask
;
443 if(!timer_dev
.occupation
&& timer_dev
.f_gptu_on
)
445 ifxmips_disable_gptu();
446 timer_dev
.f_gptu_on
= 0;
449 mutex_unlock(&timer_dev
.gptu_mutex
);
455 ifxmips_start_timer(unsigned int timer
, int is_resume
)
461 if(!timer_dev
.f_gptu_on
)
464 if(timer
< FIRST_TIMER
|| timer
>= FIRST_TIMER
+ timer_dev
.number_of_timers
)
467 mutex_lock(&timer_dev
.gptu_mutex
);
469 flag
= timer_dev
.timer
[timer
- FIRST_TIMER
].flag
;
470 if(TIMER_FLAG_MASK_SIZE (flag
) != TIMER_FLAG_16BIT
)
473 mask
= (TIMER_FLAG_MASK_SIZE (flag
) ==
474 TIMER_FLAG_16BIT
? 1 : 3) << timer
;
475 if(((timer_dev
.occupation
& mask
) ^ mask
))
477 mutex_unlock(&timer_dev
.gptu_mutex
);
484 *IFXMIPS_GPTU_RUN (n
, X
) = GPTU_RUN_RL_SET (!is_resume
) | GPTU_RUN_SEN_SET (1);
486 mutex_unlock(&timer_dev
.gptu_mutex
);
492 ifxmips_stop_timer(unsigned int timer
)
498 if (!timer_dev
.f_gptu_on
)
501 if (timer
< FIRST_TIMER
502 || timer
>= FIRST_TIMER
+ timer_dev
.number_of_timers
)
505 mutex_lock(&timer_dev
.gptu_mutex
);
507 flag
= timer_dev
.timer
[timer
- FIRST_TIMER
].flag
;
508 if(TIMER_FLAG_MASK_SIZE(flag
) != TIMER_FLAG_16BIT
)
511 mask
= (TIMER_FLAG_MASK_SIZE (flag
) == TIMER_FLAG_16BIT
? 1 : 3) << timer
;
512 if(((timer_dev
.occupation
& mask
) ^ mask
))
514 mutex_unlock(&timer_dev
.gptu_mutex
);
521 *IFXMIPS_GPTU_RUN (n
, X
) = GPTU_RUN_CEN_SET (1);
523 mutex_unlock(&timer_dev
.gptu_mutex
);
529 ifxmips_reset_counter_flags(u32 timer
, u32 flags
)
532 unsigned int mask
, con_reg
;
535 if(!timer_dev
.f_gptu_on
)
538 if(timer
< FIRST_TIMER
|| timer
>= FIRST_TIMER
+ timer_dev
.number_of_timers
)
541 mutex_lock(&timer_dev
.gptu_mutex
);
543 oflag
= timer_dev
.timer
[timer
- FIRST_TIMER
].flag
;
544 if(TIMER_FLAG_MASK_SIZE (oflag
) != TIMER_FLAG_16BIT
)
547 mask
= (TIMER_FLAG_MASK_SIZE (oflag
) == TIMER_FLAG_16BIT
? 1 : 3) << timer
;
548 if(((timer_dev
.occupation
& mask
) ^ mask
))
550 mutex_unlock(&timer_dev
.gptu_mutex
);
554 switch(TIMER_FLAG_MASK_EDGE (flags
))
557 case TIMER_FLAG_NONE_EDGE
:
558 con_reg
= GPTU_CON_EDGE_SET(0x00);
560 case TIMER_FLAG_RISE_EDGE
:
561 con_reg
= GPTU_CON_EDGE_SET(0x01);
563 case TIMER_FLAG_FALL_EDGE
:
564 con_reg
= GPTU_CON_EDGE_SET(0x02);
566 case TIMER_FLAG_ANY_EDGE
:
567 con_reg
= GPTU_CON_EDGE_SET(0x03);
570 if(TIMER_FLAG_MASK_TYPE (flags
) == TIMER_FLAG_TIMER
)
571 con_reg
|= TIMER_FLAG_MASK_SRC (flags
) == TIMER_FLAG_EXT_SRC
? GPTU_CON_SRC_EXT_SET (1) : GPTU_CON_SRC_EXT_SET (0);
573 con_reg
|= TIMER_FLAG_MASK_SRC (flags
) == TIMER_FLAG_EXT_SRC
? GPTU_CON_SRC_EG_SET (1) : GPTU_CON_SRC_EG_SET (0);
574 con_reg
|= TIMER_FLAG_MASK_SYNC (flags
) == TIMER_FLAG_UNSYNC
? GPTU_CON_SYNC_SET (0) : GPTU_CON_SYNC_SET (1);
575 con_reg
|= TIMER_FLAG_MASK_INVERT (flags
) == TIMER_FLAG_REAL
? GPTU_CON_INV_SET (0) : GPTU_CON_INV_SET (1);
576 con_reg
|= TIMER_FLAG_MASK_SIZE (flags
) == TIMER_FLAG_16BIT
? GPTU_CON_EXT_SET (0) : GPTU_CON_EXT_SET (1);
577 con_reg
|= TIMER_FLAG_MASK_STOP (flags
) == TIMER_FLAG_ONCE
? GPTU_CON_STP_SET (1) : GPTU_CON_STP_SET (0);
578 con_reg
|= TIMER_FLAG_MASK_TYPE (flags
) == TIMER_FLAG_TIMER
? GPTU_CON_CNT_SET (0) : GPTU_CON_CNT_SET (1);
579 con_reg
|= TIMER_FLAG_MASK_DIR (flags
) == TIMER_FLAG_UP
? GPTU_CON_DIR_SET (1) : GPTU_CON_DIR_SET (0);
581 timer_dev
.timer
[timer
- FIRST_TIMER
].flag
= flags
;
582 if(TIMER_FLAG_MASK_SIZE(flags
) != TIMER_FLAG_16BIT
)
583 timer_dev
.timer
[timer
- FIRST_TIMER
+ 1].flag
= flags
;
588 *IFXMIPS_GPTU_CON(n
, X
) = con_reg
;
590 printk(KERN_INFO
"[%s]: counter%d oflags %#x, nflags %#x, GPTU_CON %#x\n", __func__
, timer
, oflag
, flags
, *IFXMIPS_GPTU_CON (n
, X
));
591 mutex_unlock(&timer_dev
.gptu_mutex
);
594 EXPORT_SYMBOL(ifxmips_reset_counter_flags
);
597 ifxmips_get_count_value(unsigned int timer
, unsigned long *value
)
604 if(!timer_dev
.f_gptu_on
)
607 if(timer
< FIRST_TIMER
608 || timer
>= FIRST_TIMER
+ timer_dev
.number_of_timers
)
611 mutex_lock(&timer_dev
.gptu_mutex
);
613 flag
= timer_dev
.timer
[timer
- FIRST_TIMER
].flag
;
614 if(TIMER_FLAG_MASK_SIZE (flag
) != TIMER_FLAG_16BIT
)
617 mask
= (TIMER_FLAG_MASK_SIZE (flag
) == TIMER_FLAG_16BIT
? 1 : 3) << timer
;
618 if (((timer_dev
.occupation
& mask
) ^ mask
))
620 mutex_unlock(&timer_dev
.gptu_mutex
);
627 *value
= *IFXMIPS_GPTU_COUNT (n
, X
);
629 mutex_unlock(&timer_dev
.gptu_mutex
);
635 ifxmips_cal_divider(unsigned long freq
)
637 u64 module_freq
, fpi
= cgu_get_fpi_bus_clock(2);
638 u32 clock_divider
= 1;
639 module_freq
= fpi
* 1000;
640 do_div(module_freq
, clock_divider
* freq
);
645 ifxmips_set_timer (unsigned int timer
, unsigned int freq
, int is_cyclic
,
646 int is_ext_src
, unsigned int handle_flag
, unsigned long arg1
,
649 unsigned long divider
;
652 divider
= ifxmips_cal_divider(freq
);
655 flag
= ((divider
& ~0xFFFF) ? TIMER_FLAG_32BIT
: TIMER_FLAG_16BIT
)
656 | (is_cyclic
? TIMER_FLAG_CYCLIC
: TIMER_FLAG_ONCE
)
657 | (is_ext_src
? TIMER_FLAG_EXT_SRC
: TIMER_FLAG_INT_SRC
)
658 | TIMER_FLAG_TIMER
| TIMER_FLAG_DOWN
659 | TIMER_FLAG_MASK_HANDLE (handle_flag
);
661 printk(KERN_INFO
"set_timer(%d, %d), divider = %lu\n", timer
, freq
, divider
);
662 return ifxmips_request_timer (timer
, flag
, divider
, arg1
, arg2
);
666 ifxmips_set_counter(unsigned int timer
, unsigned int flag
, u32 reload
, unsigned long arg1
, unsigned long arg2
)
668 printk(KERN_INFO
"set_counter(%d, %#x, %d)\n", timer
, flag
, reload
);
669 return ifxmips_request_timer(timer
, flag
, reload
, arg1
, arg2
);
673 gptu_ioctl (struct inode
*inode
, struct file
*file
, unsigned int cmd
,
677 struct gptu_ioctl_param param
;
679 if (!access_ok (VERIFY_READ
, arg
, sizeof (struct gptu_ioctl_param
)))
681 copy_from_user (¶m
, (void *) arg
, sizeof (param
));
683 if ((((cmd
== GPTU_REQUEST_TIMER
|| cmd
== GPTU_SET_TIMER
684 || GPTU_SET_COUNTER
) && param
.timer
< 2)
685 || cmd
== GPTU_GET_COUNT_VALUE
|| cmd
== GPTU_CALCULATE_DIVIDER
)
686 && !access_ok (VERIFY_WRITE
, arg
,
687 sizeof (struct gptu_ioctl_param
)))
691 case GPTU_REQUEST_TIMER
:
692 ret
= ifxmips_request_timer (param
.timer
, param
.flag
, param
.value
,
693 (unsigned long) param
.pid
,
694 (unsigned long) param
.sig
);
696 copy_to_user (&((struct gptu_ioctl_param
*) arg
)->
697 timer
, &ret
, sizeof (&ret
));
701 case GPTU_FREE_TIMER
:
702 ret
= ifxmips_free_timer (param
.timer
);
704 case GPTU_START_TIMER
:
705 ret
= ifxmips_start_timer (param
.timer
, param
.flag
);
707 case GPTU_STOP_TIMER
:
708 ret
= ifxmips_stop_timer (param
.timer
);
710 case GPTU_GET_COUNT_VALUE
:
711 ret
= ifxmips_get_count_value (param
.timer
, ¶m
.value
);
713 copy_to_user (&((struct gptu_ioctl_param
*) arg
)->
715 sizeof (param
.value
));
717 case GPTU_CALCULATE_DIVIDER
:
718 param
.value
= ifxmips_cal_divider (param
.value
);
719 if (param
.value
== 0)
722 copy_to_user (&((struct gptu_ioctl_param
*) arg
)->
724 sizeof (param
.value
));
729 ret
= ifxmips_set_timer (param
.timer
, param
.value
,
730 TIMER_FLAG_MASK_STOP (param
.flag
) !=
731 TIMER_FLAG_ONCE
? 1 : 0,
732 TIMER_FLAG_MASK_SRC (param
.flag
) ==
733 TIMER_FLAG_EXT_SRC
? 1 : 0,
734 TIMER_FLAG_MASK_HANDLE (param
.flag
) ==
735 TIMER_FLAG_SIGNAL
? TIMER_FLAG_SIGNAL
:
736 TIMER_FLAG_NO_HANDLE
,
737 (unsigned long) param
.pid
,
738 (unsigned long) param
.sig
);
740 copy_to_user (&((struct gptu_ioctl_param
*) arg
)->
741 timer
, &ret
, sizeof (&ret
));
745 case GPTU_SET_COUNTER
:
746 ifxmips_set_counter (param
.timer
, param
.flag
, param
.value
, 0, 0);
748 copy_to_user (&((struct gptu_ioctl_param
*) arg
)->
749 timer
, &ret
, sizeof (&ret
));
761 gptu_open(struct inode
*inode
, struct file
*file
)
767 gptu_release(struct inode
*inode
, struct file
*file
)
772 ifxmips_gptu_init(void)
777 ifxmips_w32(0, IFXMIPS_GPTU_IRNEN
);
778 ifxmips_w32(0xfff, IFXMIPS_GPTU_IRNCR
);
780 memset(&timer_dev
, 0, sizeof (timer_dev
));
781 mutex_init(&timer_dev
.gptu_mutex
);
783 ifxmips_enable_gptu();
784 timer_dev
.number_of_timers
= GPTU_ID_CFG
* 2;
785 ifxmips_disable_gptu ();
786 if(timer_dev
.number_of_timers
> MAX_NUM_OF_32BIT_TIMER_BLOCKS
* 2)
787 timer_dev
.number_of_timers
= MAX_NUM_OF_32BIT_TIMER_BLOCKS
* 2;
788 printk (KERN_INFO
"gptu: totally %d 16-bit timers/counters\n", timer_dev
.number_of_timers
);
790 ret
= misc_register(&gptu_miscdev
);
793 printk(KERN_ERR
"gptu: can't misc_register, get error %d\n", -ret
);
796 printk(KERN_INFO
"gptu: misc_register on minor %d\n", gptu_miscdev
.minor
);
799 for(i
= 0; i
< timer_dev
.number_of_timers
; i
++)
801 ret
= request_irq (TIMER_INTERRUPT
+ i
, timer_irq_handler
, IRQF_TIMER
, gptu_miscdev
.name
, &timer_dev
.timer
[i
]);
805 free_irq (TIMER_INTERRUPT
+ i
, &timer_dev
.timer
[i
]);
806 misc_deregister(&gptu_miscdev
);
807 printk(KERN_ERR
"gptu: failed in requesting irq (%d), get error %d\n", i
, -ret
);
810 timer_dev
.timer
[i
].irq
= TIMER_INTERRUPT
+ i
;
811 disable_irq(timer_dev
.timer
[i
].irq
);
812 printk(KERN_INFO
"gptu: succeeded to request irq %d\n", timer_dev
.timer
[i
].irq
);
820 ifxmips_gptu_exit(void)
824 for(i
= 0; i
< timer_dev
.number_of_timers
; i
++)
826 if(timer_dev
.timer
[i
].f_irq_on
)
827 disable_irq (timer_dev
.timer
[i
].irq
);
828 free_irq(timer_dev
.timer
[i
].irq
, &timer_dev
.timer
[i
]);
830 ifxmips_disable_gptu();
831 misc_deregister(&gptu_miscdev
);
834 EXPORT_SYMBOL(ifxmips_request_timer
);
835 EXPORT_SYMBOL(ifxmips_free_timer
);
836 EXPORT_SYMBOL(ifxmips_start_timer
);
837 EXPORT_SYMBOL(ifxmips_stop_timer
);
838 EXPORT_SYMBOL(ifxmips_get_count_value
);
839 EXPORT_SYMBOL(ifxmips_cal_divider
);
840 EXPORT_SYMBOL(ifxmips_set_timer
);
841 EXPORT_SYMBOL(ifxmips_set_counter
);
843 module_init(ifxmips_gptu_init
);
844 module_exit(ifxmips_gptu_exit
);