target/linux/ifxmips/files/arch/mips/include/asm/ifxmips/ifxmips_mei.h

   1 /******************************************************************************
   2 **
   3 ** FILE NAME    : danube_mei.h
   4 ** PROJECT      : Danube
   5 ** MODULES      : MEI
   6 **
   7 ** DATE         : 1 Jan 2006
   8 ** AUTHOR       : TC Chen
   9 ** DESCRIPTION  : MEI Driver
  10 ** COPYRIGHT    :       Copyright (c) 2006
  11 **                      Infineon Technologies AG
  12 **                      Am Campeon 1-12, 85579 Neubiberg, Germany
  13 **
  14 **    This program is free software; you can redistribute it and/or modify
  15 **    it under the terms of the GNU General Public License as published by
  16 **    the Free Software Foundation; either version 2 of the License, or
  17 **    (at your option) any later version.
  18 **
  19 ** HISTORY
  20 ** $Version $Date      $Author     $Comment
  21 *******************************************************************************/
  22 #ifndef         _IFXMIPS_MEI_H
  23 #define         _IFXMIPS_MEI_H
  24 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
  25
  26 #include "ifxmips_mei_app.h"
  27
  28 #define IFXMIPS_MEI_DEBUG
  29 #define IFXMIPS_MEI_CMV_EXTRA
  30 #define IFXMIPS_MEI_MAJOR       106
  31
  32 /*
  33 **      Define where in ME Processor's memory map the Stratify chip lives
  34 */
  35
  36 #define MAXSWAPSIZE             8 * 1024        //8k *(32bits)
  37
  38 //      Mailboxes
  39 #define MSG_LENGTH              16      // x16 bits
  40 #define YES_REPLY               1
  41 #define NO_REPLY                0
  42
  43 #define CMV_TIMEOUT             100     //jiffies
  44 #define MIB_INTERVAL            10000   //msec
  45
  46 /***  Bit definitions ***/
  47
  48 #define FALSE   0
  49 #define TRUE    1
  50 #define BIT0    1<<0
  51 #define BIT1    1<<1
  52 #define BIT2    1<<2
  53 #define BIT3    1<<3
  54 #define BIT4    1<<4
  55 #define BIT5    1<<5
  56 #define BIT6    1<<6
  57 #define BIT7    1<<7
  58 #define BIT8    1<<8
  59 #define BIT9    1<<9
  60 #define BIT10   1<<10
  61 #define BIT11   1<<11
  62 #define BIT12   1<<12
  63 #define BIT13   1<<13
  64 #define BIT14   1<<14
  65 #define BIT15   1<<15
  66 #define BIT16   1<<16
  67 #define BIT17   1<<17
  68 #define BIT18   1<<18
  69 #define BIT19   1<<19
  70 #define BIT20   1<<20
  71 #define BIT21   1<<21
  72 #define BIT22   1<<22
  73 #define BIT23   1<<23
  74 #define BIT24   1<<24
  75 #define BIT25   1<<25
  76 #define BIT26   1<<26
  77 #define BIT27   1<<27
  78 #define BIT28   1<<28
  79 #define BIT29   1<<29
  80 #define BIT30   1<<30
  81 #define BIT31   1<<31
  82
  83 // ARC register addresss
  84 #define ARC_STATUS                              0x0
  85 #define ARC_LP_START                            0x2
  86 #define ARC_LP_END                              0x3
  87 #define ARC_DEBUG                               0x5
  88 #define ARC_INT_MASK                            0x10A
  89
  90 #define IRAM0_BASE                              (0x00000)
  91 #define IRAM1_BASE                              (0x04000)
  92 #define BRAM_BASE                               (0x0A000)
  93
  94 #define ADSL_BASE                               (0x20000)
  95 #define CRI_BASE                                (ADSL_BASE + 0x11F00)
  96 #define CRI_CCR0                                (CRI_BASE + 0x00)
  97 #define CRI_RST                                 (CRI_BASE + 0x04*4)
  98 #define ADSL_DILV_BASE                          (ADSL_BASE+0x20000)
  99
 100 //
 101 #define IRAM0_ADDR_BIT_MASK   0xFFF
 102 #define IRAM1_ADDR_BIT_MASK   0xFFF
 103 #define BRAM_ADDR_BIT_MASK    0xFFF
 104 #define RX_DILV_ADDR_BIT_MASK 0x1FFF
 105
 106 // CRI_CCR0 Register definitions
 107 #define CLK_2M_MODE_ENABLE                      BIT6
 108 #define ACL_CLK_MODE_ENABLE                     BIT4
 109 #define FDF_CLK_MODE_ENABLE                     BIT2
 110 #define STM_CLK_MODE_ENABLE                     BIT0
 111
 112 // CRI_RST Register definitions
 113 #define FDF_SRST                                BIT3
 114 #define MTE_SRST                                BIT2
 115 #define FCI_SRST                                BIT1
 116 #define AAI_SRST                                BIT0
 117
 118 //      MEI_TO_ARC_INTERRUPT Register definitions
 119 #define MEI_TO_ARC_INT1                 BIT3
 120 #define MEI_TO_ARC_INT0                 BIT2
 121 #define MEI_TO_ARC_CS_DONE              BIT1    //need to check
 122 #define MEI_TO_ARC_MSGAV                BIT0
 123
 124 //      ARC_TO_MEI_INTERRUPT Register definitions
 125 #define ARC_TO_MEI_INT1                 BIT8
 126 #define ARC_TO_MEI_INT0                 BIT7
 127 #define ARC_TO_MEI_CS_REQ               BIT6
 128 #define ARC_TO_MEI_DBG_DONE             BIT5
 129 #define ARC_TO_MEI_MSGACK               BIT4
 130 #define ARC_TO_MEI_NO_ACCESS            BIT3
 131 #define ARC_TO_MEI_CHECK_AAITX          BIT2
 132 #define ARC_TO_MEI_CHECK_AAIRX          BIT1
 133 #define ARC_TO_MEI_MSGAV                BIT0
 134
 135 //      ARC_TO_MEI_INTERRUPT_MASK Register definitions
 136 #define GP_INT1_EN                      BIT8
 137 #define GP_INT0_EN                      BIT7
 138 #define CS_REQ_EN                       BIT6
 139 #define DBG_DONE_EN                     BIT5
 140 #define MSGACK_EN                       BIT4
 141 #define NO_ACC_EN                       BIT3
 142 #define AAITX_EN                        BIT2
 143 #define AAIRX_EN                        BIT1
 144 #define MSGAV_EN                        BIT0
 145
 146 #define MEI_SOFT_RESET                  BIT0
 147
 148 #define HOST_MSTR                       BIT0
 149
 150 #define JTAG_MASTER_MODE                0x0
 151 #define MEI_MASTER_MODE                 HOST_MSTR
 152
 153 //      MEI_DEBUG_DECODE Register definitions
 154 #define MEI_DEBUG_DEC_MASK              (0x3)
 155 #define MEI_DEBUG_DEC_AUX_MASK          (0x0)
 156 #define MEI_DEBUG_DEC_DMP1_MASK         (0x1)
 157 #define MEI_DEBUG_DEC_DMP2_MASK         (0x2)
 158 #define MEI_DEBUG_DEC_CORE_MASK         (0x3)
 159
 160 #define AUX_STATUS                      (0x0)
 161 //      ARC_TO_MEI_MAILBOX[11] is a special location used to indicate
 162 //      page swap requests.
 163 #define MEI_TO_ARC_MAILBOX              (0xDFD0)
 164 #define MEI_TO_ARC_MAILBOXR             (MEI_TO_ARC_MAILBOX + 0x2C)
 165
 166 #define ARC_TO_MEI_MAILBOX              (0xDFA0)
 167 #define ARC_MEI_MAILBOXR                (ARC_TO_MEI_MAILBOX + 0x2C)
 168
 169 // Codeswap request messages are indicated by setting BIT31
 170 #define OMB_CODESWAP_MESSAGE_MSG_TYPE_MASK      (0x80000000)
 171
 172 // Clear Eoc messages received are indicated by setting BIT17
 173 #define OMB_CLEAREOC_INTERRUPT_CODE     (0x00020000)
 174
 175 /*
 176 **      Swap page header
 177 */
 178 //      Page must be loaded at boot time if size field has BIT31 set
 179 #define BOOT_FLAG       (BIT31)
 180 #define BOOT_FLAG_MASK  ~BOOT_FLAG
 181
 182 #define FREE_RELOAD             1
 183 #define FREE_SHOWTIME           2
 184 #define FREE_ALL                3
 185
 186 #define IFX_POP_EOC_DONE        0
 187 #define IFX_POP_EOC_FAIL        -1
 188
 189 #define CLREOC_BUFF_SIZE        12      //number of clreoc commands being buffered
 190
 191 // marcos
 192 #define IFXMIPS_WRITE_REGISTER_L(data,addr)     do{ *((volatile u32*)(addr)) = (u32)(data);} while (0)
 193 #define IFXMIPS_READ_REGISTER_L(addr)   (*((volatile u32*)(addr)))
 194 #define SET_BIT(reg, mask)                  reg |= (mask)
 195 #define CLEAR_BIT(reg, mask)                reg &= (~mask)
 196 #define CLEAR_BITS(reg, mask)               CLEAR_BIT(reg, mask)
 197 #define SET_BITS(reg, mask)                 SET_BIT(reg, mask)
 198 #define SET_BITFIELD(reg, mask, off, val)   {reg &= (~mask); reg |= (val << off);}
 199
 200 #define ALIGN_SIZE                          ( 1L<<10 )  //1K size align
 201 #define MEM_ALIGN(addr)             (((addr) + ALIGN_SIZE - 1) & ~ (ALIGN_SIZE -1) )
 202
 203 // swap marco
 204 #define MEI_HALF_WORD_SWAP(data) {data = ((data & 0xffff)<<16) + ((data & 0xffff0000)>>16);}
 205 #define MEI_BYTE_SWAP(data) {data = ((data & 0xff)<<24) + ((data & 0xff00)<<8)+ ((data & 0xff0000)>>8)+ ((data & 0xff000000)>>24);}
 206
 207 //      Swap page header describes size in 32-bit words, load location, and image offset
 208 //      for program and/or data segments
 209 typedef struct _arc_swp_page_hdr {
 210         u32 p_offset;           //Offset bytes of progseg from beginning of image
 211         u32 p_dest;             //Destination addr of progseg on processor
 212         u32 p_size;             //Size in 32-bitwords of program segment
 213         u32 d_offset;           //Offset bytes of dataseg from beginning of image
 214         u32 d_dest;             //Destination addr of dataseg on processor
 215         u32 d_size;             //Size in 32-bitwords of data segment
 216 } ARC_SWP_PAGE_HDR;
 217
 218 #ifdef CONFIG_PROC_FS
 219 typedef struct reg_entry {
 220         int *flag;
 221         char name[30];          // big enough to hold names
 222         char description[100];  // big enough to hold description
 223         unsigned short low_ino;
 224 } reg_entry_t;
 225 #endif
 226
 227 /*
 228 **      Swap image header
 229 */
 230 #define GET_PROG        0       //      Flag used for program mem segment
 231 #define GET_DATA        1       //      Flag used for data mem segment
 232
 233 //      Image header contains size of image, checksum for image, and count of
 234 //      page headers. Following that are 'count' page headers followed by
 235 //      the code and/or data segments to be loaded
 236 typedef struct _arc_img_hdr {
 237         u32 size;               //      Size of binary image in bytes
 238         u32 checksum;           //      Checksum for image
 239         u32 count;              //      Count of swp pages in image
 240         ARC_SWP_PAGE_HDR page[1];       //      Should be "count" pages - '1' to make compiler happy
 241 } ARC_IMG_HDR;
 242
 243 typedef struct smmu_mem_info {
 244         int type;
 245         unsigned long nCopy;
 246         unsigned long size;
 247         unsigned char *address;
 248         unsigned char *org_address;
 249 } smmu_mem_info_t;
 250
 251 /*
 252 **      Native size for the Stratiphy interface is 32-bits. All reads and writes
 253 **      MUST be aligned on 32-bit boundaries. Trickery must be invoked to read word and/or
 254 **      byte data. Read routines are provided. Write routines are probably a bad idea, as the
 255 **      Arc has unrestrained, unseen access to the same memory, so a read-modify-write cycle
 256 **      could very well have unintended results.
 257 */
 258 MEI_ERROR meiCMV (u16 *, int, u16 *);   // first arg is CMV to ARC, second to indicate whether need reply
 259
 260 MEI_ERROR meiDebugWrite (u32 destaddr, u32 * databuff, u32 databuffsize);
 261 extern int ifx_mei_hdlc_send (char *hdlc_pkt, int hdlc_pkt_len);
 262 extern int ifx_mei_hdlc_read (char *hdlc_pkt, int max_hdlc_pkt_len);
 263 #if defined(__KERNEL__) || defined (IFXMIPS_PORT_RTEMS)
 264 extern void makeCMV (u8 opcode, u8 group, u16 address, u16 index, int size,
 265                      u16 * data, u16 * CMVMSG);
 266 int ifx_mei_hdlc_send (char *, int);
 267 int ifx_mei_hdlc_read (char *, int);
 268 #endif
 269
 270 #endif