1 #include <linux/types.h>
3 #include <linux/kernel.h>
4 #include <linux/init.h>
5 #include <linux/delay.h>
7 #include <asm/addrspace.h>
8 #include <linux/vmalloc.h>
10 #include <ifxmips_irq.h>
11 #include <ifxmips_cgu.h>
13 #define IFXMIPS_PCI_MEM_BASE 0x18000000
14 #define IFXMIPS_PCI_MEM_SIZE 0x02000000
15 #define IFXMIPS_PCI_IO_BASE 0x1AE00000
16 #define IFXMIPS_PCI_IO_SIZE 0x00200000
18 extern int ifxmips_pci_read_config_dword(struct pci_bus
*bus
, unsigned int devfn
, int where
, int size
, u32
*val
);
19 extern int ifxmips_pci_write_config_dword(struct pci_bus
*bus
, unsigned int devfn
, int where
, int size
, u32 val
);
21 struct pci_ops ifxmips_pci_ops
=
23 .read
= ifxmips_pci_read_config_dword
,
24 .write
= ifxmips_pci_write_config_dword
27 static struct resource pci_io_resource
=
29 .name
= "io pci IO space",
30 .start
= IFXMIPS_PCI_IO_BASE
,
31 .end
= IFXMIPS_PCI_IO_BASE
+ IFXMIPS_PCI_IO_SIZE
- 1,
32 .flags
= IORESOURCE_IO
35 static struct resource pci_mem_resource
=
37 .name
= "ext pci memory space",
38 .start
= IFXMIPS_PCI_MEM_BASE
,
39 .end
= IFXMIPS_PCI_MEM_BASE
+ IFXMIPS_PCI_MEM_SIZE
- 1,
40 .flags
= IORESOURCE_MEM
43 static struct pci_controller ifxmips_pci_controller
=
45 .pci_ops
= &ifxmips_pci_ops
,
46 .mem_resource
= &pci_mem_resource
,
47 .mem_offset
= 0x00000000UL
,
48 .io_resource
= &pci_io_resource
,
49 .io_offset
= 0x00000000UL
,
52 /* the cpu can can generate the 33Mhz or rely on an external clock the cgu needs the
53 proper setting, otherwise the cpu hangs. we have no way of runtime detecting this */
54 u32 ifxmips_pci_mapped_cfg
;
55 int ifxmips_pci_external_clock
= 0;
58 ifxmips_pci_set_external_clk(char *str
)
60 printk("cgu: setting up external pci clock\n");
61 ifxmips_pci_external_clock
= 1;
64 __setup("pci_external_clk", ifxmips_pci_set_external_clk
);
67 pcibios_plat_dev_init(struct pci_dev
*dev
)
71 pci_read_config_byte(dev
, PCI_INTERRUPT_PIN
, &pin
);
77 //falling edge level triggered:0x4, low level:0xc, rising edge:0x2
78 ifxmips_w32(ifxmips_r32(IFXMIPS_EBU_PCC_CON
) | 0xc, IFXMIPS_EBU_PCC_CON
);
79 ifxmips_w32(ifxmips_r32(IFXMIPS_EBU_PCC_IEN
) | 0x10, IFXMIPS_EBU_PCC_IEN
);
84 printk ("WARNING: interrupt pin %d not supported yet!\n", pin
);
86 printk ("WARNING: invalid interrupt pin %d\n", pin
);
92 static u32
calc_bar11mask(void)
96 /* BAR11MASK value depends on available memory on system. */
97 mem
= num_physpages
* PAGE_SIZE
;
98 bar11mask
= (0x0ffffff0 & ~((1 << (fls(mem
) -1)) -1)) | 8;
104 ifxmips_pci_startup(void)
108 cgu_setup_pci_clk(ifxmips_pci_external_clock
);
110 ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_OUT
) | (1 << 5), IFXMIPS_GPIO_P1_OUT
);
111 ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_OD
) | (1 << 5), IFXMIPS_GPIO_P1_OD
);
112 ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_DIR
) | (1 << 5), IFXMIPS_GPIO_P1_DIR
);
113 ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_ALTSEL1
) & ~(1 << 5), IFXMIPS_GPIO_P1_ALTSEL1
);
114 ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_ALTSEL0
) & ~(1 << 5), IFXMIPS_GPIO_P1_ALTSEL0
);
115 ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_DIR
) & ~0x2000, IFXMIPS_GPIO_P1_DIR
);
116 ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_DIR
) | 0x4000, IFXMIPS_GPIO_P1_DIR
);
117 ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_ALTSEL1
) & ~0x6000, IFXMIPS_GPIO_P1_ALTSEL1
);
118 ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_ALTSEL0
) | 0x6000, IFXMIPS_GPIO_P1_ALTSEL0
);
119 /* enable auto-switching between PCI and EBU */
120 ifxmips_w32(0xa, PCI_CR_CLK_CTRL
);
121 /* busy, i.e. configuration is not done, PCI access has to be retried */
122 ifxmips_w32(ifxmips_r32(PCI_CR_PCI_MOD
) & ~(1 << 24), PCI_CR_PCI_MOD
);
124 /* BUS Master/IO/MEM access */
125 ifxmips_w32(ifxmips_r32(PCI_CS_STS_CMD
) | 7, PCI_CS_STS_CMD
);
127 /* enable external 2 PCI masters */
128 temp_buffer
= ifxmips_r32(PCI_CR_PC_ARB
);
129 temp_buffer
&= (~(0xf << 16));
130 /* enable internal arbiter */
131 temp_buffer
|= (1 << INTERNAL_ARB_ENABLE_BIT
);
132 /* enable internal PCI master reqest */
133 temp_buffer
&= (~(3 << PCI_MASTER0_REQ_MASK_2BITS
));
135 /* enable EBU reqest */
136 temp_buffer
&= (~(3 << PCI_MASTER1_REQ_MASK_2BITS
));
138 /* enable all external masters request */
139 temp_buffer
&= (~(3 << PCI_MASTER2_REQ_MASK_2BITS
));
140 ifxmips_w32(temp_buffer
, PCI_CR_PC_ARB
);
143 ifxmips_w32(0x18000000, PCI_CR_FCI_ADDR_MAP0
);
144 ifxmips_w32(0x18400000, PCI_CR_FCI_ADDR_MAP1
);
145 ifxmips_w32(0x18800000, PCI_CR_FCI_ADDR_MAP2
);
146 ifxmips_w32(0x18c00000, PCI_CR_FCI_ADDR_MAP3
);
147 ifxmips_w32(0x19000000, PCI_CR_FCI_ADDR_MAP4
);
148 ifxmips_w32(0x19400000, PCI_CR_FCI_ADDR_MAP5
);
149 ifxmips_w32(0x19800000, PCI_CR_FCI_ADDR_MAP6
);
150 ifxmips_w32(0x19c00000, PCI_CR_FCI_ADDR_MAP7
);
151 ifxmips_w32(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg
);
152 ifxmips_w32(calc_bar11mask(), PCI_CR_BAR11MASK
);
153 ifxmips_w32(0, PCI_CR_PCI_ADDR_MAP11
);
154 ifxmips_w32(0, PCI_CS_BASE_ADDR1
);
155 #ifdef CONFIG_SWAP_IO_SPACE
156 /* both TX and RX endian swap are enabled */
157 ifxmips_w32(ifxmips_r32(PCI_CR_PCI_EOI
) | 3, PCI_CR_PCI_EOI
);
160 /*TODO: disable BAR2 & BAR3 - why was this in the origianl infineon code */
161 ifxmips_w32(ifxmips_r32(PCI_CR_BAR12MASK
) | 0x80000000, PCI_CR_BAR12MASK
);
162 ifxmips_w32(ifxmips_r32(PCI_CR_BAR13MASK
) | 0x80000000, PCI_CR_BAR13MASK
);
163 /*use 8 dw burst length */
164 ifxmips_w32(0x303, PCI_CR_FCI_BURST_LENGTH
);
165 ifxmips_w32(ifxmips_r32(PCI_CR_PCI_MOD
) | (1 << 24), PCI_CR_PCI_MOD
);
167 ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_OUT
) & ~(1 << 5), IFXMIPS_GPIO_P1_OUT
);
170 ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_OUT
) | (1 << 5), IFXMIPS_GPIO_P1_OUT
);
174 pcibios_map_irq(const struct pci_dev
*dev
, u8 slot
, u8 pin
){
178 /* IDSEL = AD29 --> USB Host Controller */
179 return (INT_NUM_IM1_IRL0
+ 17);
181 /* IDSEL = AD30 --> mini PCI connector */
182 return (INT_NUM_IM0_IRL0
+ 22);
184 printk("Warning: no IRQ found for PCI device in slot %d, pin %d\n", slot
, pin
);
192 extern int pci_probe_only
;
195 printk("PCI: Probing PCI hardware on host bus 0.\n");
196 ifxmips_pci_startup ();
197 ifxmips_pci_mapped_cfg
= (u32
)ioremap_nocache(0x17000000, 0x800 * 16);
198 printk("IFXMips PCI mapped to 0x%08lX\n", (unsigned long)ifxmips_pci_mapped_cfg
);
199 ifxmips_pci_controller
.io_map_base
= (unsigned long)ioremap(IFXMIPS_PCI_IO_BASE
, IFXMIPS_PCI_IO_SIZE
- 1);
200 printk("IFXMips PCI I/O mapped to 0x%08lX\n", (unsigned long)ifxmips_pci_controller
.io_map_base
);
201 register_pci_controller(&ifxmips_pci_controller
);
205 arch_initcall(pcibios_init
);