2 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 * Copyright (C) 2004 Infineon IFAP DC COM CPE
19 * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
20 * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
23 #include <linux/module.h>
24 #include <linux/errno.h>
25 #include <linux/signal.h>
26 #include <linux/sched.h>
27 #include <linux/interrupt.h>
28 #include <linux/tty.h>
29 #include <linux/tty_flip.h>
30 #include <linux/major.h>
31 #include <linux/string.h>
32 #include <linux/fcntl.h>
33 #include <linux/ptrace.h>
34 #include <linux/ioport.h>
36 #include <linux/slab.h>
37 #include <linux/init.h>
38 #include <linux/circ_buf.h>
39 #include <linux/serial.h>
40 #include <linux/serial_core.h>
41 #include <linux/console.h>
42 #include <linux/sysrq.h>
43 #include <linux/irq.h>
45 #include <asm/system.h>
47 #include <asm/uaccess.h>
48 #include <asm/bitops.h>
49 #include <asm/ifxmips/ifxmips.h>
50 #include <asm/ifxmips/ifxmips_irq.h>
51 #include <asm/ifxmips/ifxmips_serial.h>
53 #define PORT_IFXMIPSASC 111
55 #include <linux/serial_core.h>
57 #define UART_DUMMY_UER_RX 1
59 static void ifxmipsasc_tx_chars(struct uart_port
*port
);
60 extern void prom_printf(const char * fmt
, ...);
61 static struct uart_port ifxmipsasc_port
[2];
62 static struct uart_driver ifxmipsasc_reg
;
63 static unsigned int uartclk
= 0;
64 extern unsigned int ifxmips_get_fpi_hz(void);
67 ifxmipsasc_stop_tx(struct uart_port
*port
)
73 ifxmipsasc_start_tx(struct uart_port
*port
)
76 local_irq_save(flags
);
77 ifxmipsasc_tx_chars(port
);
78 local_irq_restore(flags
);
83 ifxmipsasc_stop_rx(struct uart_port
*port
)
85 ifxmips_w32(ASCWHBSTATE_CLRREN
, port
->membase
+ IFXMIPS_ASC_WHBSTATE
);
89 ifxmipsasc_enable_ms(struct uart_port
*port
)
94 ifxmipsasc_rx_chars(struct uart_port
*port
)
96 struct tty_struct
*tty
= port
->info
->tty
;
97 unsigned int ch
= 0, rsr
= 0, fifocnt
;
99 fifocnt
= ifxmips_r32(port
->membase
+ IFXMIPS_ASC_FSTAT
) & ASCFSTAT_RXFFLMASK
;
102 u8 flag
= TTY_NORMAL
;
103 ch
= ifxmips_r32(port
->membase
+ IFXMIPS_ASC_RBUF
);
104 rsr
= (ifxmips_r32(port
->membase
+ IFXMIPS_ASC_STATE
) & ASCSTATE_ANY
) | UART_DUMMY_UER_RX
;
105 tty_flip_buffer_push(tty
);
109 * Note that the error handling code is
110 * out of the main execution path
112 if(rsr
& ASCSTATE_ANY
)
114 if(rsr
& ASCSTATE_PE
)
116 port
->icount
.parity
++;
117 ifxmips_w32(ifxmips_r32(port
->membase
+ IFXMIPS_ASC_WHBSTATE
) | ASCWHBSTATE_CLRPE
, port
->membase
+ IFXMIPS_ASC_WHBSTATE
);
118 } else if(rsr
& ASCSTATE_FE
)
120 port
->icount
.frame
++;
121 ifxmips_w32(ifxmips_r32(port
->membase
+ IFXMIPS_ASC_WHBSTATE
) | ASCWHBSTATE_CLRFE
, port
->membase
+ IFXMIPS_ASC_WHBSTATE
);
123 if(rsr
& ASCSTATE_ROE
)
125 port
->icount
.overrun
++;
126 ifxmips_w32(ifxmips_r32(port
->membase
+ IFXMIPS_ASC_WHBSTATE
) | ASCWHBSTATE_CLRROE
, port
->membase
+ IFXMIPS_ASC_WHBSTATE
);
129 rsr
&= port
->read_status_mask
;
131 if(rsr
& ASCSTATE_PE
)
133 else if(rsr
& ASCSTATE_FE
)
137 if((rsr
& port
->ignore_status_mask
) == 0)
138 tty_insert_flip_char(tty
, ch
, flag
);
140 if(rsr
& ASCSTATE_ROE
)
142 * Overrun is special, since it's reported
143 * immediately, and doesn't affect the current
146 tty_insert_flip_char(tty
, 0, TTY_OVERRUN
);
149 tty_flip_buffer_push(tty
);
155 ifxmipsasc_tx_chars(struct uart_port
*port
)
157 struct circ_buf
*xmit
= &port
->info
->xmit
;
159 if(uart_tx_stopped(port
))
161 ifxmipsasc_stop_tx(port
);
165 while(((ifxmips_r32(port
->membase
+ IFXMIPS_ASC_FSTAT
) & ASCFSTAT_TXFFLMASK
)
166 >> ASCFSTAT_TXFFLOFF
) != IFXMIPSASC_TXFIFO_FULL
)
170 ifxmips_w32(port
->x_char
, port
->membase
+ IFXMIPS_ASC_TBUF
);
176 if(uart_circ_empty(xmit
))
179 ifxmips_w32(port
->info
->xmit
.buf
[port
->info
->xmit
.tail
], port
->membase
+ IFXMIPS_ASC_TBUF
);
180 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
184 if(uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
185 uart_write_wakeup(port
);
189 ifxmipsasc_tx_int(int irq
, void *_port
)
191 struct uart_port
*port
= (struct uart_port
*) _port
;
192 ifxmips_w32(ASC_IRNCR_TIR
, port
->membase
+ IFXMIPS_ASC_IRNCR
);
193 ifxmipsasc_start_tx(port
);
194 ifxmips_mask_and_ack_irq(irq
);
199 ifxmipsasc_er_int(int irq
, void *_port
)
201 struct uart_port
*port
= (struct uart_port
*) _port
;
202 /* clear any pending interrupts */
203 ifxmips_w32(ifxmips_r32(port
->membase
+ IFXMIPS_ASC_WHBSTATE
) | ASCWHBSTATE_CLRPE
|
204 ASCWHBSTATE_CLRFE
| ASCWHBSTATE_CLRROE
, port
->membase
+ IFXMIPS_ASC_WHBSTATE
);
209 ifxmipsasc_rx_int(int irq
, void *_port
)
211 struct uart_port
*port
= (struct uart_port
*)_port
;
212 ifxmips_w32(ASC_IRNCR_RIR
, port
->membase
+ IFXMIPS_ASC_IRNCR
);
213 ifxmipsasc_rx_chars((struct uart_port
*)port
);
214 ifxmips_mask_and_ack_irq(irq
);
219 ifxmipsasc_tx_empty(struct uart_port
*port
)
222 status
= ifxmips_r32(port
->membase
+ IFXMIPS_ASC_FSTAT
) & ASCFSTAT_TXFFLMASK
;
223 return status
? 0 : TIOCSER_TEMT
;
227 ifxmipsasc_get_mctrl(struct uart_port
*port
)
229 return TIOCM_CTS
| TIOCM_CAR
| TIOCM_DSR
;
233 ifxmipsasc_set_mctrl(struct uart_port
*port
, u_int mctrl
)
238 ifxmipsasc_break_ctl(struct uart_port
*port
, int break_state
)
243 ifxmipsasc_startup(struct uart_port
*port
)
249 uartclk
= ifxmips_get_fpi_hz();
251 port
->uartclk
= uartclk
;
253 ifxmips_w32(ifxmips_r32(port
->membase
+ IFXMIPS_ASC_CLC
) & ~IFXMIPS_ASC_CLC_DISS
, port
->membase
+ IFXMIPS_ASC_CLC
);
254 ifxmips_w32(((ifxmips_r32(port
->membase
+ IFXMIPS_ASC_CLC
) & ~ASCCLC_RMCMASK
)) | (1 << ASCCLC_RMCOFFSET
), port
->membase
+ IFXMIPS_ASC_CLC
);
255 ifxmips_w32(0, port
->membase
+ IFXMIPS_ASC_PISEL
);
256 ifxmips_w32(((IFXMIPSASC_TXFIFO_FL
<< ASCTXFCON_TXFITLOFF
) & ASCTXFCON_TXFITLMASK
) | ASCTXFCON_TXFEN
| ASCTXFCON_TXFFLU
, port
->membase
+ IFXMIPS_ASC_TXFCON
);
257 ifxmips_w32(((IFXMIPSASC_RXFIFO_FL
<< ASCRXFCON_RXFITLOFF
) & ASCRXFCON_RXFITLMASK
) | ASCRXFCON_RXFEN
| ASCRXFCON_RXFFLU
, port
->membase
+ IFXMIPS_ASC_RXFCON
);
259 ifxmips_w32(ifxmips_r32(port
->membase
+ IFXMIPS_ASC_CON
) | ASCCON_M_8ASYNC
| ASCCON_FEN
| ASCCON_TOEN
| ASCCON_ROEN
, port
->membase
+ IFXMIPS_ASC_CON
);
261 local_irq_save(flags
);
263 retval
= request_irq(port
->irq
, ifxmipsasc_rx_int
, IRQF_DISABLED
, "asc_rx", port
);
266 printk("failed to request ifxmipsasc_rx_int\n");
270 retval
= request_irq(port
->irq
+ 2, ifxmipsasc_tx_int
, IRQF_DISABLED
, "asc_tx", port
);
273 printk("failed to request ifxmipsasc_tx_int\n");
277 retval
= request_irq(port
->irq
+ 3, ifxmipsasc_er_int
, IRQF_DISABLED
, "asc_er", port
);
280 printk("failed to request ifxmipsasc_er_int\n");
284 ifxmips_w32(ASC_IRNREN_RX_BUF
| ASC_IRNREN_TX_BUF
| ASC_IRNREN_ERR
| ASC_IRNREN_TX
, port
->membase
+ IFXMIPS_ASC_IRNREN
);
286 local_irq_restore(flags
);
290 free_irq(port
->irq
+ 2, port
);
292 free_irq(port
->irq
, port
);
293 local_irq_restore(flags
);
298 ifxmipsasc_shutdown(struct uart_port
*port
)
300 free_irq(port
->irq
, port
);
301 free_irq(port
->irq
+ 2, port
);
302 free_irq(port
->irq
+ 3, port
);
304 ifxmips_w32(0, port
->membase
+ IFXMIPS_ASC_CON
);
305 ifxmips_w32(ifxmips_r32(port
->membase
+ IFXMIPS_ASC_RXFCON
) | ASCRXFCON_RXFFLU
, port
->membase
+ IFXMIPS_ASC_RXFCON
);
306 ifxmips_w32(ifxmips_r32(port
->membase
+ IFXMIPS_ASC_RXFCON
) & ~ASCRXFCON_RXFEN
, port
->membase
+ IFXMIPS_ASC_RXFCON
);
307 ifxmips_w32(ifxmips_r32(port
->membase
+ IFXMIPS_ASC_TXFCON
) | ASCTXFCON_TXFFLU
, port
->membase
+ IFXMIPS_ASC_TXFCON
);
308 ifxmips_w32(ifxmips_r32(port
->membase
+ IFXMIPS_ASC_TXFCON
) & ~ASCTXFCON_TXFEN
, port
->membase
+ IFXMIPS_ASC_TXFCON
);
311 static void ifxmipsasc_set_termios(struct uart_port
*port
, struct ktermios
*new, struct ktermios
*old
)
317 unsigned int con
= 0;
320 cflag
= new->c_cflag
;
321 iflag
= new->c_iflag
;
323 switch(cflag
& CSIZE
)
326 con
= ASCCON_M_7ASYNC
;
332 con
= ASCCON_M_8ASYNC
;
341 if(!(cflag
& PARODD
))
347 port
->read_status_mask
= ASCSTATE_ROE
;
349 port
->read_status_mask
|= ASCSTATE_FE
| ASCSTATE_PE
;
351 port
->ignore_status_mask
= 0;
353 port
->ignore_status_mask
|= ASCSTATE_FE
| ASCSTATE_PE
;
358 * If we're ignoring parity and break indicators,
359 * ignore overruns too (for real raw support).
362 port
->ignore_status_mask
|= ASCSTATE_ROE
;
365 if((cflag
& CREAD
) == 0)
366 port
->ignore_status_mask
|= UART_DUMMY_UER_RX
;
368 /* set error signals - framing, parity and overrun, enable receiver */
369 con
|= ASCCON_FEN
| ASCCON_TOEN
| ASCCON_ROEN
;
371 local_irq_save(flags
);
374 ifxmips_w32(ifxmips_r32(port
->membase
+ IFXMIPS_ASC_CON
) | con
, port
->membase
+ IFXMIPS_ASC_CON
);
376 /* Set baud rate - take a divider of 2 into account */
377 baud
= uart_get_baud_rate(port
, new, old
, 0, port
->uartclk
/ 16);
378 quot
= uart_get_divisor(port
, baud
);
381 /* disable the baudrate generator */
382 ifxmips_w32(ifxmips_r32(port
->membase
+ IFXMIPS_ASC_CON
) & ~ASCCON_R
, port
->membase
+ IFXMIPS_ASC_CON
);
384 /* make sure the fractional divider is off */
385 ifxmips_w32(ifxmips_r32(port
->membase
+ IFXMIPS_ASC_CON
) & ~ASCCON_FDE
, port
->membase
+ IFXMIPS_ASC_CON
);
387 /* set up to use divisor of 2 */
388 ifxmips_w32(ifxmips_r32(port
->membase
+ IFXMIPS_ASC_CON
) & ~ASCCON_BRS
, port
->membase
+ IFXMIPS_ASC_CON
);
390 /* now we can write the new baudrate into the register */
391 ifxmips_w32(quot
, port
->membase
+ IFXMIPS_ASC_BG
);
393 /* turn the baudrate generator back on */
394 ifxmips_w32(ifxmips_r32(port
->membase
+ IFXMIPS_ASC_CON
) | ASCCON_R
, port
->membase
+ IFXMIPS_ASC_CON
);
397 ifxmips_w32(ASCWHBSTATE_SETREN
, port
->membase
+ IFXMIPS_ASC_WHBSTATE
);
399 local_irq_restore(flags
);
403 ifxmipsasc_type(struct uart_port
*port
)
405 return port
->type
== PORT_IFXMIPSASC
? "IFXMIPSASC" : NULL
;
409 ifxmipsasc_release_port(struct uart_port
*port
)
414 ifxmipsasc_request_port(struct uart_port
*port
)
420 ifxmipsasc_config_port(struct uart_port
*port
, int flags
)
422 if(flags
& UART_CONFIG_TYPE
)
424 port
->type
= PORT_IFXMIPSASC
;
425 ifxmipsasc_request_port(port
);
430 ifxmipsasc_verify_port(struct uart_port
*port
, struct serial_struct
*ser
)
433 if(ser
->type
!= PORT_UNKNOWN
&& ser
->type
!= PORT_IFXMIPSASC
)
435 if(ser
->irq
< 0 || ser
->irq
>= NR_IRQS
)
437 if(ser
->baud_base
< 9600)
442 static struct uart_ops ifxmipsasc_pops
=
444 .tx_empty
= ifxmipsasc_tx_empty
,
445 .set_mctrl
= ifxmipsasc_set_mctrl
,
446 .get_mctrl
= ifxmipsasc_get_mctrl
,
447 .stop_tx
= ifxmipsasc_stop_tx
,
448 .start_tx
= ifxmipsasc_start_tx
,
449 .stop_rx
= ifxmipsasc_stop_rx
,
450 .enable_ms
= ifxmipsasc_enable_ms
,
451 .break_ctl
= ifxmipsasc_break_ctl
,
452 .startup
= ifxmipsasc_startup
,
453 .shutdown
= ifxmipsasc_shutdown
,
454 .set_termios
= ifxmipsasc_set_termios
,
455 .type
= ifxmipsasc_type
,
456 .release_port
= ifxmipsasc_release_port
,
457 .request_port
= ifxmipsasc_request_port
,
458 .config_port
= ifxmipsasc_config_port
,
459 .verify_port
= ifxmipsasc_verify_port
,
462 static struct uart_port ifxmipsasc_port
[2] =
465 membase
: (void *)IFXMIPS_ASC_BASE_ADDR
,
466 mapbase
: IFXMIPS_ASC_BASE_ADDR
,
467 iotype
: SERIAL_IO_MEM
,
468 irq
: IFXMIPSASC_RIR(0),
471 type
: PORT_IFXMIPSASC
,
472 ops
: &ifxmipsasc_pops
,
473 flags
: ASYNC_BOOT_AUTOCONF
,
475 membase
: (void *)(IFXMIPS_ASC_BASE_ADDR
+ IFXMIPS_ASC_BASE_DIFF
),
476 mapbase
: IFXMIPS_ASC_BASE_ADDR
+ IFXMIPS_ASC_BASE_DIFF
,
477 iotype
: SERIAL_IO_MEM
,
478 irq
: IFXMIPSASC_RIR(1),
481 type
: PORT_IFXMIPSASC
,
482 ops
: &ifxmipsasc_pops
,
483 flags
: ASYNC_BOOT_AUTOCONF
,
488 ifxmipsasc_console_write(struct console
*co
, const char *s
, u_int count
)
493 local_irq_save(flags
);
494 for(i
= 0; i
< count
; i
++)
496 /* wait until the FIFO is not full */
499 fifocnt
= (ifxmips_r32((u32
*)(IFXMIPS_ASC_BASE_ADDR
+ (co
->index
* IFXMIPS_ASC_BASE_DIFF
) + IFXMIPS_ASC_FSTAT
)) & ASCFSTAT_TXFFLMASK
)
500 >> ASCFSTAT_TXFFLOFF
;
501 }while(fifocnt
== IFXMIPSASC_TXFIFO_FULL
);
508 ifxmips_w32('\r', (u32
*)(IFXMIPS_ASC_BASE_ADDR
+ (co
->index
* IFXMIPS_ASC_BASE_DIFF
) + IFXMIPS_ASC_TBUF
));
511 fifocnt
= (ifxmips_r32((u32
*)(IFXMIPS_ASC_BASE_ADDR
+ (co
->index
* IFXMIPS_ASC_BASE_DIFF
) + IFXMIPS_ASC_FSTAT
)) & ASCFSTAT_TXFFLMASK
)
512 >> ASCFSTAT_TXFFLOFF
;
513 } while(fifocnt
== IFXMIPSASC_TXFIFO_FULL
);
515 ifxmips_w32(s
[i
], (u32
*)(IFXMIPS_ASC_BASE_ADDR
+ (co
->index
* IFXMIPS_ASC_BASE_DIFF
) + IFXMIPS_ASC_TBUF
));
518 local_irq_restore(flags
);
522 ifxmipsasc_console_setup(struct console
*co
, char *options
)
524 struct uart_port
*port
;
531 uartclk
= ifxmips_get_fpi_hz();
533 port
= &ifxmipsasc_port
[co
->index
];
534 ifxmipsasc_port
[co
->index
].uartclk
= uartclk
;
535 ifxmipsasc_port
[co
->index
].type
= PORT_IFXMIPSASC
;
538 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
540 return uart_set_options(port
, co
, baud
, parity
, bits
, flow
);
543 static struct console ifxmipsasc_console
[2] =
547 write
: ifxmipsasc_console_write
,
548 device
: uart_console_device
,
549 setup
: ifxmipsasc_console_setup
,
550 flags
: CON_PRINTBUFFER
,
552 data
: &ifxmipsasc_reg
,
555 write
: ifxmipsasc_console_write
,
556 device
: uart_console_device
,
557 setup
: ifxmipsasc_console_setup
,
558 flags
: CON_PRINTBUFFER
,
560 data
: &ifxmipsasc_reg
,
565 ifxmipsasc_console_init(void)
567 register_console(&ifxmipsasc_console
[0]);
568 register_console(&ifxmipsasc_console
[1]);
571 console_initcall(ifxmipsasc_console_init
);
573 static struct uart_driver ifxmipsasc_reg
=
575 .owner
= THIS_MODULE
,
576 .driver_name
= "serial",
581 .cons
= ifxmipsasc_console
,
585 ifxmipsasc_init(void)
589 uart_register_driver(&ifxmipsasc_reg
);
590 res
= uart_add_one_port(&ifxmipsasc_reg
, &ifxmipsasc_port
[0]);
591 res
= uart_add_one_port(&ifxmipsasc_reg
, &ifxmipsasc_port
[1]);
597 ifxmipsasc_exit(void)
599 uart_unregister_driver(&ifxmipsasc_reg
);
602 module_init(ifxmipsasc_init
);
603 module_exit(ifxmipsasc_exit
);
605 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
606 MODULE_DESCRIPTION("MIPS IFXMips serial port driver");
607 MODULE_LICENSE("GPL");