2 * Synopsys Designware PCIe host controller driver
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * Author: Jingoo Han <jg1.han@samsung.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/of_address.h>
17 #include <linux/pci.h>
18 #include <linux/pci_regs.h>
19 #include <linux/types.h>
21 #include "pcie-designware.h"
23 /* Synopsis specific PCIE configuration registers */
24 #define PCIE_PORT_LINK_CONTROL 0x710
25 #define PORT_LINK_MODE_MASK (0x3f << 16)
26 #define PORT_LINK_MODE_1_LANES (0x1 << 16)
27 #define PORT_LINK_MODE_2_LANES (0x3 << 16)
28 #define PORT_LINK_MODE_4_LANES (0x7 << 16)
30 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
31 #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
32 #define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8)
33 #define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
34 #define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
35 #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
37 #define PCIE_MSI_ADDR_LO 0x820
38 #define PCIE_MSI_ADDR_HI 0x824
39 #define PCIE_MSI_INTR0_ENABLE 0x828
40 #define PCIE_MSI_INTR0_MASK 0x82C
41 #define PCIE_MSI_INTR0_STATUS 0x830
43 #define PCIE_ATU_VIEWPORT 0x900
44 #define PCIE_ATU_REGION_INBOUND (0x1 << 31)
45 #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
46 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
47 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
48 #define PCIE_ATU_CR1 0x904
49 #define PCIE_ATU_TYPE_MEM (0x0 << 0)
50 #define PCIE_ATU_TYPE_IO (0x2 << 0)
51 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
52 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
53 #define PCIE_ATU_CR2 0x908
54 #define PCIE_ATU_ENABLE (0x1 << 31)
55 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
56 #define PCIE_ATU_LOWER_BASE 0x90C
57 #define PCIE_ATU_UPPER_BASE 0x910
58 #define PCIE_ATU_LIMIT 0x914
59 #define PCIE_ATU_LOWER_TARGET 0x918
60 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
61 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
62 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
63 #define PCIE_ATU_UPPER_TARGET 0x91C
65 static struct hw_pci dw_pci
;
67 unsigned long global_io_offset
;
69 static inline struct pcie_port
*sys_to_pcie(struct pci_sys_data
*sys
)
71 return sys
->private_data
;
74 int cfg_read(void __iomem
*addr
, int where
, int size
, u32
*val
)
79 *val
= (*val
>> (8 * (where
& 3))) & 0xff;
81 *val
= (*val
>> (8 * (where
& 3))) & 0xffff;
83 return PCIBIOS_BAD_REGISTER_NUMBER
;
85 return PCIBIOS_SUCCESSFUL
;
88 int cfg_write(void __iomem
*addr
, int where
, int size
, u32 val
)
93 writew(val
, addr
+ (where
& 2));
95 writeb(val
, addr
+ (where
& 3));
97 return PCIBIOS_BAD_REGISTER_NUMBER
;
99 return PCIBIOS_SUCCESSFUL
;
102 static inline void dw_pcie_readl_rc(struct pcie_port
*pp
, u32 reg
, u32
*val
)
104 if (pp
->ops
->readl_rc
)
105 pp
->ops
->readl_rc(pp
, pp
->dbi_base
+ reg
, val
);
107 *val
= readl(pp
->dbi_base
+ reg
);
110 static inline void dw_pcie_writel_rc(struct pcie_port
*pp
, u32 val
, u32 reg
)
112 if (pp
->ops
->writel_rc
)
113 pp
->ops
->writel_rc(pp
, val
, pp
->dbi_base
+ reg
);
115 writel(val
, pp
->dbi_base
+ reg
);
118 int dw_pcie_rd_own_conf(struct pcie_port
*pp
, int where
, int size
,
123 if (pp
->ops
->rd_own_conf
)
124 ret
= pp
->ops
->rd_own_conf(pp
, where
, size
, val
);
126 ret
= cfg_read(pp
->dbi_base
+ (where
& ~0x3), where
, size
, val
);
131 int dw_pcie_wr_own_conf(struct pcie_port
*pp
, int where
, int size
,
136 if (pp
->ops
->wr_own_conf
)
137 ret
= pp
->ops
->wr_own_conf(pp
, where
, size
, val
);
139 ret
= cfg_write(pp
->dbi_base
+ (where
& ~0x3), where
, size
,
145 int dw_pcie_link_up(struct pcie_port
*pp
)
147 if (pp
->ops
->link_up
)
148 return pp
->ops
->link_up(pp
);
153 int __init
dw_pcie_host_init(struct pcie_port
*pp
)
155 struct device_node
*np
= pp
->dev
->of_node
;
156 struct of_pci_range range
;
157 struct of_pci_range_parser parser
;
160 if (of_pci_range_parser_init(&parser
, np
)) {
161 dev_err(pp
->dev
, "missing ranges property\n");
165 /* Get the I/O and memory ranges from DT */
166 for_each_of_pci_range(&parser
, &range
) {
167 unsigned long restype
= range
.flags
& IORESOURCE_TYPE_BITS
;
168 if (restype
== IORESOURCE_IO
) {
169 of_pci_range_to_resource(&range
, np
, &pp
->io
);
171 pp
->io
.start
= max_t(resource_size_t
,
173 range
.pci_addr
+ global_io_offset
);
174 pp
->io
.end
= min_t(resource_size_t
,
176 range
.pci_addr
+ range
.size
178 pp
->config
.io_size
= resource_size(&pp
->io
);
179 pp
->config
.io_bus_addr
= range
.pci_addr
;
181 if (restype
== IORESOURCE_MEM
) {
182 of_pci_range_to_resource(&range
, np
, &pp
->mem
);
183 pp
->mem
.name
= "MEM";
184 pp
->config
.mem_size
= resource_size(&pp
->mem
);
185 pp
->config
.mem_bus_addr
= range
.pci_addr
;
188 of_pci_range_to_resource(&range
, np
, &pp
->cfg
);
189 pp
->config
.cfg0_size
= resource_size(&pp
->cfg
)/2;
190 pp
->config
.cfg1_size
= resource_size(&pp
->cfg
)/2;
195 pp
->dbi_base
= devm_ioremap(pp
->dev
, pp
->cfg
.start
,
196 resource_size(&pp
->cfg
));
198 dev_err(pp
->dev
, "error with ioremap\n");
203 pp
->cfg0_base
= pp
->cfg
.start
;
204 pp
->cfg1_base
= pp
->cfg
.start
+ pp
->config
.cfg0_size
;
205 pp
->io_base
= pp
->io
.start
;
206 pp
->mem_base
= pp
->mem
.start
;
208 pp
->va_cfg0_base
= devm_ioremap(pp
->dev
, pp
->cfg0_base
,
209 pp
->config
.cfg0_size
);
210 if (!pp
->va_cfg0_base
) {
211 dev_err(pp
->dev
, "error with ioremap in function\n");
214 pp
->va_cfg1_base
= devm_ioremap(pp
->dev
, pp
->cfg1_base
,
215 pp
->config
.cfg1_size
);
216 if (!pp
->va_cfg1_base
) {
217 dev_err(pp
->dev
, "error with ioremap\n");
221 if (of_property_read_u32(np
, "num-lanes", &pp
->lanes
)) {
222 dev_err(pp
->dev
, "Failed to parse the number of lanes\n");
226 if (pp
->ops
->host_init
)
227 pp
->ops
->host_init(pp
);
229 dw_pcie_wr_own_conf(pp
, PCI_BASE_ADDRESS_0
, 4, 0);
231 /* program correct class for RC */
232 dw_pcie_wr_own_conf(pp
, PCI_CLASS_DEVICE
, 2, PCI_CLASS_BRIDGE_PCI
);
234 dw_pcie_rd_own_conf(pp
, PCIE_LINK_WIDTH_SPEED_CONTROL
, 4, &val
);
235 val
|= PORT_LOGIC_SPEED_CHANGE
;
236 dw_pcie_wr_own_conf(pp
, PCIE_LINK_WIDTH_SPEED_CONTROL
, 4, val
);
238 dw_pci
.nr_controllers
= 1;
239 dw_pci
.private_data
= (void **)&pp
;
241 pci_common_init(&dw_pci
);
242 pci_assign_unassigned_resources();
243 #ifdef CONFIG_PCI_DOMAINS
250 static void dw_pcie_prog_viewport_cfg0(struct pcie_port
*pp
, u32 busdev
)
252 /* Program viewport 0 : OUTBOUND : CFG0 */
253 dw_pcie_writel_rc(pp
, PCIE_ATU_REGION_OUTBOUND
| PCIE_ATU_REGION_INDEX0
,
255 dw_pcie_writel_rc(pp
, pp
->cfg0_base
, PCIE_ATU_LOWER_BASE
);
256 dw_pcie_writel_rc(pp
, (pp
->cfg0_base
>> 32), PCIE_ATU_UPPER_BASE
);
257 dw_pcie_writel_rc(pp
, pp
->cfg0_base
+ pp
->config
.cfg0_size
- 1,
259 dw_pcie_writel_rc(pp
, busdev
, PCIE_ATU_LOWER_TARGET
);
260 dw_pcie_writel_rc(pp
, 0, PCIE_ATU_UPPER_TARGET
);
261 dw_pcie_writel_rc(pp
, PCIE_ATU_TYPE_CFG0
, PCIE_ATU_CR1
);
262 dw_pcie_writel_rc(pp
, PCIE_ATU_ENABLE
, PCIE_ATU_CR2
);
265 static void dw_pcie_prog_viewport_cfg1(struct pcie_port
*pp
, u32 busdev
)
267 /* Program viewport 1 : OUTBOUND : CFG1 */
268 dw_pcie_writel_rc(pp
, PCIE_ATU_REGION_OUTBOUND
| PCIE_ATU_REGION_INDEX1
,
270 dw_pcie_writel_rc(pp
, PCIE_ATU_TYPE_CFG1
, PCIE_ATU_CR1
);
271 dw_pcie_writel_rc(pp
, PCIE_ATU_ENABLE
, PCIE_ATU_CR2
);
272 dw_pcie_writel_rc(pp
, pp
->cfg1_base
, PCIE_ATU_LOWER_BASE
);
273 dw_pcie_writel_rc(pp
, (pp
->cfg1_base
>> 32), PCIE_ATU_UPPER_BASE
);
274 dw_pcie_writel_rc(pp
, pp
->cfg1_base
+ pp
->config
.cfg1_size
- 1,
276 dw_pcie_writel_rc(pp
, busdev
, PCIE_ATU_LOWER_TARGET
);
277 dw_pcie_writel_rc(pp
, 0, PCIE_ATU_UPPER_TARGET
);
280 static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port
*pp
)
282 /* Program viewport 0 : OUTBOUND : MEM */
283 dw_pcie_writel_rc(pp
, PCIE_ATU_REGION_OUTBOUND
| PCIE_ATU_REGION_INDEX0
,
285 dw_pcie_writel_rc(pp
, PCIE_ATU_TYPE_MEM
, PCIE_ATU_CR1
);
286 dw_pcie_writel_rc(pp
, PCIE_ATU_ENABLE
, PCIE_ATU_CR2
);
287 dw_pcie_writel_rc(pp
, pp
->mem_base
, PCIE_ATU_LOWER_BASE
);
288 dw_pcie_writel_rc(pp
, (pp
->mem_base
>> 32), PCIE_ATU_UPPER_BASE
);
289 dw_pcie_writel_rc(pp
, pp
->mem_base
+ pp
->config
.mem_size
- 1,
291 dw_pcie_writel_rc(pp
, pp
->config
.mem_bus_addr
, PCIE_ATU_LOWER_TARGET
);
292 dw_pcie_writel_rc(pp
, upper_32_bits(pp
->config
.mem_bus_addr
),
293 PCIE_ATU_UPPER_TARGET
);
296 static void dw_pcie_prog_viewport_io_outbound(struct pcie_port
*pp
)
298 /* Program viewport 1 : OUTBOUND : IO */
299 dw_pcie_writel_rc(pp
, PCIE_ATU_REGION_OUTBOUND
| PCIE_ATU_REGION_INDEX1
,
301 dw_pcie_writel_rc(pp
, PCIE_ATU_TYPE_IO
, PCIE_ATU_CR1
);
302 dw_pcie_writel_rc(pp
, PCIE_ATU_ENABLE
, PCIE_ATU_CR2
);
303 dw_pcie_writel_rc(pp
, pp
->io_base
, PCIE_ATU_LOWER_BASE
);
304 dw_pcie_writel_rc(pp
, (pp
->io_base
>> 32), PCIE_ATU_UPPER_BASE
);
305 dw_pcie_writel_rc(pp
, pp
->io_base
+ pp
->config
.io_size
- 1,
307 dw_pcie_writel_rc(pp
, pp
->config
.io_bus_addr
, PCIE_ATU_LOWER_TARGET
);
308 dw_pcie_writel_rc(pp
, upper_32_bits(pp
->config
.io_bus_addr
),
309 PCIE_ATU_UPPER_TARGET
);
312 static int dw_pcie_rd_other_conf(struct pcie_port
*pp
, struct pci_bus
*bus
,
313 u32 devfn
, int where
, int size
, u32
*val
)
315 int ret
= PCIBIOS_SUCCESSFUL
;
318 busdev
= PCIE_ATU_BUS(bus
->number
) | PCIE_ATU_DEV(PCI_SLOT(devfn
)) |
319 PCIE_ATU_FUNC(PCI_FUNC(devfn
));
320 address
= where
& ~0x3;
322 if (bus
->parent
->number
== pp
->root_bus_nr
) {
323 dw_pcie_prog_viewport_cfg0(pp
, busdev
);
324 ret
= cfg_read(pp
->va_cfg0_base
+ address
, where
, size
, val
);
325 dw_pcie_prog_viewport_mem_outbound(pp
);
327 dw_pcie_prog_viewport_cfg1(pp
, busdev
);
328 ret
= cfg_read(pp
->va_cfg1_base
+ address
, where
, size
, val
);
329 dw_pcie_prog_viewport_io_outbound(pp
);
335 static int dw_pcie_wr_other_conf(struct pcie_port
*pp
, struct pci_bus
*bus
,
336 u32 devfn
, int where
, int size
, u32 val
)
338 int ret
= PCIBIOS_SUCCESSFUL
;
341 busdev
= PCIE_ATU_BUS(bus
->number
) | PCIE_ATU_DEV(PCI_SLOT(devfn
)) |
342 PCIE_ATU_FUNC(PCI_FUNC(devfn
));
343 address
= where
& ~0x3;
345 if (bus
->parent
->number
== pp
->root_bus_nr
) {
346 dw_pcie_prog_viewport_cfg0(pp
, busdev
);
347 ret
= cfg_write(pp
->va_cfg0_base
+ address
, where
, size
, val
);
348 dw_pcie_prog_viewport_mem_outbound(pp
);
350 dw_pcie_prog_viewport_cfg1(pp
, busdev
);
351 ret
= cfg_write(pp
->va_cfg1_base
+ address
, where
, size
, val
);
352 dw_pcie_prog_viewport_io_outbound(pp
);
359 static int dw_pcie_valid_config(struct pcie_port
*pp
,
360 struct pci_bus
*bus
, int dev
)
362 /* If there is no link, then there is no device */
363 if (bus
->number
!= pp
->root_bus_nr
) {
364 if (!dw_pcie_link_up(pp
))
368 /* access only one slot on each root port */
369 if (bus
->number
== pp
->root_bus_nr
&& dev
> 0)
373 * do not read more than one device on the bus directly attached
374 * to RC's (Virtual Bridge's) DS side.
376 if (bus
->primary
== pp
->root_bus_nr
&& dev
> 0)
382 static int dw_pcie_rd_conf(struct pci_bus
*bus
, u32 devfn
, int where
,
385 struct pcie_port
*pp
= sys_to_pcie(bus
->sysdata
);
394 if (dw_pcie_valid_config(pp
, bus
, PCI_SLOT(devfn
)) == 0) {
396 return PCIBIOS_DEVICE_NOT_FOUND
;
399 spin_lock_irqsave(&pp
->conf_lock
, flags
);
400 if (bus
->number
!= pp
->root_bus_nr
)
401 ret
= dw_pcie_rd_other_conf(pp
, bus
, devfn
,
404 ret
= dw_pcie_rd_own_conf(pp
, where
, size
, val
);
405 spin_unlock_irqrestore(&pp
->conf_lock
, flags
);
410 static int dw_pcie_wr_conf(struct pci_bus
*bus
, u32 devfn
,
411 int where
, int size
, u32 val
)
413 struct pcie_port
*pp
= sys_to_pcie(bus
->sysdata
);
422 if (dw_pcie_valid_config(pp
, bus
, PCI_SLOT(devfn
)) == 0)
423 return PCIBIOS_DEVICE_NOT_FOUND
;
425 spin_lock_irqsave(&pp
->conf_lock
, flags
);
426 if (bus
->number
!= pp
->root_bus_nr
)
427 ret
= dw_pcie_wr_other_conf(pp
, bus
, devfn
,
430 ret
= dw_pcie_wr_own_conf(pp
, where
, size
, val
);
431 spin_unlock_irqrestore(&pp
->conf_lock
, flags
);
436 static struct pci_ops dw_pcie_ops
= {
437 .read
= dw_pcie_rd_conf
,
438 .write
= dw_pcie_wr_conf
,
441 int dw_pcie_setup(int nr
, struct pci_sys_data
*sys
)
443 struct pcie_port
*pp
;
445 pp
= sys_to_pcie(sys
);
450 if (global_io_offset
< SZ_1M
&& pp
->config
.io_size
> 0) {
451 sys
->io_offset
= global_io_offset
- pp
->config
.io_bus_addr
;
452 pci_ioremap_io(sys
->io_offset
, pp
->io
.start
);
453 global_io_offset
+= SZ_64K
;
454 pci_add_resource_offset(&sys
->resources
, &pp
->io
,
458 sys
->mem_offset
= pp
->mem
.start
- pp
->config
.mem_bus_addr
;
459 pci_add_resource_offset(&sys
->resources
, &pp
->mem
, sys
->mem_offset
);
464 struct pci_bus
*dw_pcie_scan_bus(int nr
, struct pci_sys_data
*sys
)
467 struct pcie_port
*pp
= sys_to_pcie(sys
);
470 pp
->root_bus_nr
= sys
->busnr
;
471 bus
= pci_scan_root_bus(NULL
, sys
->busnr
, &dw_pcie_ops
,
472 sys
, &sys
->resources
);
481 int dw_pcie_map_irq(const struct pci_dev
*dev
, u8 slot
, u8 pin
)
483 struct pcie_port
*pp
= sys_to_pcie(dev
->bus
->sysdata
);
488 static struct hw_pci dw_pci
= {
489 .setup
= dw_pcie_setup
,
490 .scan
= dw_pcie_scan_bus
,
491 .map_irq
= dw_pcie_map_irq
,
494 void dw_pcie_setup_rc(struct pcie_port
*pp
)
496 struct pcie_port_info
*config
= &pp
->config
;
501 /* set the number of lines as 4 */
502 dw_pcie_readl_rc(pp
, PCIE_PORT_LINK_CONTROL
, &val
);
503 val
&= ~PORT_LINK_MODE_MASK
;
506 val
|= PORT_LINK_MODE_1_LANES
;
509 val
|= PORT_LINK_MODE_2_LANES
;
512 val
|= PORT_LINK_MODE_4_LANES
;
515 dw_pcie_writel_rc(pp
, val
, PCIE_PORT_LINK_CONTROL
);
517 /* set link width speed control register */
518 dw_pcie_readl_rc(pp
, PCIE_LINK_WIDTH_SPEED_CONTROL
, &val
);
519 val
&= ~PORT_LOGIC_LINK_WIDTH_MASK
;
522 val
|= PORT_LOGIC_LINK_WIDTH_1_LANES
;
525 val
|= PORT_LOGIC_LINK_WIDTH_2_LANES
;
528 val
|= PORT_LOGIC_LINK_WIDTH_4_LANES
;
531 dw_pcie_writel_rc(pp
, val
, PCIE_LINK_WIDTH_SPEED_CONTROL
);
534 dw_pcie_writel_rc(pp
, 0x00000004, PCI_BASE_ADDRESS_0
);
535 dw_pcie_writel_rc(pp
, 0x00000004, PCI_BASE_ADDRESS_1
);
537 /* setup interrupt pins */
538 dw_pcie_readl_rc(pp
, PCI_INTERRUPT_LINE
, &val
);
541 dw_pcie_writel_rc(pp
, val
, PCI_INTERRUPT_LINE
);
543 /* setup bus numbers */
544 dw_pcie_readl_rc(pp
, PCI_PRIMARY_BUS
, &val
);
547 dw_pcie_writel_rc(pp
, val
, PCI_PRIMARY_BUS
);
549 /* setup memory base, memory limit */
550 membase
= ((u32
)pp
->mem_base
& 0xfff00000) >> 16;
551 memlimit
= (config
->mem_size
+ (u32
)pp
->mem_base
) & 0xfff00000;
552 val
= memlimit
| membase
;
553 dw_pcie_writel_rc(pp
, val
, PCI_MEMORY_BASE
);
555 /* setup command register */
556 dw_pcie_readl_rc(pp
, PCI_COMMAND
, &val
);
558 val
|= PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
|
559 PCI_COMMAND_MASTER
| PCI_COMMAND_SERR
;
560 dw_pcie_writel_rc(pp
, val
, PCI_COMMAND
);
563 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
564 MODULE_DESCRIPTION("Designware PCIe host controller driver");
565 MODULE_LICENSE("GPL v2");