1 Subject: [v6,3/3] PCI: imx6: Add support for i.MX6 PCIe controller
2 From: Sean Cross <xobs@kosagi.com>
4 Add support for the PCIe port present on the i.MX6 family of controllers.
5 These use the Synopsis Designware core tied to their own PHY.
7 Signed-off-by: Sean Cross <xobs@kosagi.com>
8 Acked-by: Bjorn Helgaas <bhelgaas@google.com>
9 Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
11 arch/arm/boot/dts/imx6qdl.dtsi | 16 +
12 arch/arm/mach-imx/Kconfig | 2 +
13 arch/arm/mach-imx/clk-imx6q.c | 4 +
14 drivers/pci/host/Kconfig | 6 +
15 drivers/pci/host/Makefile | 1 +
16 drivers/pci/host/pci-imx6.c | 576 ++++++++++++++++++++
17 7 files changed, 611 insertions(+), 1 deletion(-)
18 create mode 100644 drivers/pci/host/pci-imx6.c
20 --- a/arch/arm/boot/dts/imx6qdl.dtsi
21 +++ b/arch/arm/boot/dts/imx6qdl.dtsi
26 + pcie: pcie@0x01000000 {
27 + compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
28 + reg = <0x01ffc000 0x4000>; /* DBI */
29 + #address-cells = <3>;
31 + device_type = "pci";
32 + ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */
33 + 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
34 + 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
36 + interrupts = <0 123 0x04>;
37 + clocks = <&clks 189>, <&clks 187>, <&clks 205>, <&clks 144>;
38 + clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi";
39 + status = "disabled";
43 compatible = "arm,cortex-a9-pmu";
44 interrupts = <0 94 0x04>;
45 --- a/arch/arm/mach-imx/Kconfig
46 +++ b/arch/arm/mach-imx/Kconfig
47 @@ -806,6 +806,8 @@ config SOC_IMX6Q
51 + select MIGHT_HAVE_PCI
52 + select PCI_DOMAINS if PCI
55 select PL310_ERRATA_588369 if CACHE_PL310
56 --- a/arch/arm/mach-imx/clk-imx6q.c
57 +++ b/arch/arm/mach-imx/clk-imx6q.c
58 @@ -586,6 +586,10 @@ int __init mx6q_clocks_init(void)
59 clk_prepare_enable(clk[usbphy2_gate]);
62 + /* All existing boards with PCIe use LVDS1 */
63 + if (IS_ENABLED(CONFIG_PCI_IMX6))
64 + clk_set_parent(clk[lvds1_sel], clk[sata_ref]);
66 /* Set initial power mode */
67 imx6q_set_lpm(WAIT_CLOCKED);
70 +++ b/drivers/pci/host/Kconfig
72 +menu "PCI host controller drivers"
79 + bool "Freescale i.MX6 PCIe controller"
80 + depends on SOC_IMX6Q
86 +++ b/drivers/pci/host/Makefile
88 +obj-$(CONFIG_PCIE_DW) += pcie-designware.o
89 +obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
91 +++ b/drivers/pci/host/pci-imx6.c
94 + * PCIe host controller driver for Freescale i.MX6 SoCs
96 + * Copyright (C) 2013 Kosagi
97 + * http://www.kosagi.com
99 + * Author: Sean Cross <xobs@kosagi.com>
101 + * This program is free software; you can redistribute it and/or modify
102 + * it under the terms of the GNU General Public License version 2 as
103 + * published by the Free Software Foundation.
106 +#include <linux/clk.h>
107 +#include <linux/delay.h>
108 +#include <linux/gpio.h>
109 +#include <linux/kernel.h>
110 +#include <linux/mfd/syscon.h>
111 +#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
112 +#include <linux/module.h>
113 +#include <linux/of_gpio.h>
114 +#include <linux/pci.h>
115 +#include <linux/platform_device.h>
116 +#include <linux/regmap.h>
117 +#include <linux/resource.h>
118 +#include <linux/signal.h>
119 +#include <linux/types.h>
121 +#include "pcie-designware.h"
123 +#define to_imx6_pcie(x) container_of(x, struct imx6_pcie, pp)
130 + struct clk *lvds_gate;
131 + struct clk *sata_ref_100m;
132 + struct clk *pcie_ref_125m;
133 + struct clk *pcie_axi;
134 + struct pcie_port pp;
135 + struct regmap *iomuxc_gpr;
136 + void __iomem *mem_base;
139 +/* PCIe Port Logic registers (memory-mapped) */
140 +#define PL_OFFSET 0x700
141 +#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
142 +#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
144 +#define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
145 +#define PCIE_PHY_CTRL_DATA_LOC 0
146 +#define PCIE_PHY_CTRL_CAP_ADR_LOC 16
147 +#define PCIE_PHY_CTRL_CAP_DAT_LOC 17
148 +#define PCIE_PHY_CTRL_WR_LOC 18
149 +#define PCIE_PHY_CTRL_RD_LOC 19
151 +#define PCIE_PHY_STAT (PL_OFFSET + 0x110)
152 +#define PCIE_PHY_STAT_ACK_LOC 16
154 +/* PHY registers (not memory-mapped) */
155 +#define PCIE_PHY_RX_ASIC_OUT 0x100D
157 +#define PHY_RX_OVRD_IN_LO 0x1005
158 +#define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
159 +#define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
161 +static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
164 + u32 max_iterations = 10;
165 + u32 wait_counter = 0;
168 + val = readl(dbi_base + PCIE_PHY_STAT);
169 + val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
172 + if (val == exp_val)
176 + } while ((wait_counter < max_iterations) && (val != exp_val));
181 +static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)
186 + val = addr << PCIE_PHY_CTRL_DATA_LOC;
187 + writel(val, dbi_base + PCIE_PHY_CTRL);
189 + val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
190 + writel(val, dbi_base + PCIE_PHY_CTRL);
192 + ret = pcie_phy_poll_ack(dbi_base, 1);
196 + val = addr << PCIE_PHY_CTRL_DATA_LOC;
197 + writel(val, dbi_base + PCIE_PHY_CTRL);
199 + ret = pcie_phy_poll_ack(dbi_base, 0);
206 +/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
207 +static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data)
212 + ret = pcie_phy_wait_ack(dbi_base, addr);
216 + /* assert Read signal */
217 + phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
218 + writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);
220 + ret = pcie_phy_poll_ack(dbi_base, 1);
224 + val = readl(dbi_base + PCIE_PHY_STAT);
225 + *data = val & 0xffff;
227 + /* deassert Read signal */
228 + writel(0x00, dbi_base + PCIE_PHY_CTRL);
230 + ret = pcie_phy_poll_ack(dbi_base, 0);
237 +static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
244 + ret = pcie_phy_wait_ack(dbi_base, addr);
248 + var = data << PCIE_PHY_CTRL_DATA_LOC;
249 + writel(var, dbi_base + PCIE_PHY_CTRL);
252 + var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
253 + writel(var, dbi_base + PCIE_PHY_CTRL);
255 + ret = pcie_phy_poll_ack(dbi_base, 1);
259 + /* deassert cap data */
260 + var = data << PCIE_PHY_CTRL_DATA_LOC;
261 + writel(var, dbi_base + PCIE_PHY_CTRL);
263 + /* wait for ack de-assetion */
264 + ret = pcie_phy_poll_ack(dbi_base, 0);
268 + /* assert wr signal */
269 + var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
270 + writel(var, dbi_base + PCIE_PHY_CTRL);
273 + ret = pcie_phy_poll_ack(dbi_base, 1);
277 + /* deassert wr signal */
278 + var = data << PCIE_PHY_CTRL_DATA_LOC;
279 + writel(var, dbi_base + PCIE_PHY_CTRL);
281 + /* wait for ack de-assetion */
282 + ret = pcie_phy_poll_ack(dbi_base, 0);
286 + writel(0x0, dbi_base + PCIE_PHY_CTRL);
291 +/* Added for PCI abort handling */
292 +static int imx6q_pcie_abort_handler(unsigned long addr,
293 + unsigned int fsr, struct pt_regs *regs)
296 + * If it was an imprecise abort, then we need to correct the
297 + * return address to be _after_ the instruction.
299 + if (fsr & (1 << 10))
304 +static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
306 + struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
308 + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
309 + IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
310 + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
311 + IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
312 + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
313 + IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
315 + gpio_set_value(imx6_pcie->reset_gpio, 0);
317 + gpio_set_value(imx6_pcie->reset_gpio, 1);
322 +static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
324 + struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
327 + if (gpio_is_valid(imx6_pcie->power_on_gpio))
328 + gpio_set_value(imx6_pcie->power_on_gpio, 1);
330 + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
331 + IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
332 + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
333 + IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
335 + ret = clk_prepare_enable(imx6_pcie->sata_ref_100m);
337 + dev_err(pp->dev, "unable to enable sata_ref_100m\n");
341 + ret = clk_prepare_enable(imx6_pcie->pcie_ref_125m);
343 + dev_err(pp->dev, "unable to enable pcie_ref_125m\n");
347 + ret = clk_prepare_enable(imx6_pcie->lvds_gate);
349 + dev_err(pp->dev, "unable to enable lvds_gate\n");
350 + goto err_lvds_gate;
353 + ret = clk_prepare_enable(imx6_pcie->pcie_axi);
355 + dev_err(pp->dev, "unable to enable pcie_axi\n");
359 + /* allow the clocks to stabilize */
360 + usleep_range(200, 500);
365 + clk_disable_unprepare(imx6_pcie->lvds_gate);
367 + clk_disable_unprepare(imx6_pcie->pcie_ref_125m);
369 + clk_disable_unprepare(imx6_pcie->sata_ref_100m);
375 +static void imx6_pcie_init_phy(struct pcie_port *pp)
377 + struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
379 + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
380 + IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
382 + /* configure constant input signal to the pcie ctrl and phy */
383 + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
384 + IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12);
385 + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
386 + IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
388 + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
389 + IMX6Q_GPR8_TX_DEEMPH_GEN1, 0 << 0);
390 + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
391 + IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, 0 << 6);
392 + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
393 + IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, 20 << 12);
394 + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
395 + IMX6Q_GPR8_TX_SWING_FULL, 127 << 18);
396 + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
397 + IMX6Q_GPR8_TX_SWING_LOW, 127 << 25);
400 +static void imx6_pcie_host_init(struct pcie_port *pp)
403 + struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
405 + imx6_pcie_assert_core_reset(pp);
407 + imx6_pcie_init_phy(pp);
409 + imx6_pcie_deassert_core_reset(pp);
411 + dw_pcie_setup_rc(pp);
413 + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
414 + IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
416 + while (!dw_pcie_link_up(pp)) {
417 + usleep_range(100, 1000);
420 + dev_err(pp->dev, "phy link never came up\n");
422 + "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
423 + readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
424 + readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
432 +static int imx6_pcie_link_up(struct pcie_port *pp)
434 + u32 rc, ltssm, rx_valid, temp;
436 + /* link is debug bit 36, debug register 1 starts at bit 32 */
437 + rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1) & (0x1 << (36 - 32));
442 + * From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
443 + * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).
444 + * If (MAC/LTSSM.state == Recovery.RcvrLock)
445 + * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition
448 + pcie_phy_read(pp->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
449 + ltssm = readl(pp->dbi_base + PCIE_PHY_DEBUG_R0) & 0x3F;
451 + if (rx_valid & 0x01)
458 + "transition to gen2 is stuck, reset PHY!\n");
460 + pcie_phy_read(pp->dbi_base,
461 + PHY_RX_OVRD_IN_LO, &temp);
462 + temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN
463 + | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
464 + pcie_phy_write(pp->dbi_base,
465 + PHY_RX_OVRD_IN_LO, temp);
467 + usleep_range(2000, 3000);
469 + pcie_phy_read(pp->dbi_base,
470 + PHY_RX_OVRD_IN_LO, &temp);
471 + temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN
472 + | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
473 + pcie_phy_write(pp->dbi_base,
474 + PHY_RX_OVRD_IN_LO, temp);
479 +static struct pcie_host_ops imx6_pcie_host_ops = {
480 + .link_up = imx6_pcie_link_up,
481 + .host_init = imx6_pcie_host_init,
484 +static int imx6_add_pcie_port(struct pcie_port *pp,
485 + struct platform_device *pdev)
489 + pp->irq = platform_get_irq(pdev, 0);
491 + dev_err(&pdev->dev, "failed to get irq\n");
495 + pp->root_bus_nr = -1;
496 + pp->ops = &imx6_pcie_host_ops;
498 + spin_lock_init(&pp->conf_lock);
499 + ret = dw_pcie_host_init(pp);
501 + dev_err(&pdev->dev, "failed to initialize host\n");
508 +static int __init imx6_pcie_probe(struct platform_device *pdev)
510 + struct imx6_pcie *imx6_pcie;
511 + struct pcie_port *pp;
512 + struct device_node *np = pdev->dev.of_node;
513 + struct resource *dbi_base;
516 + imx6_pcie = devm_kzalloc(&pdev->dev, sizeof(*imx6_pcie), GFP_KERNEL);
520 + pp = &imx6_pcie->pp;
521 + pp->dev = &pdev->dev;
523 + /* Added for PCI abort handling */
524 + hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0,
525 + "imprecise external abort");
527 + dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
529 + dev_err(&pdev->dev, "dbi_base memory resource not found\n");
533 + pp->dbi_base = devm_ioremap_resource(&pdev->dev, dbi_base);
534 + if (IS_ERR(pp->dbi_base)) {
535 + dev_err(&pdev->dev, "unable to remap dbi_base\n");
536 + ret = PTR_ERR(pp->dbi_base);
541 + imx6_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
542 + if (!gpio_is_valid(imx6_pcie->reset_gpio)) {
543 + dev_err(&pdev->dev, "no reset-gpio defined\n");
546 + ret = devm_gpio_request_one(&pdev->dev,
547 + imx6_pcie->reset_gpio,
548 + GPIOF_OUT_INIT_LOW,
551 + dev_err(&pdev->dev, "unable to get reset gpio\n");
555 + imx6_pcie->power_on_gpio = of_get_named_gpio(np, "power-on-gpio", 0);
556 + if (gpio_is_valid(imx6_pcie->power_on_gpio)) {
557 + ret = devm_gpio_request_one(&pdev->dev,
558 + imx6_pcie->power_on_gpio,
559 + GPIOF_OUT_INIT_LOW,
560 + "PCIe power enable");
562 + dev_err(&pdev->dev, "unable to get power-on gpio\n");
567 + imx6_pcie->wake_up_gpio = of_get_named_gpio(np, "wake-up-gpio", 0);
568 + if (gpio_is_valid(imx6_pcie->wake_up_gpio)) {
569 + ret = devm_gpio_request_one(&pdev->dev,
570 + imx6_pcie->wake_up_gpio,
574 + dev_err(&pdev->dev, "unable to get wake-up gpio\n");
579 + imx6_pcie->disable_gpio = of_get_named_gpio(np, "disable-gpio", 0);
580 + if (gpio_is_valid(imx6_pcie->disable_gpio)) {
581 + ret = devm_gpio_request_one(&pdev->dev,
582 + imx6_pcie->disable_gpio,
583 + GPIOF_OUT_INIT_HIGH,
584 + "PCIe disable endpoint");
586 + dev_err(&pdev->dev, "unable to get disable-ep gpio\n");
592 + imx6_pcie->lvds_gate = clk_get(&pdev->dev, "lvds_gate");
593 + if (IS_ERR(imx6_pcie->lvds_gate)) {
594 + dev_err(&pdev->dev,
595 + "lvds_gate clock select missing or invalid\n");
596 + ret = PTR_ERR(imx6_pcie->lvds_gate);
600 + imx6_pcie->sata_ref_100m = clk_get(&pdev->dev, "sata_ref_100m");
601 + if (IS_ERR(imx6_pcie->sata_ref_100m)) {
602 + dev_err(&pdev->dev,
603 + "sata_ref_100m clock source missing or invalid\n");
604 + ret = PTR_ERR(imx6_pcie->sata_ref_100m);
608 + imx6_pcie->pcie_ref_125m = clk_get(&pdev->dev, "pcie_ref_125m");
609 + if (IS_ERR(imx6_pcie->pcie_ref_125m)) {
610 + dev_err(&pdev->dev,
611 + "pcie_ref_125m clock source missing or invalid\n");
612 + ret = PTR_ERR(imx6_pcie->pcie_ref_125m);
616 + imx6_pcie->pcie_axi = clk_get(&pdev->dev, "pcie_axi");
617 + if (IS_ERR(imx6_pcie->pcie_axi)) {
618 + dev_err(&pdev->dev,
619 + "pcie_axi clock source missing or invalid\n");
620 + ret = PTR_ERR(imx6_pcie->pcie_axi);
624 + /* Grab GPR config register range */
625 + imx6_pcie->iomuxc_gpr =
626 + syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
627 + if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
628 + dev_err(&pdev->dev, "unable to find iomuxc registers\n");
629 + ret = PTR_ERR(imx6_pcie->iomuxc_gpr);
633 + ret = imx6_add_pcie_port(pp, pdev);
637 + platform_set_drvdata(pdev, imx6_pcie);
644 +static const struct of_device_id imx6_pcie_of_match[] = {
645 + { .compatible = "fsl,imx6q-pcie", },
648 +MODULE_DEVICE_TABLE(of, imx6_pcie_of_match);
650 +static struct platform_driver imx6_pcie_driver = {
652 + .name = "imx6q-pcie",
653 + .owner = THIS_MODULE,
654 + .of_match_table = of_match_ptr(imx6_pcie_of_match),
658 +/* Freescale PCIe driver does not allow module unload */
660 +static int __init imx6_init(void)
662 + return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe);
664 +module_init(imx6_init);
666 +MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>");
667 +MODULE_DESCRIPTION("Freescale i.MX6 PCIe host controller driver");
668 +MODULE_LICENSE("GPL v2");