1 From 9a820b55817011f53771e6bfebae5fe059f0a534 Mon Sep 17 00:00:00 2001
2 From: Robert Jones <rjones@gateworks.com>
3 Date: Wed, 8 Jan 2020 07:44:24 -0800
4 Subject: [PATCH 4/4] ARM: dts: imx: Add GW5912 board support
6 The Gateworks GW5912 is an IMX6 SoC based single board computer with:
10 - 4x miniPCIe socket with PCI Gen2, USB2
11 - 1x miniPCIe socket with PCI Gen2, USB2, mSATA
12 - 1x miniPCIe socket with PCI Gen2, USB2, mezzanine
13 - 10V to 60V DC input barrel jack
14 - 3axis accelerometer (lis2de12)
16 - bi-color front-panel LED
17 - 256MB NAND boot device
18 - nanoSIM/microSD socket (with UHS-I support)
20 - Gateworks System Controller (hwmon, pushbutton controller, EEPROM)
21 - CAN Bus transceiver (mcp2562)
22 - RS232 transceiver (1x UART with flow-control or 2x UART (build option)
23 - off-board SPI connector (1x chip-select)
25 Signed-off-by: Robert Jones <rjones@gateworks.com>
26 Reviewed-by: Tim Harvey <tharvey@gateworks.com>
27 Signed-off-by: Shawn Guo <shawnguo@kernel.org>
29 arch/arm/boot/dts/Makefile | 2 +
30 arch/arm/boot/dts/imx6dl-gw5912.dts | 13 +
31 arch/arm/boot/dts/imx6q-gw5912.dts | 13 +
32 arch/arm/boot/dts/imx6qdl-gw5912.dtsi | 461 ++++++++++++++++++++++++++++++++++
33 4 files changed, 489 insertions(+)
34 create mode 100644 arch/arm/boot/dts/imx6dl-gw5912.dts
35 create mode 100644 arch/arm/boot/dts/imx6q-gw5912.dts
36 create mode 100644 arch/arm/boot/dts/imx6qdl-gw5912.dtsi
38 diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
39 index 5b059fc..1a32a7d 100644
40 --- a/arch/arm/boot/dts/Makefile
41 +++ b/arch/arm/boot/dts/Makefile
42 @@ -424,6 +424,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
48 imx6dl-hummingboard.dtb \
49 imx6dl-hummingboard-emmc-som-v15.dtb \
50 @@ -498,6 +499,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
57 imx6q-hummingboard.dtb \
58 diff --git a/arch/arm/boot/dts/imx6dl-gw5912.dts b/arch/arm/boot/dts/imx6dl-gw5912.dts
60 index 00000000..5260e01
62 +++ b/arch/arm/boot/dts/imx6dl-gw5912.dts
64 +// SPDX-License-Identifier: GPL-2.0
66 + * Copyright 2019 Gateworks Corporation
70 +#include "imx6dl.dtsi"
71 +#include "imx6qdl-gw5912.dtsi"
74 + model = "Gateworks Ventana i.MX6 DualLite/Solo GW5912";
75 + compatible = "gw,imx6dl-gw5912", "gw,ventana", "fsl,imx6dl";
77 diff --git a/arch/arm/boot/dts/imx6q-gw5912.dts b/arch/arm/boot/dts/imx6q-gw5912.dts
79 index 00000000..4dcbd94
81 +++ b/arch/arm/boot/dts/imx6q-gw5912.dts
83 +// SPDX-License-Identifier: GPL-2.0
85 + * Copyright 2019 Gateworks Corporation
89 +#include "imx6q.dtsi"
90 +#include "imx6qdl-gw5912.dtsi"
93 + model = "Gateworks Ventana i.MX6 Dual/Quad GW5912";
94 + compatible = "gw,imx6q-gw5912", "gw,ventana", "fsl,imx6q";
96 diff --git a/arch/arm/boot/dts/imx6qdl-gw5912.dtsi b/arch/arm/boot/dts/imx6qdl-gw5912.dtsi
98 index 00000000..8c57fd2
100 +++ b/arch/arm/boot/dts/imx6qdl-gw5912.dtsi
102 +// SPDX-License-Identifier: GPL-2.0
104 + * Copyright 2019 Gateworks Corporation
107 +#include <dt-bindings/gpio/gpio.h>
110 + /* these are used by bootloader for disabling nodes */
121 + stdout-path = &uart2;
125 + compatible = "gpio-leds";
126 + pinctrl-names = "default";
127 + pinctrl-0 = <&pinctrl_gpio_leds>;
131 + gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
132 + default-state = "on";
133 + linux,default-trigger = "heartbeat";
138 + gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
139 + default-state = "off";
144 + gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
145 + default-state = "off";
150 + device_type = "memory";
151 + reg = <0x10000000 0x40000000>;
155 + compatible = "pps-gpio";
156 + pinctrl-names = "default";
157 + pinctrl-0 = <&pinctrl_pps>;
158 + gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
161 + reg_3p3v: regulator-3p3v {
162 + compatible = "regulator-fixed";
163 + regulator-name = "3P3V";
164 + regulator-min-microvolt = <3300000>;
165 + regulator-max-microvolt = <3300000>;
166 + regulator-always-on;
169 + reg_usb_vbus: regulator-5p0v {
170 + compatible = "regulator-fixed";
171 + regulator-name = "usb_vbus";
172 + regulator-min-microvolt = <5000000>;
173 + regulator-max-microvolt = <5000000>;
174 + regulator-always-on;
179 + pinctrl-names = "default";
180 + pinctrl-0 = <&pinctrl_flexcan1>;
185 + cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
186 + pinctrl-names = "default";
187 + pinctrl-0 = <&pinctrl_ecspi2>;
192 + pinctrl-names = "default";
193 + pinctrl-0 = <&pinctrl_enet>;
194 + phy-mode = "rgmii-id";
199 + pinctrl-names = "default";
200 + pinctrl-0 = <&pinctrl_gpmi_nand>;
205 + clock-frequency = <100000>;
206 + pinctrl-names = "default";
207 + pinctrl-0 = <&pinctrl_i2c1>;
211 + compatible = "nxp,pca9555";
218 + compatible = "atmel,24c02";
224 + compatible = "atmel,24c02";
230 + compatible = "atmel,24c02";
236 + compatible = "atmel,24c02";
242 + compatible = "dallas,ds1672";
248 + clock-frequency = <100000>;
249 + pinctrl-names = "default";
250 + pinctrl-0 = <&pinctrl_i2c2>;
255 + clock-frequency = <100000>;
256 + pinctrl-names = "default";
257 + pinctrl-0 = <&pinctrl_i2c3>;
261 + pinctrl-names = "default";
262 + pinctrl-0 = <&pinctrl_accel>;
263 + compatible = "st,lis2de12";
265 + st,drdy-int-pin = <1>;
266 + interrupt-parent = <&gpio7>;
267 + interrupts = <13 0>;
268 + interrupt-names = "INT1";
273 + pinctrl-names = "default";
274 + pinctrl-0 = <&pinctrl_pcie>;
275 + reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
280 + pinctrl-names = "default";
281 + pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */
282 + status = "disabled";
286 + pinctrl-names = "default";
287 + pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
288 + status = "disabled";
292 + pinctrl-names = "default";
293 + pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
294 + status = "disabled";
298 + pinctrl-names = "default";
299 + pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
300 + status = "disabled";
304 + pinctrl-names = "default";
305 + pinctrl-0 = <&pinctrl_uart1>;
306 + rts-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>;
311 + pinctrl-names = "default";
312 + pinctrl-0 = <&pinctrl_uart2>;
317 + pinctrl-names = "default";
318 + pinctrl-0 = <&pinctrl_uart5>;
323 + vbus-supply = <®_usb_vbus>;
324 + pinctrl-names = "default";
325 + pinctrl-0 = <&pinctrl_usbotg>;
326 + disable-over-current;
332 + vbus-supply = <®_usb_vbus>;
337 + pinctrl-names = "default", "state_100mhz", "state_200mhz";
338 + pinctrl-0 = <&pinctrl_usdhc3>;
339 + pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
340 + pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
341 + cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
342 + vmmc-supply = <®_3p3v>;
343 + no-1-8-v; /* firmware will remove if board revision supports */
348 + status = "disabled";
352 + pinctrl-names = "default";
353 + pinctrl-0 = <&pinctrl_wdog>;
354 + fsl,ext-reset-output;
359 + pinctrl_accel: accelmuxgrp {
361 + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1
365 + pinctrl_enet: enetgrp {
367 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
368 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
369 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
370 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
371 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
372 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
373 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
374 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
375 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
376 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
377 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
378 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
379 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
380 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
381 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
385 + pinctrl_ecspi2: escpi2grp {
387 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
388 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
389 + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
390 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1
394 + pinctrl_flexcan1: flexcan1grp {
396 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
397 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
398 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0
402 + pinctrl_gpio_leds: gpioledsgrp {
404 + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
405 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
406 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
410 + pinctrl_gpmi_nand: gpminandgrp {
412 + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
413 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
414 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
415 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
416 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
417 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
418 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
419 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
420 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
421 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
422 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
423 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
424 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
425 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
426 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
430 + pinctrl_i2c1: i2c1grp {
432 + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
433 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
434 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0
438 + pinctrl_i2c2: i2c2grp {
440 + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
441 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
445 + pinctrl_i2c3: i2c3grp {
447 + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
448 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
452 + pinctrl_pcie: pciegrp {
454 + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
455 + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
459 + pinctrl_pps: ppsgrp {
461 + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1
465 + pinctrl_pwm1: pwm1grp {
467 + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
471 + pinctrl_pwm2: pwm2grp {
473 + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
477 + pinctrl_pwm3: pwm3grp {
479 + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
483 + pinctrl_pwm4: pwm4grp {
485 + MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
489 + pinctrl_uart1: uart1grp {
491 + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
492 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
493 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b1
497 + pinctrl_uart2: uart2grp {
499 + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
500 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
501 + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b1
505 + pinctrl_uart5: uart5grp {
507 + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
508 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
512 + pinctrl_usbotg: usbotggrp {
514 + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059
518 + pinctrl_usdhc3: usdhc3grp {
520 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
521 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
522 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
523 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
524 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
525 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
526 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
527 + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
531 + pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
533 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
534 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
535 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
536 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
537 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
538 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
539 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
540 + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
544 + pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
546 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
547 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
548 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
549 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
550 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
551 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
552 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
553 + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
557 + pinctrl_wdog: wdoggrp {
559 + MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0