1 Author: Tim Harvey <tharvey@gateworks.com>
2 Date: Thu May 15 00:12:26 2014 -0700
4 net: igb: add i210/i211 support for phy read/write
6 The i210/i211 uses the MDICNFG register for the phy address instead of the
9 Signed-off-by: Tim Harvey <tharvey@gateworks.com>
11 --- a/drivers/net/ethernet/intel/igb/e1000_phy.c
12 +++ b/drivers/net/ethernet/intel/igb/e1000_phy.c
13 @@ -129,7 +129,7 @@ out:
14 s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
16 struct e1000_phy_info *phy = &hw->phy;
18 + u32 i, mdicnfg, mdic = 0;
21 if (offset > MAX_PHY_REG_ADDRESS) {
22 @@ -142,11 +142,25 @@ s32 igb_read_phy_reg_mdic(struct e1000_h
23 * Control register. The MAC will take care of interfacing with the
24 * PHY to retrieve the desired data.
26 - mdic = ((offset << E1000_MDIC_REG_SHIFT) |
27 - (phy->addr << E1000_MDIC_PHY_SHIFT) |
28 - (E1000_MDIC_OP_READ));
29 + switch (hw->mac.type) {
32 + mdicnfg = rd32(E1000_MDICNFG);
33 + mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
34 + mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT);
35 + wr32(E1000_MDICNFG, mdicnfg);
36 + mdic = ((offset << E1000_MDIC_REG_SHIFT) |
37 + (E1000_MDIC_OP_READ));
40 + mdic = ((offset << E1000_MDIC_REG_SHIFT) |
41 + (phy->addr << E1000_MDIC_PHY_SHIFT) |
42 + (E1000_MDIC_OP_READ));
46 wr32(E1000_MDIC, mdic);
49 /* Poll the ready bit to see if the MDI read completed
50 * Increasing the time out as testing showed failures with
51 @@ -171,6 +185,18 @@ s32 igb_read_phy_reg_mdic(struct e1000_h
55 + switch (hw->mac.type) {
56 + /* restore MDICNFG to have phy's addr */
59 + mdicnfg = rd32(E1000_MDICNFG);
60 + mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
61 + mdicnfg |= (hw->phy.addr << E1000_MDICNFG_PHY_SHIFT);
62 + wr32(E1000_MDICNFG, mdicnfg);
70 @@ -185,7 +211,7 @@ out:
71 s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
73 struct e1000_phy_info *phy = &hw->phy;
75 + u32 i, mdicnfg, mdic = 0;
78 if (offset > MAX_PHY_REG_ADDRESS) {
79 @@ -198,12 +224,27 @@ s32 igb_write_phy_reg_mdic(struct e1000_
80 * Control register. The MAC will take care of interfacing with the
81 * PHY to retrieve the desired data.
83 - mdic = (((u32)data) |
84 - (offset << E1000_MDIC_REG_SHIFT) |
85 - (phy->addr << E1000_MDIC_PHY_SHIFT) |
86 - (E1000_MDIC_OP_WRITE));
87 + switch (hw->mac.type) {
90 + mdicnfg = rd32(E1000_MDICNFG);
91 + mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
92 + mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT);
93 + wr32(E1000_MDICNFG, mdicnfg);
94 + mdic = (((u32)data) |
95 + (offset << E1000_MDIC_REG_SHIFT) |
96 + (E1000_MDIC_OP_WRITE));
99 + mdic = (((u32)data) |
100 + (offset << E1000_MDIC_REG_SHIFT) |
101 + (phy->addr << E1000_MDIC_PHY_SHIFT) |
102 + (E1000_MDIC_OP_WRITE));
106 wr32(E1000_MDIC, mdic);
109 /* Poll the ready bit to see if the MDI read completed
110 * Increasing the time out as testing showed failures with
111 @@ -227,6 +268,18 @@ s32 igb_write_phy_reg_mdic(struct e1000_
115 + switch (hw->mac.type) {
116 + /* restore MDICNFG to have phy's addr */
119 + mdicnfg = rd32(E1000_MDICNFG);
120 + mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
121 + mdicnfg |= (hw->phy.addr << E1000_MDICNFG_PHY_SHIFT);
122 + wr32(E1000_MDICNFG, mdicnfg);