target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-ecw5211.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 #include "qcom-ipq4019.dtsi"
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/input/input.h>
   6 #include <dt-bindings/soc/qcom,tcsr.h>
   7
   8 / {
   9         model = "Edgecore ECW5211";
  10         compatible = "edgecore,ecw5211";
  11
  12         aliases {
  13                 led-boot = &led_power;
  14                 led-failsafe = &led_power;
  15                 led-running = &led_power;
  16                 led-upgrade = &led_power;
  17         };
  18
  19         chosen {
  20                 bootargs-append = " root=/dev/ubiblock0_1";
  21         };
  22
  23         keys {
  24                 compatible = "gpio-keys";
  25
  26                 reset {
  27                         label = "reset";
  28                         gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
  29                         linux,code = <KEY_RESTART>;
  30                 };
  31         };
  32
  33         leds {
  34                 compatible = "gpio-leds";
  35
  36                 led_power: power {
  37                         label = "yellow:power";
  38                         gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
  39                 };
  40
  41                 wlan2g {
  42                         label = "green:wlan2g";
  43                         gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
  44                         linux,default-trigger = "phy0tpt";
  45                 };
  46
  47                 wlan5g {
  48                         label = "green:wlan5g";
  49                         gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
  50                         linux,default-trigger = "phy1tpt";
  51                 };
  52         };
  53
  54         soc {
  55                 rng@22000 {
  56                         status = "okay";
  57                 };
  58
  59                 counter@4a1000 {
  60                         compatible = "qcom,qca-gcnt";
  61                         reg = <0x4a1000 0x4>;
  62                 };
  63
  64                 tcsr@1949000 {
  65                         compatible = "qcom,tcsr";
  66                         reg = <0x1949000 0x100>;
  67                         qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  68                 };
  69
  70                 tcsr@194b000 {
  71                         compatible = "qcom,tcsr";
  72                         reg = <0x194b000 0x100>;
  73                         qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
  74                 };
  75
  76                 ess_tcsr@1953000 {
  77                         compatible = "qcom,tcsr";
  78                         reg = <0x1953000 0x1000>;
  79                         qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  80                 };
  81
  82                 tcsr@1957000 {
  83                         compatible = "qcom,tcsr";
  84                         reg = <0x1957000 0x100>;
  85                         qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  86                 };
  87
  88                 usb2@60f8800 {
  89                         status = "okay";
  90                 };
  91
  92                 usb3@8af8800 {
  93                         status = "okay";
  94
  95                         dwc3@8a00000 {
  96                                 phys = <&usb3_hs_phy>;
  97                                 phy-names = "usb2-phy";
  98                         };
  99                 };
 100
 101                 crypto@8e3a000 {
 102                         status = "okay";
 103                 };
 104
 105                 watchdog@b017000 {
 106                         status = "okay";
 107                 };
 108         };
 109 };
 110
 111 &tlmm {
 112         mdio_pins: mdio_pinmux {
 113                 mux_mdio {
 114                         pins = "gpio53";
 115                         function = "mdio";
 116                         bias-pull-up;
 117                 };
 118
 119                 mux_mdc {
 120                         pins = "gpio52";
 121                         function = "mdc";
 122                         bias-pull-up;
 123                 };
 124         };
 125
 126         serial_pins: serial_pinmux {
 127                 mux {
 128                         pins = "gpio60", "gpio61";
 129                         function = "blsp_uart0";
 130                         bias-disable;
 131                 };
 132         };
 133
 134         spi0_pins: spi0_pinmux {
 135                 pin {
 136                         function = "blsp_spi0";
 137                         pins = "gpio55", "gpio56", "gpio57";
 138                         drive-strength = <2>;
 139                         bias-disable;
 140                 };
 141
 142                 pin_cs {
 143                         function = "gpio";
 144                         pins = "gpio54", "gpio4";
 145                         drive-strength = <2>;
 146                         bias-disable;
 147                         output-high;
 148                 };
 149         };
 150
 151         i2c0_pins: i2c0_pinmux {
 152                 mux_i2c {
 153                         function = "blsp_i2c0";
 154                         pins = "gpio58", "gpio59";
 155                         drive-strength = <16>;
 156                         bias-disable;
 157                 };
 158         };
 159 };
 160
 161 &blsp_dma {
 162         status = "okay";
 163 };
 164
 165 &blsp1_spi1 {
 166         status = "okay";
 167
 168         pinctrl-0 = <&spi0_pins>;
 169         pinctrl-names = "default";
 170         cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 4 GPIO_ACTIVE_HIGH>;
 171
 172         flash@0 {
 173                 compatible = "jedec,spi-nor";
 174                 reg = <0>;
 175                 spi-max-frequency = <24000000>;
 176
 177                 partitions {
 178                         compatible = "fixed-partitions";
 179                         #address-cells = <1>;
 180                         #size-cells = <1>;
 181
 182                         partition@0 {
 183                                 label = "0:SBL1";
 184                                 reg = <0x00000000 0x00040000>;
 185                                 read-only;
 186                         };
 187
 188                         partition@40000 {
 189                                 label = "0:MIBIB";
 190                                 reg = <0x00040000 0x00020000>;
 191                                 read-only;
 192                         };
 193
 194                         partition@60000 {
 195                                 label = "0:QSEE";
 196                                 reg = <0x00060000 0x00060000>;
 197                                 read-only;
 198                         };
 199
 200                         partition@c0000 {
 201                                 label = "0:CDT";
 202                                 reg = <0x000c0000 0x00010000>;
 203                                 read-only;
 204                         };
 205
 206                         partition@d0000 {
 207                                 label = "0:DDRPARAMS";
 208                                 reg = <0x000d0000 0x00010000>;
 209                                 read-only;
 210                         };
 211
 212                         partition@e0000 {
 213                                 label = "0:APPSBLENV"; /* uboot env */
 214                                 reg = <0x000e0000 0x00010000>;
 215                         };
 216
 217                         partition@f0000 {
 218                                 label = "0:APPSBL"; /* uboot */
 219                                 reg = <0x000f0000 0x00080000>;
 220                                 read-only;
 221                         };
 222
 223                         partition@170000 {
 224                                 label = "0:ART";
 225                                 reg = <0x00170000 0x00010000>;
 226                                 read-only;
 227                                 compatible = "nvmem-cells";
 228                                 #address-cells = <1>;
 229                                 #size-cells = <1>;
 230
 231                                 precal_art_1000: precal@1000 {
 232                                         reg = <0x1000 0x2f20>;
 233                                 };
 234
 235                                 precal_art_5000: precal@5000 {
 236                                         reg = <0x5000 0x2f20>;
 237                                 };
 238                         };
 239                 };
 240         };
 241
 242         flash@1 {
 243                 compatible = "spi-nand";
 244                 reg = <1>;
 245                 spi-max-frequency = <24000000>;
 246
 247                 partitions {
 248                         compatible = "fixed-partitions";
 249                         #address-cells = <1>;
 250                         #size-cells = <1>;
 251
 252                         partition@0 {
 253                                 label = "rootfs";
 254                                 reg = <0x00000000 0x04000000>;
 255                         };
 256                 };
 257         };
 258 };
 259
 260 &blsp1_i2c3 {
 261         status = "okay";
 262
 263         pinctrl-0 = <&i2c0_pins>;
 264         pinctrl-names = "default";
 265
 266         tpm@29 {
 267                 compatible = "atmel,at97sc3204t";
 268                 reg = <0x29>;
 269         };
 270 };
 271
 272 &blsp1_uart1 {
 273         status = "okay";
 274
 275         pinctrl-0 = <&serial_pins>;
 276         pinctrl-names = "default";
 277 };
 278
 279 &cryptobam {
 280         status = "okay";
 281 };
 282
 283 &mdio {
 284         status = "okay";
 285
 286         pinctrl-0 = <&mdio_pins>;
 287         pinctrl-names = "default";
 288 };
 289
 290 &wifi0 {
 291         status = "okay";
 292         nvmem-cell-names = "pre-calibration";
 293         nvmem-cells = <&precal_art_1000>;
 294 };
 295
 296 &wifi1 {
 297         status = "okay";
 298         nvmem-cell-names = "pre-calibration";
 299         nvmem-cells = <&precal_art_5000>;
 300         qcom,ath10k-calibration-variant = "ALFA-Network-AP120C-AC";
 301 };
 302
 303 &usb3_hs_phy {
 304         status = "okay";
 305 };
 306
 307 &usb2_hs_phy {
 308         status = "okay";
 309 };