1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 // Copyright (c) 2018, Robert Marko <robimarko@gmail.com>
4 #include "qcom-ipq4019.dtsi"
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/soc/qcom,tcsr.h>
18 pinctrl-0 = <&mdio_pins>;
19 pinctrl-names = "default";
23 compatible = "qcom,qca-gcnt";
28 compatible = "qcom,tcsr";
29 reg = <0x1949000 0x100>;
30 qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
36 compatible = "qcom,tcsr";
37 reg = <0x194b000 0x100>;
38 qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
42 compatible = "qcom,tcsr";
43 reg = <0x1953000 0x1000>;
44 qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
48 compatible = "qcom,tcsr";
49 reg = <0x1957000 0x100>;
50 qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
72 mdio_pins: mdio_pinmux {
84 pins = "gpio52", "gpio53";
89 serial_pins: serial_pinmux {
91 pins = "gpio60", "gpio61";
92 function = "blsp_uart0";
97 spi_0_pins: spi_0_pinmux {
99 function = "blsp_spi0";
100 pins = "gpio55", "gpio56", "gpio57";
101 drive-strength = <2>;
107 pins = "gpio54", "gpio59";
108 drive-strength = <2>;
122 pinctrl-0 = <&spi_0_pins>;
123 pinctrl-names = "default";
124 cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 59 GPIO_ACTIVE_HIGH>;
129 compatible = "jedec,spi-nor";
131 spi-max-frequency = <24000000>;
134 compatible = "fixed-partitions";
135 #address-cells = <1>;
140 reg = <0x00000000 0x00040000>;
146 reg = <0x00040000 0x00020000>;
152 reg = <0x00060000 0x00060000>;
158 reg = <0x000c0000 0x00010000>;
164 reg = <0x000d0000 0x00010000>;
169 label = "APPSBLENV"; /* uboot env*/
170 reg = <0x000e0000 0x00010000>;
175 label = "APPSBL"; /* uboot */
176 reg = <0x000f0000 0x00080000>;
182 reg = <0x00170000 0x00010000>;
184 compatible = "nvmem-cells";
185 #address-cells = <1>;
188 precal_art_1000: precal@1000 {
189 reg = <0x1000 0x2f20>;
192 precal_art_5000: precal@5000 {
193 reg = <0x5000 0x2f20>;
202 compatible = "spi-nand";
204 spi-max-frequency = <24000000>;
207 compatible = "fixed-partitions";
208 #address-cells = <1>;
213 reg = <0x00000000 0x08000000>;
222 pinctrl-0 = <&serial_pins>;
223 pinctrl-names = "default";
232 nvmem-cell-names = "pre-calibration";
233 nvmem-cells = <&precal_art_1000>;
234 qcom,ath10k-calibration-variant = "8devices-Jalapeno";
239 nvmem-cell-names = "pre-calibration";
240 nvmem-cells = <&precal_art_5000>;
241 qcom,ath10k-calibration-variant = "8devices-Jalapeno";