1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 // Copyright (c) 2022, Pawel Dembicki <paweldembicki@gmail.com>.
3 // Copyright (c) 2022, Giammarco Marzano <stich86@gmail.com>.
4 // Copyright (c) 2023, Andreas Böhler <dev@aboehler.at>
6 #include "qcom-ipq4019.dtsi"
7 #include <dt-bindings/soc/qcom,tcsr.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/leds/common.h>
13 model = "ZTE MF287Plus";
14 compatible = "zte,mf287plus";
17 led-boot = &led_status;
18 led-failsafe = &led_status;
19 led-running = &led_status;
20 led-upgrade = &led_status;
25 * bootargs forced by u-boot bootipq command:
26 * 'ubi.mtd=rootfs root=mtd:ubi_rootfs rootfstype=squashfs rootwait'
28 bootargs-append = " root=/dev/ubiblock0_1";
32 * This node is used to restart modem module to avoid anomalous
33 * behaviours on initial communication.
36 compatible = "gpio-restart";
37 gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
41 compatible = "gpio-leds";
45 function = LED_FUNCTION_POWER;
46 color = <LED_COLOR_ID_BLUE>;
47 gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
52 compatible = "gpio-keys";
56 linux,code = <KEY_RESTART>;
57 gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
62 linux,code = <KEY_WPS_BUTTON>;
63 gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
73 compatible = "qcom,tcsr";
74 reg = <0x1949000 0x100>;
75 qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
80 compatible = "qcom,tcsr";
81 reg = <0x194b000 0x100>;
82 qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
87 compatible = "qcom,tcsr";
88 reg = <0x1953000 0x1000>;
89 qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
93 compatible = "qcom,tcsr";
94 reg = <0x1957000 0x100>;
95 qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
121 pinctrl-0 = <&spi_0_pins>;
122 pinctrl-names = "default";
124 cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
125 <&tlmm 59 GPIO_ACTIVE_HIGH>,
126 <&tlmm 1 GPIO_ACTIVE_HIGH>;
129 compatible = "jedec,spi-nor";
130 #address-cells = <1>;
133 spi-max-frequency = <24000000>;
136 compatible = "fixed-partitions";
137 #address-cells = <1>;
148 reg = <0x40000 0x20000>;
154 reg = <0x60000 0x60000>;
160 reg = <0xc0000 0x10000>;
165 label = "0:DDRPARAMS";
166 reg = <0xd0000 0x10000>;
171 label = "0:APPSBLENV";
172 reg = <0xe0000 0x10000>;
178 reg = <0xf0000 0xc0000>;
183 label = "0:reserved1";
184 reg = <0x1b0000 0x50000>;
190 spi-nand@1 { /* flash@1 ? */
191 compatible = "spi-nand";
193 spi-max-frequency = <24000000>;
196 compatible = "fixed-partitions";
197 #address-cells = <1>;
202 reg = <0x0 0x140000>;
208 reg = <0x140000 0x140000>;
210 compatible = "nvmem-cells";
211 #address-cells = <1>;
214 precal_art_1000: precal@1000 {
215 reg = <0x1000 0x2f20>;
218 precal_art_5000: precal@5000 {
219 reg = <0x5000 0x2f20>;
225 reg = <0x280000 0x140000>;
227 compatible = "nvmem-cells";
228 #address-cells = <1>;
231 macaddr_mac_0: macaddr@0 {
238 reg = <0x3c0000 0x600000>;
244 reg = <0x9c0000 0x140000>;
249 reg = <0xb00000 0x800000>;
254 reg = <0x1300000 0x2200000>;
259 reg = <0x3500000 0x1900000>;
264 reg = <0x4e00000 0x3200000>;
270 #address-cells = <1>;
273 compatible = "silabs,em3581";
275 spi-max-frequency = <12000000>;
280 pinctrl-0 = <&serial_pins>;
281 pinctrl-names = "default";
295 nvmem-cell-names = "mac-address";
296 nvmem-cells = <&macaddr_mac_0>;
297 mac-address-increment = <2>;
333 serial_pins: serial_pinmux {
335 pins = "gpio60", "gpio61";
336 function = "blsp_uart0";
341 spi_0_pins: spi_0_pinmux {
343 function = "blsp_spi0";
344 pins = "gpio55", "gpio56", "gpio57";
345 drive-strength = <12>;
351 pins = "gpio54", "gpio59", "gpio1";
352 drive-strength = <2>;
373 nvmem-cell-names = "pre-calibration", "mac-address";
374 nvmem-cells = <&precal_art_1000>, <&macaddr_mac_0>;
375 qcom,ath10k-calibration-variant = "zte,mf287plus";
380 nvmem-cell-names = "pre-calibration", "mac-address";
381 nvmem-cells = <&precal_art_5000>, <&macaddr_mac_0>;
382 mac-address-increment = <1>;
383 qcom,ath10k-calibration-variant = "zte,mf287plus";