1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 // Copyright (c) 2022, Pawel Dembicki <paweldembicki@gmail.com>.
3 // Copyright (c) 2022, Giammarco Marzano <stich86@gmail.com>.
4 // Copyright (c) 2023, Andreas Böhler <dev@aboehler.at>
6 #include "qcom-ipq4018-mf287.dtsi"
9 model = "ZTE MF287Plus";
10 compatible = "zte,mf287plus";
13 * This node is used to restart modem module to avoid anomalous
14 * behaviours on initial communication.
17 compatible = "gpio-restart";
18 gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
23 gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
27 gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
31 gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
35 pinctrl-0 = <&spi_0_pins>;
36 pinctrl-names = "default";
38 cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
39 <&tlmm 59 GPIO_ACTIVE_HIGH>,
40 <&tlmm 1 GPIO_ACTIVE_HIGH>;
43 compatible = "jedec,spi-nor";
47 spi-max-frequency = <24000000>;
50 compatible = "fixed-partitions";
62 reg = <0x40000 0x20000>;
68 reg = <0x60000 0x60000>;
74 reg = <0xc0000 0x10000>;
79 label = "0:DDRPARAMS";
80 reg = <0xd0000 0x10000>;
85 label = "0:APPSBLENV";
86 reg = <0xe0000 0x10000>;
92 reg = <0xf0000 0xc0000>;
97 label = "0:reserved1";
98 reg = <0x1b0000 0x50000>;
104 spi-nand@1 { /* flash@1 ? */
105 compatible = "spi-nand";
107 spi-max-frequency = <24000000>;
110 compatible = "fixed-partitions";
111 #address-cells = <1>;
116 reg = <0x0 0x140000>;
122 reg = <0x140000 0x140000>;
124 compatible = "nvmem-cells";
125 #address-cells = <1>;
128 precal_art_1000: precal@1000 {
129 reg = <0x1000 0x2f20>;
132 precal_art_5000: precal@5000 {
133 reg = <0x5000 0x2f20>;
139 reg = <0x280000 0x140000>;
141 compatible = "nvmem-cells";
142 #address-cells = <1>;
145 macaddr_mac_0: macaddr@0 {
152 reg = <0x3c0000 0x600000>;
158 reg = <0x9c0000 0x140000>;
163 reg = <0xb00000 0x800000>;
168 reg = <0x1300000 0x2200000>;
173 reg = <0x3500000 0x1900000>;
178 reg = <0x4e00000 0x3200000>;
184 #address-cells = <1>;
187 compatible = "silabs,em3581";
189 spi-max-frequency = <12000000>;
194 serial_pins: serial_pinmux {
196 pins = "gpio60", "gpio61";
197 function = "blsp_uart0";
202 spi_0_pins: spi_0_pinmux {
204 function = "blsp_spi0";
205 pins = "gpio55", "gpio56", "gpio57";
206 drive-strength = <12>;
212 pins = "gpio54", "gpio59", "gpio1";
213 drive-strength = <2>;