target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-wrtq-329acn.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 #include "qcom-ipq4019.dtsi"
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/input/input.h>
   6 #include <dt-bindings/soc/qcom,tcsr.h>
   7
   8 / {
   9         model = "Luma Home WRTQ-329ACN";
  10         compatible = "luma,wrtq-329acn";
  11
  12         i2c-gpio {
  13                 compatible = "i2c-gpio";
  14                 sda-gpios = <&tlmm 1 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
  15                 scl-gpios = <&tlmm 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 /* No driver exists */
  20                 led_ring@48 {
  21                         compatible = "ti,msp430";
  22                         reg = <0x48>;
  23                 };
  24
  25                 eeprom@50 {
  26                         compatible = "atmel,24c16";
  27                         reg = <0x50>;
  28                         pagesize = <16>;
  29                         read-only;
  30                 };
  31         };
  32
  33         keys {
  34                 compatible = "gpio-keys";
  35
  36                 reset {
  37                         label = "reset";
  38                         gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
  39                         linux,code = <KEY_RESTART>;
  40                 };
  41         };
  42
  43         soc {
  44                 rng@22000 {
  45                         status = "okay";
  46                 };
  47
  48                 mdio@90000 {
  49                         status = "okay";
  50
  51                         /delete-node/ ethernet-phy@0;
  52                         /delete-node/ ethernet-phy@1;
  53                         /delete-node/ ethernet-phy@3;
  54                 };
  55
  56                 ess-psgmii@98000 {
  57                         status = "okay";
  58                 };
  59
  60                 tcsr@1949000 {
  61                         compatible = "qcom,tcsr";
  62                         reg = <0x1949000 0x100>;
  63                         qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  64                 };
  65
  66                 tcsr@194b000 {
  67                         compatible = "qcom,tcsr";
  68                         reg = <0x194b000 0x100>;
  69                         qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
  70                 };
  71
  72                 ess_tcsr@1953000 {
  73                         compatible = "qcom,tcsr";
  74                         reg = <0x1953000 0x1000>;
  75                         qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  76                 };
  77
  78                 tcsr@1957000 {
  79                         compatible = "qcom,tcsr";
  80                         reg = <0x1957000 0x100>;
  81                         qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  82                 };
  83
  84                 usb2@60f8800 {
  85                         status = "okay";
  86                 };
  87
  88                 usb3@8af8800 {
  89                         status = "okay";
  90                 };
  91
  92                 crypto@8e3a000 {
  93                         status = "okay";
  94                 };
  95
  96                 watchdog@b017000 {
  97                         status = "okay";
  98                 };
  99
 100                 ess-switch@c000000 {
 101                         status = "okay";
 102
 103                         switch_lan_bmp = <0x1e>;
 104                         switch_wan_bmp = <0x20>;
 105                 };
 106
 107                 edma@c080000 {
 108                         status = "okay";
 109                 };
 110         };
 111 };
 112
 113 &blsp_dma {
 114         status = "okay";
 115 };
 116
 117
 118 &blsp1_spi1 {
 119         status = "okay";
 120
 121         cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
 122                    <&tlmm 59 GPIO_ACTIVE_HIGH>;
 123         pinctrl-0 = <&spi0_pins>;
 124         pinctrl-names = "default";
 125
 126         flash@0 {
 127                 compatible = "jedec,spi-nor";
 128                 reg = <0>;
 129                 spi-max-frequency = <24000000>;
 130
 131                 partitions {
 132                         compatible = "fixed-partitions";
 133                         #address-cells = <1>;
 134                         #size-cells = <1>;
 135
 136                         partition@0 {
 137                                 label = "0:SBL1";
 138                                 reg = <0x000000 0x040000>;
 139                                 read-only;
 140                         };
 141
 142                         partition@40000 {
 143                                 label = "0:MIBIB";
 144                                 reg = <0x040000 0x020000>;
 145                                 read-only;
 146                         };
 147
 148                         partition@60000 {
 149                                 label = "0:QSEE";
 150                                 reg = <0x060000 0x060000>;
 151                                 read-only;
 152                         };
 153
 154                         partition@c0000 {
 155                                 label = "0:CDT";
 156                                 reg = <0x0c0000 0x010000>;
 157                                 read-only;
 158                         };
 159
 160                         partition@d0000 {
 161                                 label = "0:DDRPARAMS";
 162                                 reg = <0x0d0000 0x010000>;
 163                                 read-only;
 164                         };
 165
 166                         partition@e0000 {
 167                                 label = "0:APPSBLENV";
 168                                 reg = <0x0e0000 0x010000>;
 169                         };
 170
 171                         partition@f0000 {
 172                                 label = "0:APPSBL";
 173                                 reg = <0x0f0000 0x080000>;
 174                                 read-only;
 175                         };
 176
 177                         partition@170000 {
 178                                 label = "0:ART";
 179                                 reg = <0x170000 0x010000>;
 180                                 read-only;
 181                                 compatible = "nvmem-cells";
 182                                 #address-cells = <1>;
 183                                 #size-cells = <1>;
 184
 185                                 macaddr_art_0: macaddr@0{
 186                                         reg = <0x0000 0x0006>;
 187                                 };
 188
 189                                 macaddr_art_6: macaddr@6{
 190                                         reg = <0x0006 0x0006>;
 191                                 };
 192
 193                                 precal_art_1000: precal@1000 {
 194                                         reg = <0x1000 0x2f20>;
 195                                 };
 196
 197                                 precal_art_5000: precal@5000 {
 198                                         reg = <0x5000 0x2f20>;
 199                                 };
 200                         };
 201                 };
 202         };
 203
 204         flash@1 {
 205                 status = "okay";
 206
 207                 compatible = "spi-nand";
 208                 reg = <1>;
 209                 spi-max-frequency = <24000000>;
 210
 211                 partitions {
 212                         compatible = "fixed-partitions";
 213                         #address-cells = <1>;
 214                         #size-cells = <1>;
 215
 216                         partition@0 {
 217                                 label = "ubi";
 218                                 reg = <0x0000000 0x8000000>;
 219                         };
 220                 };
 221         };
 222 };
 223
 224 &blsp1_uart1 {
 225         status = "okay";
 226
 227         pinctrl-0 = <&serial0_pins>;
 228         pinctrl-names = "default";
 229 };
 230
 231 &cryptobam {
 232         status = "okay";
 233 };
 234
 235 &gmac0 {
 236         qcom,phy_mdio_addr = <2>;
 237         qcom,poll_required = <1>;
 238         nvmem-cell-names = "mac-address";
 239         nvmem-cells = <&macaddr_art_6>;
 240 };
 241
 242 &gmac1 {
 243         qcom,phy_mdio_addr = <4>;
 244         qcom,poll_required = <1>;
 245         nvmem-cell-names = "mac-address";
 246         nvmem-cells = <&macaddr_art_0>;
 247 };
 248
 249 &tlmm {
 250         serial0_pins: serial0_pinmux {
 251                 mux {
 252                         function = "blsp_uart0";
 253                         pins = "gpio60", "gpio61";
 254                         bias-disable;
 255                 };
 256         };
 257
 258         spi0_pins: spi0_pinmux {
 259                 mux {
 260                         function = "blsp_spi0";
 261                         pins = "gpio55", "gpio56", "gpio57";
 262                         bias-disable;
 263                         drive-strength = <12>;
 264                 };
 265
 266                 mux_cs {
 267                         function = "gpio";
 268                         pins = "gpio54", "gpio59";
 269                         bias-disable;
 270                         drive-strength = <2>;
 271                         output-high;
 272                 };
 273         };
 274 };
 275
 276 &usb2_hs_phy {
 277         status = "okay";
 278 };
 279
 280 &usb3_hs_phy {
 281         status = "okay";
 282 };
 283
 284 &usb3_ss_phy {
 285         status = "okay";
 286 };
 287
 288 &wifi0 {
 289         status = "okay";
 290         nvmem-cell-names = "pre-calibration";
 291         nvmem-cells = <&precal_art_1000>;
 292         qcom,ath10k-calibration-variant = "Luma-WRTQ-329ACN";
 293 };
 294
 295 &wifi1 {
 296         status = "okay";
 297         nvmem-cell-names = "pre-calibration";
 298         nvmem-cells = <&precal_art_5000>;
 299         qcom,ath10k-calibration-variant = "Luma-WRTQ-329ACN";
 300 };