1 /* SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright (c) 2018 Peng Zhang <sd20@qxwlan.com>
7 #include "qcom-ipq4019-e2600ac.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
12 model = "Qxwlan E2600AC c2";
13 compatible = "qxwlan,e2600ac-c2";
17 pinctrl-0 = <&spi_0_pins>;
18 pinctrl-names = "default";
20 cs-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
24 compatible = "jedec,spi-nor";
25 spi-max-frequency = <24000000>;
28 compatible = "fixed-partitions";
39 reg = <0x40000 0x20000>;
44 reg = <0x60000 0x60000>;
49 reg = <0xc0000 0x10000>;
53 label = "0:DDRPARAMS";
54 reg = <0xd0000 0x10000>;
58 label = "0:APPSBLENV";
59 reg = <0xe0000 0x10000>;
64 reg = <0xf0000 0x80000>;
69 reg = <0x170000 0x10000>;
71 compatible = "nvmem-cells";
75 precal_art_1000: precal@1000 {
76 reg = <0x1000 0x2f20>;
79 precal_art_5000: precal@5000 {
80 reg = <0x5000 0x2f20>;
83 macaddr_gmac0: macaddr@0 {
87 macaddr_gmac1: macaddr@6 {
96 pinctrl-0 = <&nand_pins>;
97 pinctrl-names = "default";
102 compatible = "fixed-partitions";
103 #address-cells = <1>;
108 reg = <0x00000000 0x04000000>;
115 nand_pins: nand-pins {
118 pins = "gpio53", "gpio58", "gpio59";
124 pins = "gpio54", "gpio55", "gpio56",
125 "gpio57", "gpio60", "gpio61",
126 "gpio62", "gpio63", "gpio64",
127 "gpio65", "gpio66", "gpio67",
137 nvmem-cell-names = "pre-calibration";
138 nvmem-cells = <&precal_art_1000>;
139 qcom,ath10k-calibration-variant = "Qxwlan-E2600AC-C2";
144 nvmem-cell-names = "pre-calibration";
145 nvmem-cells = <&precal_art_5000>;
146 qcom,ath10k-calibration-variant = "Qxwlan-E2600AC-C2";
161 nvmem-cell-names = "mac-address";
162 nvmem-cells = <&macaddr_gmac0>;
169 nvmem-cell-names = "mac-address";
170 nvmem-cells = <&macaddr_gmac0>;
177 nvmem-cell-names = "mac-address";
178 nvmem-cells = <&macaddr_gmac1>;