63fd66901d8cbc9a821af5505ecb07d3ea81e18b
[openwrt/staging/jow.git] / target / linux / ipq40xx / files / arch / arm / boot / dts / qcom-ipq4019-eap2200.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "qcom-ipq4019.dtsi"
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
6
7 / {
8 model = "EnGenius EAP2200";
9 compatible = "engenius,eap2200";
10
11 aliases {
12 led-boot = &led_power;
13 led-failsafe = &led_power;
14 led-running = &led_power;
15 led-upgrade = &led_power;
16 };
17
18 keys {
19 compatible = "gpio-keys";
20
21 wps {
22 label = "wps";
23 gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
24 linux,code = <KEY_WPS_BUTTON>;
25 };
26 };
27
28 leds {
29 compatible = "gpio-leds";
30
31 led_power: power {
32 label = "amber:power";
33 gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
34 };
35
36 lan1 {
37 label = "blue:lan1";
38 gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
39 };
40
41 lan2 {
42 label = "blue:lan2";
43 gpios = <&tlmm 45 GPIO_ACTIVE_LOW>;
44 };
45
46 wlan2g {
47 label = "blue:wlan2g";
48 gpios = <&tlmm 46 GPIO_ACTIVE_LOW>;
49 linux,default-trigger = "phy0tpt";
50 };
51
52 wlan5g {
53 label = "yellow:wlan5g";
54 gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
55 linux,default-trigger = "phy1tpt";
56 };
57
58 wlan5g2 {
59 label = "yellow:wlan5g2";
60 gpios = <&tlmm 48 GPIO_ACTIVE_LOW>;
61 linux,default-trigger = "phy2tpt";
62 };
63
64 mode {
65 label = "blue:mode";
66 gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
67 };
68 };
69
70 soc {
71 rng@22000 {
72 status = "okay";
73 };
74
75 mdio@90000 {
76 status = "okay";
77 };
78
79 crypto@8e3a000 {
80 status = "okay";
81 };
82
83 watchdog@b017000 {
84 status = "okay";
85 };
86 };
87 };
88
89 &blsp_dma {
90 status = "okay";
91 };
92
93 &blsp1_spi1 {
94 pinctrl-0 = <&spi_0_pins>;
95 pinctrl-names = "default";
96 status = "okay";
97 cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
98
99 flash@0 {
100 #address-cells = <1>;
101 #size-cells = <1>;
102 compatible = "jedec,spi-nor";
103 reg = <0>;
104 spi-max-frequency = <24000000>;
105 partitions {
106 compatible = "fixed-partitions";
107 #address-cells = <1>;
108 #size-cells = <1>;
109
110 partition0@0 {
111 label = "0:SBL1";
112 reg = <0x00000000 0x00040000>;
113 read-only;
114 };
115 partition1@40000 {
116 label = "0:MIBIB";
117 reg = <0x00040000 0x00020000>;
118 read-only;
119 };
120 partition2@60000 {
121 label = "0:QSEE";
122 reg = <0x00060000 0x00060000>;
123 read-only;
124 };
125 partition3@c0000 {
126 label = "0:CDT";
127 reg = <0x000c0000 0x00010000>;
128 read-only;
129 };
130 partition4@d0000 {
131 label = "0:DDRPARAMS";
132 reg = <0x000d0000 0x00010000>;
133 read-only;
134 };
135 partition5@e0000 {
136 label = "0:APPSBLENV";
137 reg = <0x000e0000 0x00010000>;
138 read-only;
139 };
140 partition6@f0000 {
141 label = "0:APPSBL";
142 reg = <0x000f0000 0x00080000>;
143 read-only;
144 };
145 partition7@170000 {
146 label = "0:ART";
147 reg = <0x00170000 0x00010000>;
148 read-only;
149
150 nvmem-layout {
151 compatible = "fixed-layout";
152 #address-cells = <1>;
153 #size-cells = <1>;
154
155 precal_art_1000: precal@1000 {
156 reg = <0x1000 0x2f20>;
157 };
158
159 precal_art_5000: precal@5000 {
160 reg = <0x5000 0x2f20>;
161 };
162
163 precal_art_9000: precal@9000 {
164 reg = <0x9000 0x2f20>;
165 };
166 };
167 };
168 };
169 };
170 };
171
172 &blsp1_uart1 {
173 pinctrl-0 = <&serial_0_pins>;
174 pinctrl-names = "default";
175 status = "okay";
176 };
177
178 &cryptobam {
179 status = "okay";
180 };
181
182 &nand {
183 pinctrl-0 = <&nand_pins>;
184 pinctrl-names = "default";
185 status = "okay";
186
187 nand@0 {
188 partitions {
189 compatible = "fixed-partitions";
190 #address-cells = <1>;
191 #size-cells = <1>;
192
193 partition@0 {
194 label = "rootfs1";
195 reg = <0x00000000 0x04000000>;
196 };
197 partition@40000000 {
198 label = "ubi";
199 reg = <0x04000000 0x04000000>;
200 };
201
202 };
203 };
204 };
205
206 &pcie0 {
207 status = "okay";
208 perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
209 wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
210
211 bridge@0,0 {
212 reg = <0x00000000 0 0 0 0>;
213 #address-cells = <3>;
214 #size-cells = <2>;
215 ranges;
216
217 wifi2: wifi@1,0 {
218 compatible = "qcom,ath10k";
219 reg = <0x00010000 0 0 0 0>;
220 nvmem-cell-names = "pre-calibration";
221 nvmem-cells = <&precal_art_9000>;
222 ieee80211-freq-limit = <5470000 5875000>;
223 qcom,ath10k-calibration-variant = "EnGenius-EAP2200";
224 };
225 };
226 };
227
228 &qpic_bam {
229 status = "okay";
230 };
231
232 &tlmm {
233 nand_pins: nand_pins {
234 pullups {
235 pins = "gpio53", "gpio58", "gpio59";
236 function = "qpic";
237 bias-pull-up;
238 };
239
240 pulldowns {
241 pins = "gpio54", "gpio55", "gpio56",
242 "gpio57", "gpio60", "gpio61",
243 "gpio62", "gpio63", "gpio64",
244 "gpio65", "gpio66", "gpio67",
245 "gpio68", "gpio69";
246 function = "qpic";
247 bias-pull-down;
248 };
249 };
250
251 serial_0_pins: serial_pinmux {
252 mux {
253 pins = "gpio16", "gpio17";
254 function = "blsp_uart0";
255 bias-disable;
256 };
257 };
258
259 spi_0_pins: spi_0_pinmux {
260 pinmux {
261 function = "blsp_spi0";
262 pins = "gpio13", "gpio14", "gpio15";
263 drive-strength = <12>;
264 bias-disable;
265 };
266 pinmux_cs {
267 function = "gpio";
268 pins = "gpio12";
269 drive-strength = <2>;
270 bias-disable;
271 output-high;
272 };
273 };
274 };
275
276 &wifi0 {
277 status = "okay";
278 nvmem-cell-names = "pre-calibration";
279 nvmem-cells = <&precal_art_1000>;
280 qcom,ath10k-calibration-variant = "EnGenius-EAP2200";
281 };
282
283 &wifi1 {
284 status = "okay";
285 ieee80211-freq-limit = <5170000 5350000>;
286 nvmem-cell-names = "pre-calibration";
287 nvmem-cells = <&precal_art_5000>;
288 qcom,ath10k-calibration-variant = "EnGenius-EAP2200";
289 };