target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-gl-b2200.dts

   1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
   2
   3 #include "qcom-ipq4019.dtsi"
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/input/input.h>
   6 #include <dt-bindings/soc/qcom,tcsr.h>
   7
   8 / {
   9         model = "GL.iNet GL-B2200";
  10         compatible = "glinet,gl-b2200", "qcom,ipq4019";
  11
  12         memory {
  13                 device_type = "memory";
  14                 reg = <0x80000000 0x10000000>;
  15         };
  16
  17         chosen {
  18                 bootargs-append = " root=/dev/mmcblk0p2 rw rootwait clk_ignore_unused";
  19         };
  20
  21         soc {
  22                 rng@22000 {
  23                         status = "okay";
  24                 };
  25
  26                 mdio@90000 {
  27                         status = "okay";
  28                 };
  29
  30                 ess-psgmii@98000 {
  31                         status = "okay";
  32                 };
  33
  34                 tcsr@1949000 {
  35                         compatible = "qcom,tcsr";
  36                         reg = <0x1949000 0x100>;
  37                         qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  38                 };
  39
  40                 tcsr@194b000 {
  41                         /* select hostmode */
  42                         compatible = "qcom,tcsr";
  43                         reg = <0x194b000 0x100>;
  44                         qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
  45                         status = "okay";
  46                 };
  47
  48                 ess_tcsr@1953000 {
  49                         compatible = "qcom,tcsr";
  50                         reg = <0x1953000 0x1000>;
  51                         qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  52                 };
  53
  54                 tcsr@1957000 {
  55                         compatible = "qcom,tcsr";
  56                         reg = <0x1957000 0x100>;
  57                         qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  58                 };
  59
  60                 crypto@8e3a000 {
  61                         status = "okay";
  62                 };
  63
  64                 ess-switch@c000000 {
  65                         status = "okay";
  66                         switch_lan_bmp = <0x2e>;
  67                         switch_wan_bmp = <0x10>;
  68                 };
  69
  70                 edma@c080000 {
  71                         status = "okay";
  72                 };
  73         };
  74
  75         keys {
  76                 compatible = "gpio-keys";
  77
  78                 wps {
  79                         label = "wps";
  80                         gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
  81                         linux,code = <KEY_WPS_BUTTON>;
  82                         linux,input-type = <1>;
  83                 };
  84
  85                 reset {
  86                         label = "reset";
  87                         gpios = <&tlmm 40 GPIO_ACTIVE_LOW>;
  88                         linux,code = <KEY_RESTART>;
  89                         linux,input-type = <1>;
  90                 };
  91         };
  92
  93         leds {
  94                 compatible = "gpio-leds";
  95
  96                 power_blue {
  97                         label = "blue:power";
  98                         gpios = <&tlmm 57 GPIO_ACTIVE_HIGH>;
  99                         default-state = "on";
 100                 };
 101                 internet_blue {
 102                         label = "blue:internet";
 103                         gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>;
 104                 };
 105                 power_white {
 106                         label = "white:power";
 107                         gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
 108                 };
 109                 internet_white {
 110                         label = "white:internet";
 111                         gpios = <&tlmm 66 GPIO_ACTIVE_LOW>;
 112                 };
 113         };
 114 };
 115
 116 &gmac1 {
 117         qcom,phy_mdio_addr = <3>;
 118         qcom,poll_required = <1>;
 119         qcom,forced_speed = <1000>;
 120         qcom,forced_duplex = <1>;
 121         vlan_tag = <2 0x10>;
 122 };
 123
 124 &gmac0 {
 125         vlan_tag = <1 0x2e>;
 126 };
 127
 128 &vqmmc {
 129         status = "okay";
 130 };
 131
 132 &sdhci {
 133         status = "okay";
 134         pinctrl-0 = <&sd_pins>;
 135         pinctrl-names = "default";
 136         cd-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
 137         vqmmc-supply = <&vqmmc>;
 138 };
 139
 140 &blsp_dma {
 141         status = "okay";
 142 };
 143
 144 &cryptobam {
 145         status = "okay";
 146 };
 147
 148 &blsp1_spi1 {
 149         pinctrl-0 = <&spi_0_pins>;
 150         pinctrl-names = "default";
 151         status = "okay";
 152         cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
 153
 154         flash@0 {
 155                 compatible = "jedec,spi-nor";
 156                 reg = <0>;
 157                 spi-max-frequency = <24000000>;
 158
 159                 partitions {
 160                         compatible = "fixed-partitions";
 161                         #address-cells = <1>;
 162                         #size-cells = <1>;
 163
 164                         partition@0 {
 165                                 label = "SBL1";
 166                                 reg = <0x0 0x40000>;
 167                                 read-only;
 168                         };
 169
 170                         partition@40000 {
 171                                 label = "MIBIB";
 172                                 reg = <0x40000 0x20000>;
 173                                 read-only;
 174                         };
 175
 176                         partition@60000 {
 177                                 label = "QSEE";
 178                                 reg = <0x60000 0x60000>;
 179                                 read-only;
 180                         };
 181
 182                         partition@c0000 {
 183                                 label = "CDT";
 184                                 reg = <0xc0000 0x10000>;
 185                                 read-only;
 186                         };
 187
 188                         partition@d0000 {
 189                                 label = "DDRPARAMS";
 190                                 reg = <0xd0000 0x10000>;
 191                                 read-only;
 192                         };
 193
 194                         partition@e0000 {
 195                                 label = "APPSBLENV";
 196                                 reg = <0xe0000 0x10000>;
 197                                 read-only;
 198                         };
 199
 200                         partition@f0000 {
 201                                 label = "APPSBL";
 202                                 reg = <0xf0000 0x80000>;
 203                                 read-only;
 204                         };
 205
 206                         partition@170000 {
 207                                 label = "ART";
 208                                 reg = <0x170000 0x10000>;
 209                                 read-only;
 210                                 compatible = "nvmem-cells";
 211                                 #address-cells = <1>;
 212                                 #size-cells = <1>;
 213
 214                                 precal_art_1000: precal@1000 {
 215                                         reg = <0x1000 0x2f20>;
 216                                 };
 217
 218                                 precal_art_5000: precal@5000 {
 219                                         reg = <0x5000 0x2f20>;
 220                                 };
 221
 222                                 precal_art_9000: precal@9000 {
 223                                         reg = <0x9000 0x2f20>;
 224                                 };
 225                         };
 226                 };
 227         };
 228 };
 229
 230 &blsp1_spi2 {
 231         pinctrl-0 = <&spi_1_pins>;
 232         pinctrl-names = "default";
 233         status = "okay";
 234
 235         spidev1: spi@0 {
 236                 compatible = "siliconlabs,si3210";
 237                 reg = <0>;
 238                 spi-max-frequency = <24000000>;
 239         };
 240 };
 241
 242 &blsp1_uart1 {
 243         pinctrl-0 = <&serial_pins>;
 244         pinctrl-names = "default";
 245         status = "okay";
 246 };
 247
 248 &blsp1_uart2 {
 249         pinctrl-0 = <&serial_1_pins>;
 250         pinctrl-names = "default";
 251         status = "okay";
 252 };
 253
 254 &tlmm {
 255         serial_pins: serial_pinmux {
 256                 mux {
 257                         pins = "gpio16", "gpio17";
 258                         function = "blsp_uart0";
 259                         bias-disable;
 260                 };
 261         };
 262
 263         serial_1_pins: serial1_pinmux {
 264                 mux {
 265                         pins = "gpio8", "gpio9",
 266                                 "gpio10", "gpio11";
 267                         function = "blsp_uart1";
 268                         bias-disable;
 269                 };
 270         };
 271
 272         spi_0_pins: spi_0_pinmux {
 273                 pinmux {
 274                         function = "blsp_spi0";
 275                         pins = "gpio13", "gpio14", "gpio15";
 276                 };
 277                 pinmux_cs {
 278                         function = "gpio";
 279                         pins = "gpio12";
 280                 };
 281                 pinconf {
 282                         pins = "gpio13", "gpio14", "gpio15";
 283                         drive-strength = <12>;
 284                         bias-disable;
 285                 };
 286                 pinconf_cs {
 287                         pins = "gpio12";
 288                         drive-strength = <2>;
 289                         bias-disable;
 290                         output-high;
 291                 };
 292         };
 293
 294         spi_1_pins: spi_1_pinmux {
 295                 mux {
 296                         pins = "gpio44", "gpio46", "gpio47";
 297                         function = "blsp_spi1";
 298                         bias-disable;
 299                 };
 300                 cs {
 301                         pins = "gpio45";
 302                         function = "gpio";
 303                         bias-pull-up;
 304                 };
 305                 reset {
 306                         pins = "gpio43";
 307                         function = "gpio";
 308                         output-high;
 309                 };
 310                 mux_2 {
 311                         pins = "gpio35";
 312                         function = "gpio";
 313                         output-high;
 314                 };
 315                 host_int {
 316                         pins = "gpio2";
 317                         function = "gpio";
 318                         input;
 319                 };
 320                 wake {
 321                         pins = "gpio48";
 322                         function = "gpio";
 323                         output-high;
 324                 };
 325         };
 326
 327         sd_pins: sd_pins {
 328                 pinmux {
 329                         function = "sdio";
 330                         pins = "gpio23", "gpio24", "gpio25", "gpio26",
 331                                 "gpio29", "gpio30", "gpio31", "gpio32";
 332                         drive-strength = <10>;
 333                 };
 334
 335                 pinmux_sd_clk {
 336                         function = "sdio";
 337                         pins = "gpio27";
 338                         drive-strength = <16>;
 339                 };
 340
 341                 pinmux_sd7 {
 342                         function = "sdio";
 343                         pins = "gpio28";
 344                         drive-strength = <10>;
 345                         bias-disable;
 346                 };
 347         };
 348
 349 };
 350
 351 &pcie0 {
 352         status = "okay";
 353         perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
 354         wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
 355
 356         bridge@0,0 {
 357                 reg = <0x00000000 0 0 0 0>;
 358                 #address-cells = <3>;
 359                 #size-cells = <2>;
 360                 ranges;
 361
 362                 wifi2: wifi@1,0 {
 363                         status = "okay";
 364                         /* Bootlog shows this is a 168c:0056 - QCA 9888v2 */
 365                         compatible = "qcom,ath10k";
 366                         reg = <0x00010000 0 0 0 0>;
 367                         nvmem-cell-names = "pre-calibration";
 368                         nvmem-cells = <&precal_art_9000>;
 369                         qcom,ath10k-calibration-variant = "GL-B2200";
 370                         ieee80211-freq-limit = <5450000 5900000>;
 371                 };
 372         };
 373 };
 374
 375 &wifi0 {
 376         status = "okay";
 377         nvmem-cell-names = "pre-calibration";
 378         nvmem-cells = <&precal_art_1000>;
 379         qcom,ath10k-calibration-variant = "GL-B2200";
 380 };
 381
 382 &wifi1 {
 383         status = "okay";
 384         nvmem-cell-names = "pre-calibration";
 385         nvmem-cells = <&precal_art_5000>;
 386         qcom,ath10k-calibration-variant = "GL-B2200";
 387         ieee80211-freq-limit = <5100000 5400000>;
 388 };