1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 // Copyright (c) 2022, Pawel Dembicki <paweldembicki@gmail.com>.
3 // Copyright (c) 2022, Marcin Gajda <mgajda@o2.pl>.
6 #include "qcom-ipq4019.dtsi"
7 #include <dt-bindings/soc/qcom,tcsr.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/leds/common.h>
14 compatible = "zte,mf18a";
17 led-boot = &led_power;
18 led-failsafe = &led_power;
19 led-running = &led_power;
20 led-upgrade = &led_power;
25 * bootargs forced by u-boot bootipq command:
26 * 'ubi.mtd=rootfs root=mtd:ubi_rootfs rootfstype=squashfs rootwait'
28 bootargs-append = " root=/dev/ubiblock0_1";
32 compatible = "gpio-restart";
33 gpios = <&tlmm 8 GPIO_ACTIVE_HIGH>;
37 compatible = "gpio-leds";
40 label = "blue:internal";
41 gpios = <&tlmm 10 GPIO_ACTIVE_LOW>;
42 default-state = "keep";
47 gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>;
48 default-state = "keep";
52 function = LED_FUNCTION_WLAN;
54 gpios = <&tlmm 23 GPIO_ACTIVE_HIGH>;
55 linux,default-trigger = "phy0tpt";
60 gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>;
64 function = LED_FUNCTION_WLAN;
66 gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
67 linux,default-trigger = "phy1tpt";
72 gpios = <&tlmm 25 GPIO_ACTIVE_HIGH>;
77 gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
82 compatible = "gpio-keys";
86 linux,code = <KEY_RESTART>;
87 gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
92 linux,code = <KEY_WPS_BUTTON>;
93 gpios = <&tlmm 68 GPIO_ACTIVE_LOW>;
104 pinctrl-0 = <&mdio_pins>;
105 pinctrl-names = "default";
106 reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
107 reset-delay-us = <2000>;
111 compatible = "qcom,tcsr";
112 reg = <0x1949000 0x100>;
113 qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
117 /* select hostmode */
118 compatible = "qcom,tcsr";
119 reg = <0x194b000 0x100>;
120 qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
125 compatible = "qcom,tcsr";
126 reg = <0x1953000 0x1000>;
127 qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
131 compatible = "qcom,tcsr";
132 reg = <0x1957000 0x100>;
133 qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
159 pinctrl-0 = <&spi_0_pins>;
160 pinctrl-names = "default";
162 cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
165 /* u-boot is looking for "n25q128a11" property */
166 compatible = "jedec,spi-nor", "n25q128a11";
167 #address-cells = <1>;
170 spi-max-frequency = <24000000>;
173 compatible = "fixed-partitions";
174 #address-cells = <1>;
185 reg = <0x40000 0x20000>;
191 reg = <0x60000 0x60000>;
197 reg = <0xc0000 0x10000>;
202 label = "0:DDRPARAMS";
203 reg = <0xd0000 0x10000>;
208 label = "0:APPSBLENV";
209 reg = <0xe0000 0x10000>;
215 reg = <0xf0000 0xc0000>;
220 label = "0:reserved1";
221 reg = <0x1b0000 0x50000>;
229 pinctrl-0 = <&serial_pins>;
230 pinctrl-names = "default";
240 nvmem-cell-names = "mac-address";
241 nvmem-cells = <&macaddr_config_0 0>;
253 nvmem-cell-names = "mac-address";
254 nvmem-cells = <&macaddr_config_0 1>;
264 pinctrl-0 = <&nand_pins>;
265 pinctrl-names = "default";
270 compatible = "fixed-partitions";
271 #address-cells = <1>;
282 reg = <0xa0000 0x80000>;
286 compatible = "fixed-layout";
287 #address-cells = <1>;
290 precal_art_1000: precal@1000 {
291 reg = <0x1000 0x2f20>;
294 precal_art_9000: precal@9000 {
295 reg = <0x9000 0x2f20>;
302 reg = <0x120000 0x80000>;
306 compatible = "fixed-layout";
307 #address-cells = <1>;
310 macaddr_config_0: macaddr@0 {
311 compatible = "mac-base";
313 #nvmem-cell-cells = <1>;
320 reg = <0x1a0000 0xc0000>;
326 reg = <0x260000 0x400000>;
332 reg = <0x660000 0x400000>;
337 reg = <0xa60000 0xa0000>;
342 reg = <0xb00000 0x500000>;
348 reg = <0x1000000 0x800000>;
353 reg = <0x1800000 0x1d00000>;
358 reg = <0x3500000 0x1900000>;
363 reg = <0x4e00000 0x2800000>;
368 reg = <0x7600000 0xa00000>;
379 i2c_0_pins: i2c_0_pinmux {
381 pins = "gpio20", "gpio21";
382 function = "blsp_i2c0";
387 mdio_pins: mdio_pinmux {
401 nand_pins: nand_pins {
403 pins = "gpio52", "gpio53", "gpio58",
410 pins = "gpio54", "gpio55", "gpio56",
412 "gpio62", "gpio63", "gpio64",
413 "gpio65", "gpio66", "gpio67",
420 serial_pins: serial_pinmux {
422 pins = "gpio16", "gpio17";
423 function = "blsp_uart0";
428 spi_0_pins: spi_0_pinmux {
430 function = "blsp_spi0";
431 pins = "gpio13", "gpio14", "gpio15";
432 drive-strength = <12>;
439 drive-strength = <2>;
460 nvmem-cell-names = "pre-calibration", "mac-address";
461 nvmem-cells = <&precal_art_1000>, <&macaddr_config_0 2>;
462 qcom,ath10k-calibration-variant = "ZTE-MF18A";
465 //* This node is used for 5Ghz on QCA9982 */
468 perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
469 wake-gpio = <&tlmm 40 GPIO_ACTIVE_LOW>;
470 clkreq-gpio = <&tlmm 39 GPIO_ACTIVE_LOW>;
473 reg = <0x00000000 0 0 0 0>;
474 #address-cells = <3>;
479 compatible = "pci168c,0040";
480 nvmem-cell-names = "pre-calibration", "mac-address";
481 nvmem-cells = <&precal_art_9000>, <&macaddr_config_0 3>;
482 qcom,ath10k-calibration-variant = "ZTE-MF18A";
483 reg = <0x00010000 0 0 0 0>;