1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 // Copyright (c) 2022, Pawel Dembicki <paweldembicki@gmail.com>.
3 // Copyright (c) 2022, Marcin Gajda <mgajda@o2.pl>.
6 #include "qcom-ipq4019.dtsi"
7 #include <dt-bindings/soc/qcom,tcsr.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/leds/common.h>
14 compatible = "zte,mf18a";
17 led-boot = &led_power;
18 led-failsafe = &led_power;
19 led-running = &led_power;
20 led-upgrade = &led_power;
25 * bootargs forced by u-boot bootipq command:
26 * 'ubi.mtd=rootfs root=mtd:ubi_rootfs rootfstype=squashfs rootwait'
28 bootargs-append = " root=/dev/ubiblock0_1";
32 compatible = "gpio-restart";
33 gpios = <&tlmm 8 GPIO_ACTIVE_HIGH>;
37 compatible = "gpio-leds";
40 label = "blue:internal";
41 gpios = <&tlmm 10 GPIO_ACTIVE_LOW>;
42 default-state = "keep";
46 function = LED_FUNCTION_POWER;
47 color = <LED_COLOR_ID_BLUE>;
48 gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>;
49 default-state = "keep";
53 function = LED_FUNCTION_WLAN;
54 function = LED_FUNCTION_WLAN;
55 color = <LED_COLOR_ID_BLUE>;
56 gpios = <&tlmm 23 GPIO_ACTIVE_HIGH>;
57 linux,default-trigger = "phy0tpt";
61 function = LED_FUNCTION_WLAN;
62 color = <LED_COLOR_ID_RED>;
63 gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>;
67 function = LED_FUNCTION_WLAN;
69 gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
70 linux,default-trigger = "phy1tpt";
75 gpios = <&tlmm 25 GPIO_ACTIVE_HIGH>;
80 gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
85 compatible = "gpio-keys";
89 linux,code = <KEY_RESTART>;
90 gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
95 linux,code = <KEY_WPS_BUTTON>;
96 gpios = <&tlmm 68 GPIO_ACTIVE_LOW>;
107 pinctrl-0 = <&mdio_pins>;
108 pinctrl-names = "default";
109 reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
110 reset-delay-us = <2000>;
114 compatible = "qcom,tcsr";
115 reg = <0x1949000 0x100>;
116 qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
120 /* select hostmode */
121 compatible = "qcom,tcsr";
122 reg = <0x194b000 0x100>;
123 qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
128 compatible = "qcom,tcsr";
129 reg = <0x1953000 0x1000>;
130 qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
134 compatible = "qcom,tcsr";
135 reg = <0x1957000 0x100>;
136 qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
162 pinctrl-0 = <&spi_0_pins>;
163 pinctrl-names = "default";
165 cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
168 /* u-boot is looking for "n25q128a11" property */
169 compatible = "jedec,spi-nor", "n25q128a11";
170 #address-cells = <1>;
173 spi-max-frequency = <24000000>;
176 compatible = "fixed-partitions";
177 #address-cells = <1>;
188 reg = <0x40000 0x20000>;
194 reg = <0x60000 0x60000>;
200 reg = <0xc0000 0x10000>;
205 label = "0:DDRPARAMS";
206 reg = <0xd0000 0x10000>;
211 label = "0:APPSBLENV";
212 reg = <0xe0000 0x10000>;
218 reg = <0xf0000 0xc0000>;
223 label = "0:reserved1";
224 reg = <0x1b0000 0x50000>;
232 pinctrl-0 = <&serial_pins>;
233 pinctrl-names = "default";
243 nvmem-cell-names = "mac-address";
244 nvmem-cells = <&macaddr_config_0 0>;
256 nvmem-cell-names = "mac-address";
257 nvmem-cells = <&macaddr_config_0 1>;
267 pinctrl-0 = <&nand_pins>;
268 pinctrl-names = "default";
273 compatible = "fixed-partitions";
274 #address-cells = <1>;
285 reg = <0xa0000 0x80000>;
289 compatible = "fixed-layout";
290 #address-cells = <1>;
293 precal_art_1000: precal@1000 {
294 reg = <0x1000 0x2f20>;
297 precal_art_9000: precal@9000 {
298 reg = <0x9000 0x2f20>;
305 reg = <0x120000 0x80000>;
309 compatible = "fixed-layout";
310 #address-cells = <1>;
313 macaddr_config_0: macaddr@0 {
314 compatible = "mac-base";
316 #nvmem-cell-cells = <1>;
323 reg = <0x1a0000 0xc0000>;
329 reg = <0x260000 0x400000>;
335 reg = <0x660000 0x400000>;
340 reg = <0xa60000 0xa0000>;
345 reg = <0xb00000 0x500000>;
351 reg = <0x1000000 0x800000>;
356 reg = <0x1800000 0x1d00000>;
361 reg = <0x3500000 0x1900000>;
366 reg = <0x4e00000 0x2800000>;
371 reg = <0x7600000 0xa00000>;
382 i2c_0_pins: i2c_0_pinmux {
384 pins = "gpio20", "gpio21";
385 function = "blsp_i2c0";
390 mdio_pins: mdio_pinmux {
404 nand_pins: nand_pins {
406 pins = "gpio52", "gpio53", "gpio58",
413 pins = "gpio54", "gpio55", "gpio56",
415 "gpio62", "gpio63", "gpio64",
416 "gpio65", "gpio66", "gpio67",
423 serial_pins: serial_pinmux {
425 pins = "gpio16", "gpio17";
426 function = "blsp_uart0";
431 spi_0_pins: spi_0_pinmux {
433 function = "blsp_spi0";
434 pins = "gpio13", "gpio14", "gpio15";
435 drive-strength = <12>;
442 drive-strength = <2>;
463 nvmem-cell-names = "pre-calibration", "mac-address";
464 nvmem-cells = <&precal_art_1000>, <&macaddr_config_0 2>;
465 qcom,ath10k-calibration-variant = "ZTE-MF18A";
468 //* This node is used for 5Ghz on QCA9982 */
471 perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
472 wake-gpio = <&tlmm 40 GPIO_ACTIVE_LOW>;
473 clkreq-gpio = <&tlmm 39 GPIO_ACTIVE_LOW>;
476 reg = <0x00000000 0 0 0 0>;
477 #address-cells = <3>;
482 compatible = "pci168c,0040";
483 nvmem-cell-names = "pre-calibration", "mac-address";
484 nvmem-cells = <&precal_art_9000>, <&macaddr_config_0 3>;
485 qcom,ath10k-calibration-variant = "ZTE-MF18A";
486 reg = <0x00010000 0 0 0 0>;