1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 // Copyright (c) 2022, Pawel Dembicki <paweldembicki@gmail.com>.
3 // Copyright (c) 2022, Giammarco Marzano <stich86@gmail.com>.
5 #include "qcom-ipq4019.dtsi"
6 #include <dt-bindings/soc/qcom,tcsr.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/leds/common.h>
13 compatible = "zte,mf289f";
16 led-boot = &led_status;
17 led-failsafe = &led_status;
18 led-running = &led_status;
19 led-upgrade = &led_status;
24 * bootargs forced by u-boot bootipq command:
25 * 'ubi.mtd=rootfs root=mtd:ubi_rootfs rootfstype=squashfs rootwait'
27 bootargs-append = " root=/dev/ubiblock0_1";
31 * This node is used to restart modem module to avoid anomalous
32 * behaviours on initial communication.
35 compatible = "gpio-restart";
36 gpios = <&tlmm 8 GPIO_ACTIVE_HIGH>;
40 compatible = "gpio-leds";
44 function = LED_FUNCTION_POWER;
45 color = <LED_COLOR_ID_BLUE>;
46 gpios = <&tlmm 10 GPIO_ACTIVE_LOW>;
50 function = LED_FUNCTION_WLAN;
51 color = <LED_COLOR_ID_BLUE>;
52 gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
53 linux,default-trigger = "phy0tpt";
58 compatible = "gpio-keys";
62 linux,code = <KEY_RESTART>;
63 gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
68 linux,code = <KEY_WPS_BUTTON>;
69 gpios = <&tlmm 68 GPIO_ACTIVE_LOW>;
75 compatible = "qcom,tcsr";
76 reg = <0x1949000 0x100>;
77 qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
82 compatible = "qcom,tcsr";
83 reg = <0x194b000 0x100>;
84 qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
89 compatible = "qcom,tcsr";
90 reg = <0x1953000 0x1000>;
91 qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
95 compatible = "qcom,tcsr";
96 reg = <0x1957000 0x100>;
97 qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
108 pinctrl-0 = <&mdio_pins>;
109 pinctrl-names = "default";
110 reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
111 reset-delay-us = <2000>;
131 pinctrl-0 = <&spi_0_pins>;
132 pinctrl-names = "default";
134 cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>,
135 <&tlmm 54 GPIO_ACTIVE_HIGH>;
138 compatible = "jedec,spi-nor";
139 #address-cells = <1>;
142 spi-max-frequency = <24000000>;
145 compatible = "fixed-partitions";
146 #address-cells = <1>;
157 reg = <0x40000 0x20000>;
163 reg = <0x60000 0x60000>;
169 reg = <0xc0000 0x10000>;
174 label = "0:DDRPARAMS";
175 reg = <0xd0000 0x10000>;
180 label = "0:APPSBLENV";
181 reg = <0xe0000 0x10000>;
187 reg = <0xf0000 0xc0000>;
192 label = "0:reserved1";
193 reg = <0x1b0000 0x50000>;
199 spi-nand@1 { /* flash@1 ? */
200 compatible = "spi-nand";
202 spi-max-frequency = <24000000>;
205 compatible = "fixed-partitions";
206 #address-cells = <1>;
217 reg = <0xa0000 0x80000>;
219 compatible = "nvmem-cells";
220 #address-cells = <1>;
223 precal_art_1000: precal@1000 {
224 reg = <0x1000 0x2f20>;
227 precal_art_5000: precal@5000 {
228 reg = <0x5000 0x2f20>;
234 reg = <0x120000 0x80000>;
236 compatible = "nvmem-cells";
237 #address-cells = <1>;
240 macaddr_mac_0: macaddr@0 {
247 reg = <0x1a0000 0xc0000>;
253 reg = <0x260000 0x400000>;
259 reg = <0x660000 0x400000>;
264 reg = <0xa60000 0xa0000>;
269 reg = <0xb00000 0x500000>;
275 reg = <0x1000000 0x800000>;
280 reg = <0x1800000 0x1d00000>;
285 reg = <0x3500000 0x1900000>;
290 reg = <0x4e00000 0x3200000>;
297 pinctrl-0 = <&serial_pins>;
298 pinctrl-names = "default";
312 nvmem-cell-names = "mac-address";
313 nvmem-cells = <&macaddr_mac_0>;
325 nvmem-cell-names = "mac-address";
326 nvmem-cells = <&macaddr_mac_0>;
327 mac-address-increment = <1>;
341 i2c_0_pins: i2c_0_pinmux {
343 pins = "gpio20", "gpio21";
344 function = "blsp_i2c0";
349 mdio_pins: mdio_pinmux {
363 serial_pins: serial_pinmux {
365 pins = "gpio16", "gpio17";
366 function = "blsp_uart0";
371 spi_0_pins: spi_0_pinmux {
373 function = "blsp_spi0";
374 pins = "gpio13", "gpio14", "gpio15";
375 drive-strength = <12>;
381 pins = "gpio12", "gpio54";
382 drive-strength = <2>;
403 nvmem-cell-names = "pre-calibration", "mac-address";
404 nvmem-cells = <&precal_art_1000>, <&macaddr_mac_0>;
405 mac-address-increment = <2>;
406 qcom,ath10k-calibration-variant = "zte,mf289f";
409 /* This node is used only on AT2 version for 5Ghz on IPQ4019 with board-id=21 */
412 nvmem-cell-names = "pre-calibration", "mac-address";
413 nvmem-cells = <&precal_art_5000>, <&macaddr_mac_0>;
414 mac-address-increment = <3>;
415 qcom,ath10k-calibration-variant = "zte,mf289f";
418 /* This node is used only on AT1 version for 5Ghz on QCA9984 */
421 perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
422 wake-gpio = <&tlmm 40 GPIO_ACTIVE_LOW>;
423 clkreq-gpio = <&tlmm 39 GPIO_ACTIVE_LOW>;
426 reg = <0x00000000 0 0 0 0>;
427 #address-cells = <3>;
432 nvmem-cell-names = "mac-address";
433 nvmem-cells = <&macaddr_mac_0>;
434 mac-address-increment = <4>;
435 compatible = "qcom,ath10k";
436 reg = <0x00010000 0 0 0 0>;
437 qcom,ath10k-calibration-variant = "zte,mf289f";