1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 #include "qcom-ipq4019.dtsi"
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/soc/qcom,tcsr.h>
9 model = "EdgeCore OAP-100";
10 compatible = "edgecore,oap100";
13 led-boot = &led_system;
14 led-failsafe = &led_system;
15 led-running = &led_system;
16 led-upgrade = &led_system;
20 bootargs-append = " root=/dev/ubiblock0_1";
26 pinctrl-0 = <&mdio_pins>;
27 pinctrl-names = "default";
35 compatible = "qcom,tcsr";
36 reg = <0x1949000 0x100>;
37 qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
41 compatible = "qcom,tcsr";
42 reg = <0x1953000 0x1000>;
43 qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
47 compatible = "qcom,tcsr";
48 reg = <0x1957000 0x100>;
49 qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
54 compatible = "qcom,tcsr";
55 reg = <0x194b000 0x100>;
56 qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
69 #trigger-source-cells = <0>;
83 #trigger-source-cells = <0>;
88 #trigger-source-cells = <0>;
103 switch_mac_mode = <0x0>; /* mac mode for RGMII RMII */
104 switch_initvlas = <0x0007c 0x54>; /* port0 status */
105 switch_lan_bmp = <0x10>;
114 compatible = "gpio-keys";
118 linux,code = <KEY_RESTART>;
119 gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
120 linux,input-type = <1>;
125 compatible = "gpio-leds";
127 led_system: led_system {
128 label = "green:system";
129 gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
133 label = "blue:wlan2g";
134 gpios = <&tlmm 34 GPIO_ACTIVE_HIGH>;
138 label = "blue:wlan5g";
139 gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
144 compatible = "gpio-export";
148 gpio-export,name = "usb-power";
149 gpio-export,output = <1>;
150 gpios = <&tlmm 44 GPIO_ACTIVE_HIGH>;
154 gpio-export,name = "poe-power";
155 gpio-export,output = <0>;
156 gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
162 serial_0_pins: serial_pinmux {
164 pins = "gpio16", "gpio17";
165 function = "blsp_uart0";
170 spi_0_pins: spi_0_pinmux {
172 function = "blsp_spi0";
173 pins = "gpio13", "gpio14", "gpio15";
174 drive-strength = <12>;
181 drive-strength = <2>;
187 nand_pins: nand_pins {
189 pins = "gpio53", "gpio58", "gpio59";
195 pins = "gpio54", "gpio55", "gpio56",
196 "gpio57", "gpio60", "gpio61",
197 "gpio62", "gpio63", "gpio64",
198 "gpio65", "gpio66", "gpio67",
205 mdio_pins: mdio_pinmux {
224 pinctrl-0 = <&spi_0_pins>;
225 pinctrl-names = "default";
227 cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
230 #address-cells = <1>;
232 compatible = "jedec,spi-nor";
234 linux,modalias = "m25p80", "gd25q256";
235 spi-max-frequency = <24000000>;
238 compatible = "fixed-partitions";
239 #address-cells = <1>;
244 reg = <0x00000000 0x00040000>;
249 reg = <0x00040000 0x00020000>;
254 reg = <0x00060000 0x00060000>;
259 reg = <0x000c0000 0x00010000>;
263 label = "0:DDRPARAMS";
264 reg = <0x000d0000 0x00010000>;
268 label = "0:APPSBLENV";
269 reg = <0x000e0000 0x00010000>;
274 reg = <0x000f0000 0x00080000>;
279 reg = <0x00170000 0x00010000>;
281 compatible = "nvmem-cells";
282 #address-cells = <1>;
285 precal_art_1000: precal@1000 {
286 reg = <0x1000 0x2f20>;
289 precal_art_5000: precal@5000 {
290 reg = <0x5000 0x2f20>;
298 pinctrl-0 = <&nand_pins>;
299 pinctrl-names = "default";
304 compatible = "fixed-partitions";
305 #address-cells = <1>;
310 reg = <0x00000000 0x4000000>;
321 pinctrl-0 = <&serial_0_pins>;
322 pinctrl-names = "default";
332 nvmem-cell-names = "pre-calibration";
333 nvmem-cells = <&precal_art_1000>;
334 qcom,ath10k-calibration-variant = "Edgecore OAP100";
339 nvmem-cell-names = "pre-calibration";
340 nvmem-cells = <&precal_art_5000>;
341 qcom,ath10k-calibration-variant = "Edgecore OAP100";