1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 #include "qcom-ipq4019.dtsi"
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/soc/qcom,tcsr.h>
9 model = "EdgeCore OAP-100";
10 compatible = "edgecore,oap100";
13 led-boot = &led_system;
14 led-failsafe = &led_system;
15 led-running = &led_system;
16 led-upgrade = &led_system;
20 bootargs-append = " root=/dev/ubiblock0_1";
26 pinctrl-0 = <&mdio_pins>;
27 pinctrl-names = "default";
31 compatible = "qcom,tcsr";
32 reg = <0x1949000 0x100>;
33 qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
37 compatible = "qcom,tcsr";
38 reg = <0x1953000 0x1000>;
39 qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
43 compatible = "qcom,tcsr";
44 reg = <0x1957000 0x100>;
45 qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
50 compatible = "qcom,tcsr";
51 reg = <0x194b000 0x100>;
52 qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
65 #trigger-source-cells = <0>;
79 #trigger-source-cells = <0>;
84 #trigger-source-cells = <0>;
99 compatible = "gpio-keys";
103 linux,code = <KEY_RESTART>;
104 gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
105 linux,input-type = <1>;
110 compatible = "gpio-leds";
112 led_system: led_system {
113 label = "green:system";
114 gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
118 label = "blue:wlan2g";
119 gpios = <&tlmm 34 GPIO_ACTIVE_HIGH>;
123 label = "blue:wlan5g";
124 gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
129 compatible = "gpio-export";
133 gpio-export,name = "usb-power";
134 gpio-export,output = <1>;
135 gpios = <&tlmm 44 GPIO_ACTIVE_HIGH>;
139 gpio-export,name = "poe-power";
140 gpio-export,output = <0>;
141 gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
147 serial_0_pins: serial_pinmux {
149 pins = "gpio16", "gpio17";
150 function = "blsp_uart0";
155 spi_0_pins: spi_0_pinmux {
157 function = "blsp_spi0";
158 pins = "gpio13", "gpio14", "gpio15";
159 drive-strength = <12>;
166 drive-strength = <2>;
172 nand_pins: nand_pins {
174 pins = "gpio53", "gpio58", "gpio59";
180 pins = "gpio54", "gpio55", "gpio56",
181 "gpio57", "gpio60", "gpio61",
182 "gpio62", "gpio63", "gpio64",
183 "gpio65", "gpio66", "gpio67",
190 mdio_pins: mdio_pinmux {
209 pinctrl-0 = <&spi_0_pins>;
210 pinctrl-names = "default";
212 cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
215 #address-cells = <1>;
217 compatible = "jedec,spi-nor";
219 linux,modalias = "m25p80", "gd25q256";
220 spi-max-frequency = <24000000>;
223 compatible = "fixed-partitions";
224 #address-cells = <1>;
229 reg = <0x00000000 0x00040000>;
234 reg = <0x00040000 0x00020000>;
239 reg = <0x00060000 0x00060000>;
244 reg = <0x000c0000 0x00010000>;
248 label = "0:DDRPARAMS";
249 reg = <0x000d0000 0x00010000>;
253 label = "0:APPSBLENV";
254 reg = <0x000e0000 0x00010000>;
259 reg = <0x000f0000 0x00080000>;
264 reg = <0x00170000 0x00010000>;
266 compatible = "nvmem-cells";
267 #address-cells = <1>;
270 precal_art_1000: precal@1000 {
271 reg = <0x1000 0x2f20>;
274 precal_art_5000: precal@5000 {
275 reg = <0x5000 0x2f20>;
283 pinctrl-0 = <&nand_pins>;
284 pinctrl-names = "default";
289 compatible = "fixed-partitions";
290 #address-cells = <1>;
295 reg = <0x00000000 0x4000000>;
306 pinctrl-0 = <&serial_0_pins>;
307 pinctrl-names = "default";
317 nvmem-cell-names = "pre-calibration";
318 nvmem-cells = <&precal_art_1000>;
319 qcom,ath10k-calibration-variant = "Edgecore OAP100";
324 nvmem-cell-names = "pre-calibration";
325 nvmem-cells = <&precal_art_5000>;
326 qcom,ath10k-calibration-variant = "Edgecore OAP100";