1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for Meraki "Insect" series
5 * Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com>
6 * Copyright (C) 2017 Christian Lamparter <chunkeey@googlemail.com>
8 * Based on Cisco Meraki DTS from GPL release r25-linux-3.14-20170427
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without
12 * any warranty of any kind, whether express or implied.
15 #include "qcom-ipq4019.dtsi"
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/input/input.h>
18 #include <dt-bindings/soc/qcom,tcsr.h>
19 #include <dt-bindings/leds/common.h>
23 led-boot = &status_green;
24 led-failsafe = &status_red;
25 led-running = &status_green;
26 led-upgrade = &power_orange;
29 /* Do we really need this defined? */
31 device_type = "memory";
32 reg = <0x80000000 0x10000000>;
42 pinctrl-0 = <&mdio_pins>;
43 pinctrl-names = "default";
46 /* It is a 56-bit counter that supplies the count to the ARM arch
47 timers and without upstream driver */
49 compatible = "qcom,qca-gcnt";
54 compatible = "qcom,tcsr";
55 reg = <0x1953000 0x1000>;
56 qcom,ess-interface-select = <TCSR_ESS_PSGMII_RGMII5>;
60 compatible = "qcom,tcsr";
61 reg = <0x1949000 0x100>;
62 qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
66 compatible = "qcom,tcsr";
67 reg = <0x1957000 0x100>;
68 qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
72 pinctrl-0 = <&serial_1_pins>;
73 pinctrl-names = "default";
77 compatible = "ti,cc2650";
78 enable-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
92 compatible = "gpio-keys";
96 gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
97 linux,code = <KEY_RESTART>;
102 compatible = "gpio-leds";
104 power_orange: power {
105 label = "orange:power";
106 gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
117 pinctrl-0 = <&serial_0_pins>;
118 pinctrl-names = "default";
127 pinctrl-0 = <&i2c_0_pins>;
128 pinctrl-names = "default";
132 compatible = "atmel,24c64";
135 read-only; /* This holds our MAC & Meraki board-data */
136 #address-cells = <1>;
139 mac_address: mac-address@66 {
140 compatible = "mac-base";
142 #nvmem-cell-cells = <1>;
148 pinctrl-0 = <&i2c_1_pins>;
149 pinctrl-names = "default";
152 tricolor: led-controller@30 {
153 compatible = "ti,lp5562";
155 clock-mode = /bits/8 <2>;
156 #address-cells = <1>;
161 chan-name = "red:status";
162 led-cur = /bits/ 8 <0x20>;
163 max-cur = /bits/ 8 <0x60>;
165 color = <LED_COLOR_ID_RED>;
168 status_green: chan@1 {
169 chan-name = "green:status";
170 led-cur = /bits/ 8 <0x20>;
171 max-cur = /bits/ 8 <0x60>;
173 color = <LED_COLOR_ID_GREEN>;
177 chan-name = "blue:status";
178 led-cur = /bits/ 8 <0x20>;
179 max-cur = /bits/ 8 <0x60>;
181 color = <LED_COLOR_ID_BLUE>;
185 chan-name = "white:status";
186 led-cur = /bits/ 8 <0x20>;
187 max-cur = /bits/ 8 <0x60>;
189 color = <LED_COLOR_ID_WHITE>;
195 pinctrl-0 = <&nand_pins>;
196 pinctrl-names = "default";
201 compatible = "fixed-partitions";
202 #address-cells = <1>;
207 reg = <0x00000000 0x00100000>;
212 reg = <0x00100000 0x00100000>;
216 label = "bootconfig";
217 reg = <0x00200000 0x00100000>;
222 reg = <0x00300000 0x00100000>;
227 reg = <0x00400000 0x00100000>;
232 reg = <0x00500000 0x00080000>;
237 reg = <0x00580000 0x00080000>;
242 reg = <0x00600000 0x00080000>;
247 reg = <0x00700000 0x00200000>;
251 label = "u-boot-backup";
252 reg = <0x00900000 0x00200000>;
257 reg = <0x00b00000 0x00080000>;
262 reg = <0x00c00000 0x07000000>;
264 * Do not try to allocate the remaining
265 * 4 MiB to this ubi partition. It will
266 * confuse the u-boot and it might not
267 * find the kernel partition anymore.
276 perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
277 wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
280 reg = <0x00000000 0 0 0 0>;
281 #address-cells = <3>;
286 compatible = "qcom,ath10k";
288 reg = <0x00010000 0 0 0 0>;
289 nvmem-cells = <&mac_address 1>;
290 nvmem-cell-names = "mac-address";
301 * GPIO43 should be 0/1 whenever the unit is
302 * powered through PoE or AC-Adapter.
303 * That said, playing with this seems to
307 mdio_pins: mdio_pinmux {
320 serial_0_pins: serial_pinmux {
322 pins = "gpio16", "gpio17";
323 function = "blsp_uart0";
328 serial_1_pins: serial1_pinmux {
330 /* We use the i2c-0 pins for serial_1 */
331 pins = "gpio8", "gpio9";
332 function = "blsp_uart1";
337 i2c_0_pins: i2c_0_pinmux {
339 function = "blsp_i2c0";
340 pins = "gpio20", "gpio21";
343 pins = "gpio20", "gpio21";
344 drive-strength = <16>;
349 i2c_1_pins: i2c_1_pinmux {
351 function = "blsp_i2c1";
352 pins = "gpio34", "gpio35";
355 pins = "gpio34", "gpio35";
356 drive-strength = <16>;
361 nand_pins: nand_pins {
363 * There are 18 pins. 15 pins are common between LCD and NAND.
364 * The QPIC controller arbitrates between LCD and NAND. Of the
365 * remaining 4, 2 are for NAND and 2 are for LCD exclusively.
367 * The meraki source hints that the bluetooth module claims
368 * pin 52 as well. But sadly, there's no data whenever this
369 * is a NAND or LCD exclusive pin or not.
373 pins = "gpio52", "gpio53", "gpio58",
380 pins = "gpio54", "gpio55", "gpio56",
381 "gpio57", "gpio60", "gpio61",
382 "gpio62", "gpio63", "gpio64",
383 "gpio65", "gpio66", "gpio67",
393 qcom,ath10k-calibration-variant = "Meraki-MR33";
394 nvmem-cells = <&mac_address 2>;
395 nvmem-cell-names = "mac-address";
400 qcom,ath10k-calibration-variant = "Meraki-MR33";
401 nvmem-cells = <&mac_address 3>;
402 nvmem-cell-names = "mac-address";
407 nvmem-cells = <&mac_address 0>;
408 nvmem-cell-names = "mac-address";
414 /delete-property/ psgmii-ethphy;
421 phy-handle = <ðphy1>;
422 phy-mode = "rgmii-rxid";