1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for Meraki "Insect" series
5 * Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com>
6 * Copyright (C) 2017 Christian Lamparter <chunkeey@googlemail.com>
8 * Based on Cisco Meraki DTS from GPL release r25-linux-3.14-20170427
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without
12 * any warranty of any kind, whether express or implied.
15 #include "qcom-ipq4019.dtsi"
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/input/input.h>
18 #include <dt-bindings/soc/qcom,tcsr.h>
19 #include <dt-bindings/leds/common.h>
23 led-boot = &status_green;
24 led-failsafe = &status_red;
25 led-running = &status_green;
26 led-upgrade = &power_orange;
29 /* Do we really need this defined? */
31 device_type = "memory";
32 reg = <0x80000000 0x10000000>;
42 pinctrl-0 = <&mdio_pins>;
43 pinctrl-names = "default";
46 /* It is a 56-bit counter that supplies the count to the ARM arch
47 timers and without upstream driver */
49 compatible = "qcom,qca-gcnt";
54 compatible = "qcom,tcsr";
55 reg = <0x1953000 0x1000>;
56 qcom,ess-interface-select = <TCSR_ESS_PSGMII_RGMII5>;
60 compatible = "qcom,tcsr";
61 reg = <0x1949000 0x100>;
62 qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
66 compatible = "qcom,tcsr";
67 reg = <0x1957000 0x100>;
68 qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
72 pinctrl-0 = <&serial_1_pins>;
73 pinctrl-names = "default";
77 compatible = "ti,cc2650";
78 enable-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
92 compatible = "gpio-keys";
96 gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
97 linux,code = <KEY_RESTART>;
102 compatible = "gpio-leds";
104 power_orange: power {
105 label = "orange:power";
106 gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
117 pinctrl-0 = <&serial_0_pins>;
118 pinctrl-names = "default";
127 pinctrl-0 = <&i2c_0_pins>;
128 pinctrl-names = "default";
131 compatible = "atmel,24c64";
134 read-only; /* This holds our MAC & Meraki board-data */
139 pinctrl-0 = <&i2c_1_pins>;
140 pinctrl-names = "default";
143 tricolor: led-controller@30 {
144 compatible = "ti,lp5562";
146 clock-mode = /bits/8 <2>;
147 #address-cells = <1>;
152 chan-name = "red:status";
153 led-cur = /bits/ 8 <0x20>;
154 max-cur = /bits/ 8 <0x60>;
156 color = <LED_COLOR_ID_RED>;
159 status_green: chan@1 {
160 chan-name = "green:status";
161 led-cur = /bits/ 8 <0x20>;
162 max-cur = /bits/ 8 <0x60>;
164 color = <LED_COLOR_ID_GREEN>;
168 chan-name = "blue:status";
169 led-cur = /bits/ 8 <0x20>;
170 max-cur = /bits/ 8 <0x60>;
172 color = <LED_COLOR_ID_BLUE>;
176 chan-name = "white:status";
177 led-cur = /bits/ 8 <0x20>;
178 max-cur = /bits/ 8 <0x60>;
180 color = <LED_COLOR_ID_WHITE>;
186 pinctrl-0 = <&nand_pins>;
187 pinctrl-names = "default";
192 compatible = "fixed-partitions";
193 #address-cells = <1>;
198 reg = <0x00000000 0x00100000>;
203 reg = <0x00100000 0x00100000>;
207 label = "bootconfig";
208 reg = <0x00200000 0x00100000>;
213 reg = <0x00300000 0x00100000>;
218 reg = <0x00400000 0x00100000>;
223 reg = <0x00500000 0x00080000>;
228 reg = <0x00580000 0x00080000>;
233 reg = <0x00600000 0x00080000>;
238 reg = <0x00700000 0x00200000>;
242 label = "u-boot-backup";
243 reg = <0x00900000 0x00200000>;
248 reg = <0x00b00000 0x00080000>;
253 reg = <0x00c00000 0x07000000>;
255 * Do not try to allocate the remaining
256 * 4 MiB to this ubi partition. It will
257 * confuse the u-boot and it might not
258 * find the kernel partition anymore.
267 perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
268 wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
271 reg = <0x00000000 0 0 0 0>;
272 #address-cells = <3>;
277 compatible = "qcom,ath10k";
279 reg = <0x00010000 0 0 0 0>;
290 * GPIO43 should be 0/1 whenever the unit is
291 * powered through PoE or AC-Adapter.
292 * That said, playing with this seems to
296 mdio_pins: mdio_pinmux {
309 serial_0_pins: serial_pinmux {
311 pins = "gpio16", "gpio17";
312 function = "blsp_uart0";
317 serial_1_pins: serial1_pinmux {
319 /* We use the i2c-0 pins for serial_1 */
320 pins = "gpio8", "gpio9";
321 function = "blsp_uart1";
326 i2c_0_pins: i2c_0_pinmux {
328 function = "blsp_i2c0";
329 pins = "gpio20", "gpio21";
332 pins = "gpio20", "gpio21";
333 drive-strength = <16>;
338 i2c_1_pins: i2c_1_pinmux {
340 function = "blsp_i2c1";
341 pins = "gpio34", "gpio35";
344 pins = "gpio34", "gpio35";
345 drive-strength = <16>;
350 nand_pins: nand_pins {
352 * There are 18 pins. 15 pins are common between LCD and NAND.
353 * The QPIC controller arbitrates between LCD and NAND. Of the
354 * remaining 4, 2 are for NAND and 2 are for LCD exclusively.
356 * The meraki source hints that the bluetooth module claims
357 * pin 52 as well. But sadly, there's no data whenever this
358 * is a NAND or LCD exclusive pin or not.
362 pins = "gpio52", "gpio53", "gpio58",
369 pins = "gpio54", "gpio55", "gpio56",
370 "gpio57", "gpio60", "gpio61",
371 "gpio62", "gpio63", "gpio64",
372 "gpio65", "gpio66", "gpio67",
382 qcom,ath10k-calibration-variant = "Meraki-MR33";
387 qcom,ath10k-calibration-variant = "Meraki-MR33";