target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq40x9-dr40x9.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 #include "qcom-ipq4019.dtsi"
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/input/input.h>
   6 #include <dt-bindings/soc/qcom,tcsr.h>
   7
   8 / {
   9         model = "Wallystech DR40X9";
  10         compatible = "wallys,dr40x9";
  11
  12         chosen {
  13                 bootargs-append = " ubi.mtd=ubi root=/dev/ubiblock0_1";
  14         };
  15
  16         soc {
  17                 counter@4a1000 {
  18                         compatible = "qcom,qca-gcnt";
  19                         reg = <0x4a1000 0x4>;
  20                 };
  21
  22                 tcsr@1949000 {
  23                         compatible = "qcom,tcsr";
  24                         reg = <0x1949000 0x100>;
  25                         qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  26                 };
  27
  28                 tcsr@194b000 {
  29                         status = "okay";
  30
  31                         /* select hostmode */
  32                         compatible = "qcom,tcsr";
  33                         reg = <0x194b000 0x100>;
  34                         qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
  35                 };
  36
  37                 ess_tcsr@1953000 {
  38                         compatible = "qcom,tcsr";
  39                         reg = <0x1953000 0x1000>;
  40                         qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  41                 };
  42
  43                 tcsr@1957000 {
  44                         compatible = "qcom,tcsr";
  45                         reg = <0x1957000 0x100>;
  46                         qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  47                 };
  48         };
  49
  50         keys {
  51                 compatible = "gpio-keys";
  52
  53                 reset {
  54                         label = "reset";
  55                         gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
  56                         linux,code = <KEY_RESTART>;
  57                 };
  58         };
  59
  60         leds {
  61                 compatible = "gpio-leds";
  62
  63                 wlan2g {
  64                         label = "dr4029:green:wlan2g";
  65                         gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
  66                         linux,default-trigger = "phy0tpt";
  67                 };
  68
  69                 wlan5g {
  70                         label = "dr4029:green:wlan5g";
  71                         gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
  72                         linux,default-trigger = "phy1tpt";
  73                 };
  74
  75                 wlan2g-strength {
  76                         label = "dr4029:green:wlan2g-strength";
  77                         gpios = <&tlmm 36 GPIO_ACTIVE_LOW>;
  78                 };
  79
  80                 wlan5g-strength {
  81                         label = "dr4029:green:wlan5g-strength";
  82                         gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
  83                 };
  84         };
  85 };
  86
  87 &tlmm {
  88         mdio_pins: mdio_pinmux {
  89                 mux_1 {
  90                         pins = "gpio6";
  91                         function = "mdio";
  92                         bias-pull-up;
  93                 };
  94                 mux_2 {
  95                         pins = "gpio7";
  96                         function = "mdc";
  97                         bias-pull-up;
  98                 };
  99         };
 100
 101         serial0_pins: serial0_pinmux {
 102                 mux {
 103                         pins = "gpio16", "gpio17";
 104                         function = "blsp_uart0";
 105                         bias-disable;
 106                 };
 107         };
 108
 109         serial1_pins: serial1_pinmux {
 110                 mux {
 111                         pins = "gpio8", "gpio9";
 112                         function = "blsp_uart1";
 113                         bias-disable;
 114                 };
 115         };
 116
 117         spi_0_pins: spi_0_pinmux {
 118                 pinmux {
 119                         function = "blsp_spi0";
 120                         pins = "gpio13", "gpio14", "gpio15";
 121                         drive-strength = <12>;
 122                         bias-disable;
 123                 };
 124                 pinmux_cs {
 125                         function = "gpio";
 126                         pins = "gpio12";
 127                         drive-strength = <2>;
 128                         bias-disable;
 129                         output-high;
 130                 };
 131         };
 132
 133         nand_pins: nand_pins {
 134                 pullups {
 135                         pins =  "gpio52", "gpio53", "gpio58", "gpio59";
 136                         function = "qpic";
 137                         bias-pull-up;
 138                 };
 139
 140                 pulldowns {
 141                         pins = "gpio54", "gpio55", "gpio56", "gpio57",
 142                                 "gpio60", "gpio62", "gpio63", "gpio64",
 143                                 "gpio65", "gpio66", "gpio67", "gpio68",
 144                                 "gpio69";
 145                         function = "qpic";
 146                         bias-pull-down;
 147                 };
 148         };
 149
 150         sd_pins: sd_pins {
 151                 pinmux {
 152                         function = "sdio";
 153                         pins = "gpio23", "gpio24", "gpio25", "gpio26",
 154                                 "gpio28", "gpio29", "gpio30", "gpio31";
 155                         drive-strength = <10>;
 156                 };
 157                 pinmux_sd_clk {
 158                         function = "sdio";
 159                         pins = "gpio27";
 160                         drive-strength = <16>;
 161                 };
 162                 pinmux_sd7 {
 163                         function = "sdio";
 164                         pins = "gpio32";
 165                         drive-strength = <10>;
 166                         bias-disable;
 167                 };
 168         };
 169 };
 170
 171 &blsp_dma {
 172         status = "okay";
 173 };
 174
 175 &blsp1_spi1 {
 176         status = "okay";
 177
 178         pinctrl-0 = <&spi_0_pins>;
 179         pinctrl-names = "default";
 180
 181         cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
 182
 183         flash@0 {
 184                 compatible = "jedec,spi-nor";
 185                 spi-max-frequency = <24000000>;
 186                 reg = <0>;
 187
 188                 partitions {
 189                         compatible = "fixed-partitions";
 190                         #address-cells = <1>;
 191                         #size-cells = <1>;
 192
 193                         partition0@0 {
 194                                 label = "0:SBL1";
 195                                 reg = <0x00000000 0x00040000>;
 196                                 read-only;
 197                         };
 198
 199                         partition1@40000 {
 200                                 label = "0:MIBIB";
 201                                 reg = <0x00040000 0x00020000>;
 202                                 read-only;
 203                         };
 204
 205                         partition2@60000 {
 206                                 label = "0:QSEE";
 207                                 reg = <0x00060000 0x00060000>;
 208                                 read-only;
 209                         };
 210
 211                         partition3@c0000 {
 212                                 label = "0:CDT";
 213                                 reg = <0x000c0000 0x00010000>;
 214                                 read-only;
 215                         };
 216
 217                         partition4@d0000 {
 218                                 label = "0:DDRPARAMS";
 219                                 reg = <0x000d0000 0x00010000>;
 220                                 read-only;
 221                         };
 222
 223                         partition5@e0000 {
 224                                 label = "0:APPSBLENV"; /* uboot env */
 225                                 reg = <0x000e0000 0x00010000>;
 226                                 read-only;
 227                         };
 228
 229                         partition6@f0000 {
 230                                 label = "0:APPSBL"; /* uboot */
 231                                 reg = <0x000f0000 0x00080000>;
 232                                 read-only;
 233                         };
 234
 235                         partition7@170000 {
 236                                 label = "0:ART";
 237                                 reg = <0x00170000 0x00010000>;
 238                                 read-only;
 239                                 compatible = "nvmem-cells";
 240                                 #address-cells = <1>;
 241                                 #size-cells = <1>;
 242
 243                                 precal_art_1000: precal@1000 {
 244                                         reg = <0x1000 0x2f20>;
 245                                 };
 246
 247                                 precal_art_5000: precal@5000 {
 248                                         reg = <0x5000 0x2f20>;
 249                                 };
 250
 251                                 macaddr_art_0: mac-address@0 {
 252                                         reg = <0x0 0x6>;
 253                                 };
 254
 255                                 macaddr_art_6: mac-address@6 {
 256                                         reg = <0x6 0x6>;
 257                                 };
 258
 259                                 macaddr_art_1006: mac-address@1006 {
 260                                         reg = <0x1006 0x6>;
 261                                 };
 262
 263                                 macaddr_art_5006: mac-address@5006 {
 264                                         reg = <0x5006 0x6>;
 265                                 };
 266
 267                         };
 268
 269                         partition8@180000 {
 270                                 label = "0:CONFIG";
 271                                 reg = <0x00180000 0x00010000>;
 272                                 read-only;
 273                         };
 274                 };
 275         };
 276 };
 277
 278 &qpic_bam {
 279         status = "okay";
 280 };
 281
 282 &nand {
 283         status = "okay";
 284
 285         pinctrl-0 = <&nand_pins>;
 286         pinctrl-names = "default";
 287
 288         nand@0 {
 289                 partitions {
 290                         compatible = "fixed-partitions";
 291                         #address-cells = <1>;
 292                         #size-cells = <1>;
 293
 294                         partition@0 {
 295                                 label = "ubi";
 296                                 reg = <0x00000000 0x04000000>;
 297                         };
 298                 };
 299         };
 300 };
 301
 302 &blsp1_uart1 {
 303         status = "okay";
 304         pinctrl-0 = <&serial0_pins>;
 305         pinctrl-names = "default";
 306 };
 307
 308 &blsp1_uart2 {
 309         status = "okay";
 310         pinctrl-0 = <&serial1_pins>;
 311         pinctrl-names = "default";
 312 };
 313
 314 &crypto {
 315         status = "okay";
 316 };
 317
 318 &cryptobam {
 319         num-channels = <4>;
 320         qcom,num-ees = <2>;
 321         status = "okay";
 322 };
 323
 324 &mdio {
 325         status = "okay";
 326         pinctrl-0 = <&mdio_pins>;
 327         pinctrl-names = "default";
 328         reset-gpios = <&tlmm 41 GPIO_ACTIVE_LOW>;
 329         reset-delay-us = <2000>;
 330 };
 331
 332 &pcie0 {
 333         status = "okay";
 334
 335         perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
 336         wake-gpio = <&tlmm 40 GPIO_ACTIVE_LOW>;
 337
 338         /* Unpolulated slot */
 339         bridge@0,0 {
 340                 reg = <0x00000000 0 0 0 0>;
 341                 #address-cells = <3>;
 342                 #size-cells = <2>;
 343                 ranges;
 344         };
 345 };
 346
 347 &vqmmc {
 348         status = "okay";
 349 };
 350
 351 &sdhci {
 352         status = "okay";
 353         pinctrl-0 = <&sd_pins>;
 354         pinctrl-names = "default";
 355         cd-gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
 356         vqmmc-supply = <&vqmmc>;
 357 };
 358
 359 &gmac {
 360         status = "okay";
 361 };
 362
 363 &switch {
 364         status = "okay";
 365 };
 366
 367 &swport4 {
 368         status = "okay";
 369         label = "wan";
 370         nvmem-cells = <&macaddr_art_0>;
 371         nvmem-cell-names = "mac-address";
 372 };
 373
 374 &swport5 {
 375         status = "okay";
 376         label = "lan";
 377         nvmem-cells = <&macaddr_art_6>;
 378         nvmem-cell-names = "mac-address";
 379 };
 380
 381 &wifi0 {
 382         status = "okay";
 383         nvmem-cells = <&precal_art_1000>, <&macaddr_art_1006>;
 384         nvmem-cell-names = "pre-calibration", "mac-address";
 385         qcom,ath10k-calibration-variant = "Wallys-DR40X9";
 386 };
 387
 388 &wifi1 {
 389         status = "okay";
 390         nvmem-cell-names = "pre-calibration", "mac-address";
 391         nvmem-cells = <&precal_art_5000>, <&macaddr_art_5006>;
 392         qcom,ath10k-calibration-variant = "Wallys-DR40X9";
 393 };
 394
 395 &usb2 {
 396         status = "okay";
 397 };
 398
 399 &usb2_hs_phy {
 400         status = "okay";
 401 };
 402
 403 &usb3 {
 404         status = "okay";
 405 };
 406
 407 &usb3_ss_phy {
 408         status = "okay";
 409 };
 410
 411 &usb3_hs_phy {
 412         status = "okay";
 413 };
 414
 415 &prng {
 416         status = "okay";
 417 };
 418
 419 &watchdog {
 420         status = "okay";
 421 };
 422