1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
4 * Copyright (C) 2011-2012, 2020-2021 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (c) 2015, 2019, The Linux Foundation. All rights reserved.
6 * Copyright (c) 2016 John Crispin <john@phrozen.org>
7 * Copyright (c) 2021 Robert Marko <robert.marko@sartura.hr>
10 #include <linux/bitfield.h>
11 #include <linux/version.h>
12 #include <linux/etherdevice.h>
13 #include <linux/if_bridge.h>
14 #include <linux/mdio.h>
15 #include <linux/mfd/syscon.h>
16 #include <linux/module.h>
17 #include <linux/netdevice.h>
18 #include <linux/of_mdio.h>
19 #include <linux/of_net.h>
20 #include <linux/of_platform.h>
21 #include <linux/phy.h>
22 #include <linux/phylink.h>
23 #include <linux/reset.h>
26 #include "qca8k-ipq4019.h"
28 #define MIB_DESC(_s, _o, _n) \
35 static const struct qca8k_mib_desc ar8327_mib
[] = {
36 MIB_DESC(1, 0x00, "RxBroad"),
37 MIB_DESC(1, 0x04, "RxPause"),
38 MIB_DESC(1, 0x08, "RxMulti"),
39 MIB_DESC(1, 0x0c, "RxFcsErr"),
40 MIB_DESC(1, 0x10, "RxAlignErr"),
41 MIB_DESC(1, 0x14, "RxRunt"),
42 MIB_DESC(1, 0x18, "RxFragment"),
43 MIB_DESC(1, 0x1c, "Rx64Byte"),
44 MIB_DESC(1, 0x20, "Rx128Byte"),
45 MIB_DESC(1, 0x24, "Rx256Byte"),
46 MIB_DESC(1, 0x28, "Rx512Byte"),
47 MIB_DESC(1, 0x2c, "Rx1024Byte"),
48 MIB_DESC(1, 0x30, "Rx1518Byte"),
49 MIB_DESC(1, 0x34, "RxMaxByte"),
50 MIB_DESC(1, 0x38, "RxTooLong"),
51 MIB_DESC(2, 0x3c, "RxGoodByte"),
52 MIB_DESC(2, 0x44, "RxBadByte"),
53 MIB_DESC(1, 0x4c, "RxOverFlow"),
54 MIB_DESC(1, 0x50, "Filtered"),
55 MIB_DESC(1, 0x54, "TxBroad"),
56 MIB_DESC(1, 0x58, "TxPause"),
57 MIB_DESC(1, 0x5c, "TxMulti"),
58 MIB_DESC(1, 0x60, "TxUnderRun"),
59 MIB_DESC(1, 0x64, "Tx64Byte"),
60 MIB_DESC(1, 0x68, "Tx128Byte"),
61 MIB_DESC(1, 0x6c, "Tx256Byte"),
62 MIB_DESC(1, 0x70, "Tx512Byte"),
63 MIB_DESC(1, 0x74, "Tx1024Byte"),
64 MIB_DESC(1, 0x78, "Tx1518Byte"),
65 MIB_DESC(1, 0x7c, "TxMaxByte"),
66 MIB_DESC(1, 0x80, "TxOverSize"),
67 MIB_DESC(2, 0x84, "TxByte"),
68 MIB_DESC(1, 0x8c, "TxCollision"),
69 MIB_DESC(1, 0x90, "TxAbortCol"),
70 MIB_DESC(1, 0x94, "TxMultiCol"),
71 MIB_DESC(1, 0x98, "TxSingleCol"),
72 MIB_DESC(1, 0x9c, "TxExcDefer"),
73 MIB_DESC(1, 0xa0, "TxDefer"),
74 MIB_DESC(1, 0xa4, "TxLateCol"),
75 MIB_DESC(1, 0xa8, "RXUnicast"),
76 MIB_DESC(1, 0xac, "TXunicast"),
80 qca8k_read(struct qca8k_priv
*priv
, u32 reg
, u32
*val
)
82 return regmap_read(priv
->regmap
, reg
, val
);
86 qca8k_write(struct qca8k_priv
*priv
, u32 reg
, u32 val
)
88 return regmap_write(priv
->regmap
, reg
, val
);
92 qca8k_rmw(struct qca8k_priv
*priv
, u32 reg
, u32 mask
, u32 write_val
)
94 return regmap_update_bits(priv
->regmap
, reg
, mask
, write_val
);
98 qca8k_reg_set(struct qca8k_priv
*priv
, u32 reg
, u32 val
)
100 return regmap_set_bits(priv
->regmap
, reg
, val
);
104 qca8k_reg_clear(struct qca8k_priv
*priv
, u32 reg
, u32 val
)
106 return regmap_clear_bits(priv
->regmap
, reg
, val
);
109 static const struct regmap_range qca8k_readable_ranges
[] = {
110 regmap_reg_range(0x0000, 0x00e4), /* Global control */
111 regmap_reg_range(0x0100, 0x0168), /* EEE control */
112 regmap_reg_range(0x0200, 0x0270), /* Parser control */
113 regmap_reg_range(0x0400, 0x0454), /* ACL */
114 regmap_reg_range(0x0600, 0x0718), /* Lookup */
115 regmap_reg_range(0x0800, 0x0b70), /* QM */
116 regmap_reg_range(0x0c00, 0x0c80), /* PKT */
117 regmap_reg_range(0x0e00, 0x0e98), /* L3 */
118 regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */
119 regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */
120 regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */
121 regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */
122 regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */
123 regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */
124 regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */
128 static const struct regmap_access_table qca8k_readable_table
= {
129 .yes_ranges
= qca8k_readable_ranges
,
130 .n_yes_ranges
= ARRAY_SIZE(qca8k_readable_ranges
),
133 static struct regmap_config qca8k_ipq4019_regmap_config
= {
137 .max_register
= 0x16ac, /* end MIB - Port6 range */
138 .rd_table
= &qca8k_readable_table
,
141 static struct regmap_config qca8k_ipq4019_psgmii_phy_regmap_config
= {
142 .name
= "psgmii-phy",
146 .max_register
= 0x7fc,
150 qca8k_busy_wait(struct qca8k_priv
*priv
, u32 reg
, u32 mask
)
154 return regmap_read_poll_timeout(priv
->regmap
, reg
, val
,
157 QCA8K_BUSY_WAIT_TIMEOUT
);
161 qca8k_fdb_read(struct qca8k_priv
*priv
, struct qca8k_fdb
*fdb
)
166 /* load the ARL table into an array */
167 for (i
= 0; i
< 4; i
++) {
168 ret
= qca8k_read(priv
, QCA8K_REG_ATU_DATA0
+ (i
* 4), &val
);
176 fdb
->vid
= (reg
[2] >> QCA8K_ATU_VID_S
) & QCA8K_ATU_VID_M
;
178 fdb
->aging
= reg
[2] & QCA8K_ATU_STATUS_M
;
179 /* portmask - 54:48 */
180 fdb
->port_mask
= (reg
[1] >> QCA8K_ATU_PORT_S
) & QCA8K_ATU_PORT_M
;
182 fdb
->mac
[0] = (reg
[1] >> QCA8K_ATU_ADDR0_S
) & 0xff;
183 fdb
->mac
[1] = reg
[1] & 0xff;
184 fdb
->mac
[2] = (reg
[0] >> QCA8K_ATU_ADDR2_S
) & 0xff;
185 fdb
->mac
[3] = (reg
[0] >> QCA8K_ATU_ADDR3_S
) & 0xff;
186 fdb
->mac
[4] = (reg
[0] >> QCA8K_ATU_ADDR4_S
) & 0xff;
187 fdb
->mac
[5] = reg
[0] & 0xff;
193 qca8k_fdb_write(struct qca8k_priv
*priv
, u16 vid
, u8 port_mask
, const u8
*mac
,
200 reg
[2] = (vid
& QCA8K_ATU_VID_M
) << QCA8K_ATU_VID_S
;
202 reg
[2] |= aging
& QCA8K_ATU_STATUS_M
;
203 /* portmask - 54:48 */
204 reg
[1] = (port_mask
& QCA8K_ATU_PORT_M
) << QCA8K_ATU_PORT_S
;
206 reg
[1] |= mac
[0] << QCA8K_ATU_ADDR0_S
;
208 reg
[0] |= mac
[2] << QCA8K_ATU_ADDR2_S
;
209 reg
[0] |= mac
[3] << QCA8K_ATU_ADDR3_S
;
210 reg
[0] |= mac
[4] << QCA8K_ATU_ADDR4_S
;
213 /* load the array into the ARL table */
214 for (i
= 0; i
< 3; i
++)
215 qca8k_write(priv
, QCA8K_REG_ATU_DATA0
+ (i
* 4), reg
[i
]);
219 qca8k_fdb_access(struct qca8k_priv
*priv
, enum qca8k_fdb_cmd cmd
, int port
)
224 /* Set the command and FDB index */
225 reg
= QCA8K_ATU_FUNC_BUSY
;
228 reg
|= QCA8K_ATU_FUNC_PORT_EN
;
229 reg
|= (port
& QCA8K_ATU_FUNC_PORT_M
) << QCA8K_ATU_FUNC_PORT_S
;
232 /* Write the function register triggering the table access */
233 ret
= qca8k_write(priv
, QCA8K_REG_ATU_FUNC
, reg
);
237 /* wait for completion */
238 ret
= qca8k_busy_wait(priv
, QCA8K_REG_ATU_FUNC
, QCA8K_ATU_FUNC_BUSY
);
242 /* Check for table full violation when adding an entry */
243 if (cmd
== QCA8K_FDB_LOAD
) {
244 ret
= qca8k_read(priv
, QCA8K_REG_ATU_FUNC
, ®
);
247 if (reg
& QCA8K_ATU_FUNC_FULL
)
255 qca8k_fdb_next(struct qca8k_priv
*priv
, struct qca8k_fdb
*fdb
, int port
)
259 qca8k_fdb_write(priv
, fdb
->vid
, fdb
->port_mask
, fdb
->mac
, fdb
->aging
);
260 ret
= qca8k_fdb_access(priv
, QCA8K_FDB_NEXT
, port
);
264 return qca8k_fdb_read(priv
, fdb
);
268 qca8k_fdb_add(struct qca8k_priv
*priv
, const u8
*mac
, u16 port_mask
,
273 mutex_lock(&priv
->reg_mutex
);
274 qca8k_fdb_write(priv
, vid
, port_mask
, mac
, aging
);
275 ret
= qca8k_fdb_access(priv
, QCA8K_FDB_LOAD
, -1);
276 mutex_unlock(&priv
->reg_mutex
);
282 qca8k_fdb_del(struct qca8k_priv
*priv
, const u8
*mac
, u16 port_mask
, u16 vid
)
286 mutex_lock(&priv
->reg_mutex
);
287 qca8k_fdb_write(priv
, vid
, port_mask
, mac
, 0);
288 ret
= qca8k_fdb_access(priv
, QCA8K_FDB_PURGE
, -1);
289 mutex_unlock(&priv
->reg_mutex
);
295 qca8k_fdb_flush(struct qca8k_priv
*priv
)
297 mutex_lock(&priv
->reg_mutex
);
298 qca8k_fdb_access(priv
, QCA8K_FDB_FLUSH
, -1);
299 mutex_unlock(&priv
->reg_mutex
);
303 qca8k_vlan_access(struct qca8k_priv
*priv
, enum qca8k_vlan_cmd cmd
, u16 vid
)
308 /* Set the command and VLAN index */
309 reg
= QCA8K_VTU_FUNC1_BUSY
;
311 reg
|= vid
<< QCA8K_VTU_FUNC1_VID_S
;
313 /* Write the function register triggering the table access */
314 ret
= qca8k_write(priv
, QCA8K_REG_VTU_FUNC1
, reg
);
318 /* wait for completion */
319 ret
= qca8k_busy_wait(priv
, QCA8K_REG_VTU_FUNC1
, QCA8K_VTU_FUNC1_BUSY
);
323 /* Check for table full violation when adding an entry */
324 if (cmd
== QCA8K_VLAN_LOAD
) {
325 ret
= qca8k_read(priv
, QCA8K_REG_VTU_FUNC1
, ®
);
328 if (reg
& QCA8K_VTU_FUNC1_FULL
)
336 qca8k_vlan_add(struct qca8k_priv
*priv
, u8 port
, u16 vid
, bool untagged
)
342 We do the right thing with VLAN 0 and treat it as untagged while
343 preserving the tag on egress.
348 mutex_lock(&priv
->reg_mutex
);
349 ret
= qca8k_vlan_access(priv
, QCA8K_VLAN_READ
, vid
);
353 ret
= qca8k_read(priv
, QCA8K_REG_VTU_FUNC0
, ®
);
356 reg
|= QCA8K_VTU_FUNC0_VALID
| QCA8K_VTU_FUNC0_IVL_EN
;
357 reg
&= ~(QCA8K_VTU_FUNC0_EG_MODE_MASK
<< QCA8K_VTU_FUNC0_EG_MODE_S(port
));
359 reg
|= QCA8K_VTU_FUNC0_EG_MODE_UNTAG
<<
360 QCA8K_VTU_FUNC0_EG_MODE_S(port
);
362 reg
|= QCA8K_VTU_FUNC0_EG_MODE_TAG
<<
363 QCA8K_VTU_FUNC0_EG_MODE_S(port
);
365 ret
= qca8k_write(priv
, QCA8K_REG_VTU_FUNC0
, reg
);
368 ret
= qca8k_vlan_access(priv
, QCA8K_VLAN_LOAD
, vid
);
371 mutex_unlock(&priv
->reg_mutex
);
377 qca8k_vlan_del(struct qca8k_priv
*priv
, u8 port
, u16 vid
)
383 mutex_lock(&priv
->reg_mutex
);
384 ret
= qca8k_vlan_access(priv
, QCA8K_VLAN_READ
, vid
);
388 ret
= qca8k_read(priv
, QCA8K_REG_VTU_FUNC0
, ®
);
391 reg
&= ~(3 << QCA8K_VTU_FUNC0_EG_MODE_S(port
));
392 reg
|= QCA8K_VTU_FUNC0_EG_MODE_NOT
<<
393 QCA8K_VTU_FUNC0_EG_MODE_S(port
);
395 /* Check if we're the last member to be removed */
397 for (i
= 0; i
< QCA8K_NUM_PORTS
; i
++) {
398 mask
= QCA8K_VTU_FUNC0_EG_MODE_NOT
;
399 mask
<<= QCA8K_VTU_FUNC0_EG_MODE_S(i
);
401 if ((reg
& mask
) != mask
) {
408 ret
= qca8k_vlan_access(priv
, QCA8K_VLAN_PURGE
, vid
);
410 ret
= qca8k_write(priv
, QCA8K_REG_VTU_FUNC0
, reg
);
413 ret
= qca8k_vlan_access(priv
, QCA8K_VLAN_LOAD
, vid
);
417 mutex_unlock(&priv
->reg_mutex
);
423 qca8k_mib_init(struct qca8k_priv
*priv
)
427 mutex_lock(&priv
->reg_mutex
);
428 ret
= qca8k_reg_set(priv
, QCA8K_REG_MIB
, QCA8K_MIB_FLUSH
| QCA8K_MIB_BUSY
);
432 ret
= qca8k_busy_wait(priv
, QCA8K_REG_MIB
, QCA8K_MIB_BUSY
);
436 ret
= qca8k_reg_set(priv
, QCA8K_REG_MIB
, QCA8K_MIB_CPU_KEEP
);
440 ret
= qca8k_write(priv
, QCA8K_REG_MODULE_EN
, QCA8K_MODULE_EN_MIB
);
443 mutex_unlock(&priv
->reg_mutex
);
448 qca8k_port_set_status(struct qca8k_priv
*priv
, int port
, int enable
)
450 u32 mask
= QCA8K_PORT_STATUS_TXMAC
| QCA8K_PORT_STATUS_RXMAC
;
452 /* Port 0 is internally connected to the CPU
453 * TODO: Probably check for RGMII as well if it doesnt work
456 if (port
> QCA8K_CPU_PORT
)
457 mask
|= QCA8K_PORT_STATUS_LINK_AUTO
;
460 qca8k_reg_set(priv
, QCA8K_REG_PORT_STATUS(port
), mask
);
462 qca8k_reg_clear(priv
, QCA8K_REG_PORT_STATUS(port
), mask
);
466 qca8k_setup_port(struct dsa_switch
*ds
, int port
)
468 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
471 /* CPU port gets connected to all user ports of the switch */
472 if (dsa_is_cpu_port(ds
, port
)) {
473 ret
= qca8k_rmw(priv
, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT
),
474 QCA8K_PORT_LOOKUP_MEMBER
, dsa_user_ports(ds
));
478 /* Disable CPU ARP Auto-learning by default */
479 ret
= qca8k_reg_clear(priv
, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT
),
480 QCA8K_PORT_LOOKUP_LEARN
);
485 /* Individual user ports get connected to CPU port only */
486 if (dsa_is_user_port(ds
, port
)) {
487 int shift
= 16 * (port
% 2);
489 ret
= qca8k_rmw(priv
, QCA8K_PORT_LOOKUP_CTRL(port
),
490 QCA8K_PORT_LOOKUP_MEMBER
,
491 BIT(QCA8K_CPU_PORT
));
495 /* Enable ARP Auto-learning by default */
496 ret
= qca8k_reg_set(priv
, QCA8K_PORT_LOOKUP_CTRL(port
),
497 QCA8K_PORT_LOOKUP_LEARN
);
501 /* For port based vlans to work we need to set the
504 ret
= qca8k_rmw(priv
, QCA8K_EGRESS_VLAN(port
),
506 QCA8K_PORT_VID_DEF
<< shift
);
510 ret
= qca8k_write(priv
, QCA8K_REG_PORT_VLAN_CTRL0(port
),
511 QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF
) |
512 QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF
));
521 qca8k_setup(struct dsa_switch
*ds
)
523 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
526 /* Make sure that port 0 is the cpu port */
527 if (!dsa_is_cpu_port(ds
, 0)) {
528 dev_err(priv
->dev
, "port 0 is not the CPU port");
532 /* Enable CPU Port */
533 ret
= qca8k_reg_set(priv
, QCA8K_REG_GLOBAL_FW_CTRL0
,
534 QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN
);
536 dev_err(priv
->dev
, "failed enabling CPU port");
540 /* Enable MIB counters */
541 ret
= qca8k_mib_init(priv
);
543 dev_warn(priv
->dev
, "MIB init failed");
545 /* Enable QCA header mode on the cpu port */
546 ret
= qca8k_write(priv
, QCA8K_REG_PORT_HDR_CTRL(QCA8K_CPU_PORT
),
547 QCA8K_PORT_HDR_CTRL_ALL
<< QCA8K_PORT_HDR_CTRL_TX_S
|
548 QCA8K_PORT_HDR_CTRL_ALL
<< QCA8K_PORT_HDR_CTRL_RX_S
);
550 dev_err(priv
->dev
, "failed enabling QCA header mode");
554 /* Disable forwarding by default on all ports */
555 for (i
= 0; i
< QCA8K_NUM_PORTS
; i
++) {
556 ret
= qca8k_rmw(priv
, QCA8K_PORT_LOOKUP_CTRL(i
),
557 QCA8K_PORT_LOOKUP_MEMBER
, 0);
562 /* Disable MAC by default on all ports */
563 for (i
= 1; i
< QCA8K_NUM_PORTS
; i
++)
564 qca8k_port_set_status(priv
, i
, 0);
566 /* Forward all unknown frames to CPU port for Linux processing */
567 ret
= qca8k_write(priv
, QCA8K_REG_GLOBAL_FW_CTRL1
,
568 BIT(QCA8K_CPU_PORT
) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S
|
569 BIT(QCA8K_CPU_PORT
) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S
|
570 BIT(QCA8K_CPU_PORT
) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S
|
571 BIT(QCA8K_CPU_PORT
) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S
);
575 /* Setup connection between CPU port & user ports */
576 for (i
= 0; i
< QCA8K_NUM_PORTS
; i
++) {
577 ret
= qca8k_setup_port(ds
, i
);
582 /* Setup our port MTUs to match power on defaults */
583 for (i
= 0; i
< QCA8K_NUM_PORTS
; i
++)
584 /* Set per port MTU to 1500 as the MTU change function
585 * will add the overhead and if its set to 1518 then it
586 * will apply the overhead again and we will end up with
587 * MTU of 1536 instead of 1518
589 priv
->port_mtu
[i
] = ETH_DATA_LEN
;
590 ret
= qca8k_write(priv
, QCA8K_MAX_FRAME_SIZE
, ETH_FRAME_LEN
+ ETH_FCS_LEN
);
592 dev_warn(priv
->dev
, "failed setting MTU settings");
594 /* Flush the FDB table */
595 qca8k_fdb_flush(priv
);
597 /* We don't have interrupts for link changes, so we need to poll */
600 /* CPU port HW learning doesnt work correctly, so let DSA handle it */
601 ds
->assisted_learning_on_cpu_port
= true;
606 static int psgmii_vco_calibrate(struct qca8k_priv
*priv
)
610 if (!priv
->psgmii_ethphy
) {
611 dev_err(priv
->dev
, "PSGMII eth PHY missing, calibration failed!\n");
615 /* Fix PSGMII RX 20bit */
616 ret
= phy_write(priv
->psgmii_ethphy
, MII_BMCR
, 0x5b);
617 /* Reset PHY PSGMII */
618 ret
= phy_write(priv
->psgmii_ethphy
, MII_BMCR
, 0x1b);
619 /* Release PHY PSGMII reset */
620 ret
= phy_write(priv
->psgmii_ethphy
, MII_BMCR
, 0x5b);
622 /* Poll for VCO PLL calibration finish - Malibu(QCA8075) */
623 ret
= phy_read_mmd_poll_timeout(priv
->psgmii_ethphy
,
630 dev_err(priv
->dev
, "QCA807x PSGMII VCO calibration PLL not ready\n");
635 /* Freeze PSGMII RX CDR */
636 ret
= phy_write(priv
->psgmii_ethphy
, MII_RESV2
, 0x2230);
638 /* Start PSGMIIPHY VCO PLL calibration */
639 ret
= regmap_set_bits(priv
->psgmii
,
640 PSGMIIPHY_VCO_CALIBRATION_CONTROL_REGISTER_1
,
641 PSGMIIPHY_REG_PLL_VCO_CALIB_RESTART
);
643 /* Poll for PSGMIIPHY PLL calibration finish - Dakota(IPQ40xx) */
644 ret
= regmap_read_poll_timeout(priv
->psgmii
,
645 PSGMIIPHY_VCO_CALIBRATION_CONTROL_REGISTER_2
,
646 val
, val
& PSGMIIPHY_REG_PLL_VCO_CALIB_READY
,
649 dev_err(priv
->dev
, "IPQ PSGMIIPHY VCO calibration PLL not ready\n");
654 /* Release PSGMII RX CDR */
655 ret
= phy_write(priv
->psgmii_ethphy
, MII_RESV2
, 0x3230);
656 /* Release PSGMII RX 20bit */
657 ret
= phy_write(priv
->psgmii_ethphy
, MII_BMCR
, 0x5f);
664 qca8k_switch_port_loopback_on_off(struct qca8k_priv
*priv
, int port
, int on
)
666 u32 val
= QCA8K_PORT_LOOKUP_LOOPBACK
;
671 qca8k_rmw(priv
, QCA8K_PORT_LOOKUP_CTRL(port
),
672 QCA8K_PORT_LOOKUP_LOOPBACK
, val
);
676 qca8k_wait_for_phy_link_state(struct phy_device
*phy
, int need_status
)
681 for (a
= 0; a
< 100; a
++) {
682 status
= phy_read(phy
, MII_QCA8075_SSTATUS
);
683 status
&= QCA8075_PHY_SPEC_STATUS_LINK
;
685 if (status
== need_status
)
694 qca8k_phy_loopback_on_off(struct qca8k_priv
*priv
, struct phy_device
*phy
,
698 phy_write(phy
, MII_BMCR
, BMCR_ANENABLE
| BMCR_RESET
);
699 phy_modify(phy
, MII_BMCR
, BMCR_PDOWN
, BMCR_PDOWN
);
700 qca8k_wait_for_phy_link_state(phy
, 0);
701 qca8k_write(priv
, QCA8K_REG_PORT_STATUS(sw_port
), 0);
702 phy_write(phy
, MII_BMCR
,
706 qca8k_wait_for_phy_link_state(phy
, 1);
707 qca8k_write(priv
, QCA8K_REG_PORT_STATUS(sw_port
),
708 QCA8K_PORT_STATUS_SPEED_1000
|
709 QCA8K_PORT_STATUS_TXMAC
|
710 QCA8K_PORT_STATUS_RXMAC
|
711 QCA8K_PORT_STATUS_DUPLEX
);
712 qca8k_rmw(priv
, QCA8K_PORT_LOOKUP_CTRL(sw_port
),
713 QCA8K_PORT_LOOKUP_STATE_FORWARD
,
714 QCA8K_PORT_LOOKUP_STATE_FORWARD
);
716 qca8k_write(priv
, QCA8K_REG_PORT_STATUS(sw_port
), 0);
717 qca8k_rmw(priv
, QCA8K_PORT_LOOKUP_CTRL(sw_port
),
718 QCA8K_PORT_LOOKUP_STATE_DISABLED
,
719 QCA8K_PORT_LOOKUP_STATE_DISABLED
);
720 phy_write(phy
, MII_BMCR
, BMCR_SPEED1000
| BMCR_ANENABLE
| BMCR_RESET
);
721 /* turn off the power of the phys - so that unused
722 ports do not raise links */
723 phy_modify(phy
, MII_BMCR
, BMCR_PDOWN
, BMCR_PDOWN
);
728 qca8k_phy_pkt_gen_prep(struct qca8k_priv
*priv
, struct phy_device
*phy
,
729 int pkts_num
, int on
)
732 /* enable CRC checker and packets counters */
733 phy_write_mmd(phy
, MDIO_MMD_AN
, QCA8075_MMD7_CRC_AND_PKTS_COUNT
, 0);
734 phy_write_mmd(phy
, MDIO_MMD_AN
, QCA8075_MMD7_CRC_AND_PKTS_COUNT
,
735 QCA8075_MMD7_CNT_FRAME_CHK_EN
| QCA8075_MMD7_CNT_SELFCLR
);
736 qca8k_wait_for_phy_link_state(phy
, 1);
738 phy_write_mmd(phy
, MDIO_MMD_AN
, QCA8075_MMD7_PKT_GEN_PKT_NUMB
, pkts_num
);
739 /* pkt size - 1504 bytes + 20 bytes */
740 phy_write_mmd(phy
, MDIO_MMD_AN
, QCA8075_MMD7_PKT_GEN_PKT_SIZE
, 1504);
743 phy_write_mmd(phy
, MDIO_MMD_AN
, QCA8075_MMD7_PKT_GEN_PKT_NUMB
, 0);
744 /* disable CRC checker and packet counter */
745 phy_write_mmd(phy
, MDIO_MMD_AN
, QCA8075_MMD7_CRC_AND_PKTS_COUNT
, 0);
746 /* disable traffic gen */
747 phy_write_mmd(phy
, MDIO_MMD_AN
, QCA8075_MMD7_PKT_GEN_CTRL
, 0);
752 qca8k_wait_for_phy_pkt_gen_fin(struct qca8k_priv
*priv
, struct phy_device
*phy
)
755 /* wait for all traffic end: 4096(pkt num)*1524(size)*8ns(125MHz)=49938us */
756 phy_read_mmd_poll_timeout(phy
, MDIO_MMD_AN
, QCA8075_MMD7_PKT_GEN_CTRL
,
757 val
, !(val
& QCA8075_MMD7_PKT_GEN_INPROGR
),
758 50000, 1000000, true);
762 qca8k_start_phy_pkt_gen(struct phy_device
*phy
)
764 /* start traffic gen */
765 phy_write_mmd(phy
, MDIO_MMD_AN
, QCA8075_MMD7_PKT_GEN_CTRL
,
766 QCA8075_MMD7_PKT_GEN_START
| QCA8075_MMD7_PKT_GEN_INPROGR
);
770 qca8k_start_all_phys_pkt_gens(struct qca8k_priv
*priv
)
772 struct phy_device
*phy
;
773 phy
= phy_device_create(priv
->bus
, QCA8075_MDIO_BRDCST_PHY_ADDR
,
776 dev_err(priv
->dev
, "unable to create mdio broadcast PHY(0x%x)\n",
777 QCA8075_MDIO_BRDCST_PHY_ADDR
);
781 qca8k_start_phy_pkt_gen(phy
);
783 phy_device_free(phy
);
788 qca8k_get_phy_pkt_gen_test_result(struct phy_device
*phy
, int pkts_num
)
794 u32 tx_all_ok
, rx_all_ok
;
797 tx_ok
= phy_read_mmd(phy
, MDIO_MMD_AN
, QCA8075_MMD7_EG_FRAME_RECV_CNT_LO
);
798 tx_ok_high16
= phy_read_mmd(phy
, MDIO_MMD_AN
, QCA8075_MMD7_EG_FRAME_RECV_CNT_HI
);
799 tx_error
= phy_read_mmd(phy
, MDIO_MMD_AN
, QCA8075_MMD7_EG_FRAME_ERR_CNT
);
800 rx_ok
= phy_read_mmd(phy
, MDIO_MMD_AN
, QCA8075_MMD7_IG_FRAME_RECV_CNT_LO
);
801 rx_ok_high16
= phy_read_mmd(phy
, MDIO_MMD_AN
, QCA8075_MMD7_IG_FRAME_RECV_CNT_HI
);
802 rx_error
= phy_read_mmd(phy
, MDIO_MMD_AN
, QCA8075_MMD7_IG_FRAME_ERR_CNT
);
803 tx_all_ok
= tx_ok
+ (tx_ok_high16
<< 16);
804 rx_all_ok
= rx_ok
+ (rx_ok_high16
<< 16);
806 if (tx_all_ok
< pkts_num
)
808 if(rx_all_ok
< pkts_num
)
814 return 0; /* test is ok */
818 void qca8k_phy_broadcast_write_on_off(struct qca8k_priv
*priv
,
819 struct phy_device
*phy
, int on
)
823 val
= phy_read_mmd(phy
, MDIO_MMD_AN
, QCA8075_MMD7_MDIO_BRDCST_WRITE
);
826 val
&= ~QCA8075_MMD7_MDIO_BRDCST_WRITE_EN
;
828 val
|= QCA8075_MMD7_MDIO_BRDCST_WRITE_EN
;
830 phy_write_mmd(phy
, MDIO_MMD_AN
, QCA8075_MMD7_MDIO_BRDCST_WRITE
, val
);
834 qca8k_test_dsa_port_for_errors(struct qca8k_priv
*priv
, struct phy_device
*phy
,
835 int port
, int test_phase
)
838 const int test_pkts_num
= QCA8075_PKT_GEN_PKTS_COUNT
;
840 if (test_phase
== 1) { /* start test preps */
841 qca8k_phy_loopback_on_off(priv
, phy
, port
, 1);
842 qca8k_switch_port_loopback_on_off(priv
, port
, 1);
843 qca8k_phy_broadcast_write_on_off(priv
, phy
, 1);
844 qca8k_phy_pkt_gen_prep(priv
, phy
, test_pkts_num
, 1);
845 } else if (test_phase
== 2) {
846 /* wait for test results, collect it and cleanup */
847 qca8k_wait_for_phy_pkt_gen_fin(priv
, phy
);
848 res
= qca8k_get_phy_pkt_gen_test_result(phy
, test_pkts_num
);
849 qca8k_phy_pkt_gen_prep(priv
, phy
, test_pkts_num
, 0);
850 qca8k_phy_broadcast_write_on_off(priv
, phy
, 0);
851 qca8k_switch_port_loopback_on_off(priv
, port
, 0);
852 qca8k_phy_loopback_on_off(priv
, phy
, port
, 0);
859 qca8k_do_dsa_sw_ports_self_test(struct qca8k_priv
*priv
, int parallel_test
)
861 struct device_node
*dn
= priv
->dev
->of_node
;
862 struct device_node
*ports
, *port
;
863 struct device_node
*phy_dn
;
864 struct phy_device
*phy
;
865 int reg
, err
= 0, test_phase
;
866 u32 tests_result
= 0;
868 ports
= of_get_child_by_name(dn
, "ports");
870 dev_err(priv
->dev
, "no ports child node found\n");
874 for (test_phase
= 1; test_phase
<= 2; test_phase
++) {
875 if (parallel_test
&& test_phase
== 2) {
876 err
= qca8k_start_all_phys_pkt_gens(priv
);
880 for_each_available_child_of_node(ports
, port
) {
881 err
= of_property_read_u32(port
, "reg", ®
);
884 if (reg
>= QCA8K_NUM_PORTS
) {
888 phy_dn
= of_parse_phandle(port
, "phy-handle", 0);
890 phy
= of_phy_find_device(phy_dn
);
894 result
= qca8k_test_dsa_port_for_errors(priv
,
895 phy
, reg
, test_phase
);
896 if (!parallel_test
&& test_phase
== 1)
897 qca8k_start_phy_pkt_gen(phy
);
898 put_device(&phy
->mdio
.dev
);
899 if (test_phase
== 2) {
911 qca8k_fdb_flush(priv
);
914 tests_result
|= 0xf000;
919 psgmii_vco_calibrate_and_test(struct dsa_switch
*ds
)
921 int ret
, a
, test_result
;
922 struct qca8k_priv
*priv
= ds
->priv
;
924 for (a
= 0; a
<= QCA8K_PSGMII_CALB_NUM
; a
++) {
925 ret
= psgmii_vco_calibrate(priv
);
928 /* first we run serial test */
929 test_result
= qca8k_do_dsa_sw_ports_self_test(priv
, 0);
930 /* and if it is ok then we run the test in parallel */
932 test_result
= qca8k_do_dsa_sw_ports_self_test(priv
, 1);
935 dev_warn(priv
->dev
, "PSGMII work was stabilized after %d "
936 "calibration retries !\n", a
);
941 if (a
> 0 && a
% 10 == 0) {
942 dev_err(priv
->dev
, "PSGMII work is unstable !!! "
943 "Let's try to wait a bit ... %d\n", a
);
944 set_current_state(TASK_INTERRUPTIBLE
);
945 schedule_timeout(msecs_to_jiffies(a
* 100));
950 panic("PSGMII work is unstable !!! "
951 "Repeated recalibration attempts did not help(0x%x) !\n",
958 ipq4019_psgmii_configure(struct dsa_switch
*ds
)
960 struct qca8k_priv
*priv
= ds
->priv
;
963 if (!priv
->psgmii_calibrated
) {
964 ret
= psgmii_vco_calibrate_and_test(ds
);
966 ret
= regmap_clear_bits(priv
->psgmii
, PSGMIIPHY_MODE_CONTROL
,
967 PSGMIIPHY_MODE_ATHR_CSCO_MODE_25M
);
968 ret
= regmap_write(priv
->psgmii
, PSGMIIPHY_TX_CONTROL
,
969 PSGMIIPHY_TX_CONTROL_MAGIC_VALUE
);
971 priv
->psgmii_calibrated
= true;
980 qca8k_phylink_mac_config(struct dsa_switch
*ds
, int port
, unsigned int mode
,
981 const struct phylink_link_state
*state
)
983 struct qca8k_priv
*priv
= ds
->priv
;
987 /* CPU port, no configuration needed */
992 if (state
->interface
== PHY_INTERFACE_MODE_PSGMII
)
993 if (ipq4019_psgmii_configure(ds
))
994 dev_err(ds
->dev
, "PSGMII configuration failed!\n");
998 if (state
->interface
== PHY_INTERFACE_MODE_RGMII
||
999 state
->interface
== PHY_INTERFACE_MODE_RGMII_ID
||
1000 state
->interface
== PHY_INTERFACE_MODE_RGMII_RXID
||
1001 state
->interface
== PHY_INTERFACE_MODE_RGMII_TXID
) {
1002 qca8k_reg_set(priv
, QCA8K_REG_RGMII_CTRL
, QCA8K_RGMII_CTRL_CLK
);
1005 if (state
->interface
== PHY_INTERFACE_MODE_PSGMII
)
1006 if (ipq4019_psgmii_configure(ds
))
1007 dev_err(ds
->dev
, "PSGMII configuration failed!\n");
1010 dev_err(ds
->dev
, "%s: unsupported port: %i\n", __func__
, port
);
1016 qca8k_phylink_validate(struct dsa_switch
*ds
, int port
,
1017 unsigned long *supported
,
1018 struct phylink_link_state
*state
)
1020 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask
) = { 0, };
1023 case 0: /* CPU port */
1024 if (state
->interface
!= PHY_INTERFACE_MODE_INTERNAL
)
1030 /* Only PSGMII mode is supported */
1031 if (state
->interface
!= PHY_INTERFACE_MODE_PSGMII
)
1036 /* PSGMII and RGMII modes are supported */
1037 if (state
->interface
!= PHY_INTERFACE_MODE_PSGMII
&&
1038 state
->interface
!= PHY_INTERFACE_MODE_RGMII
&&
1039 state
->interface
!= PHY_INTERFACE_MODE_RGMII_ID
&&
1040 state
->interface
!= PHY_INTERFACE_MODE_RGMII_RXID
&&
1041 state
->interface
!= PHY_INTERFACE_MODE_RGMII_TXID
)
1046 dev_warn(ds
->dev
, "interface '%s' (%d) on port %d is not supported\n",
1047 phy_modes(state
->interface
), state
->interface
, port
);
1048 linkmode_zero(supported
);
1053 phylink_set_port_modes(mask
);
1055 phylink_set(mask
, 1000baseT_Full
);
1057 phylink_set(mask
, Pause
);
1058 phylink_set(mask
, Asym_Pause
);
1060 linkmode_and(supported
, supported
, mask
);
1061 linkmode_and(state
->advertising
, state
->advertising
, mask
);
1063 /* Simply copy what PHYs tell us */
1064 linkmode_copy(state
->advertising
, supported
);
1069 qca8k_phylink_mac_link_state(struct dsa_switch
*ds
, int port
,
1070 struct phylink_link_state
*state
)
1072 struct qca8k_priv
*priv
= ds
->priv
;
1076 ret
= qca8k_read(priv
, QCA8K_REG_PORT_STATUS(port
), ®
);
1080 state
->link
= !!(reg
& QCA8K_PORT_STATUS_LINK_UP
);
1081 state
->an_complete
= state
->link
;
1082 state
->an_enabled
= !!(reg
& QCA8K_PORT_STATUS_LINK_AUTO
);
1083 state
->duplex
= (reg
& QCA8K_PORT_STATUS_DUPLEX
) ? DUPLEX_FULL
:
1086 switch (reg
& QCA8K_PORT_STATUS_SPEED
) {
1087 case QCA8K_PORT_STATUS_SPEED_10
:
1088 state
->speed
= SPEED_10
;
1090 case QCA8K_PORT_STATUS_SPEED_100
:
1091 state
->speed
= SPEED_100
;
1093 case QCA8K_PORT_STATUS_SPEED_1000
:
1094 state
->speed
= SPEED_1000
;
1097 state
->speed
= SPEED_UNKNOWN
;
1101 state
->pause
= MLO_PAUSE_NONE
;
1102 if (reg
& QCA8K_PORT_STATUS_RXFLOW
)
1103 state
->pause
|= MLO_PAUSE_RX
;
1104 if (reg
& QCA8K_PORT_STATUS_TXFLOW
)
1105 state
->pause
|= MLO_PAUSE_TX
;
1111 qca8k_phylink_mac_link_down(struct dsa_switch
*ds
, int port
, unsigned int mode
,
1112 phy_interface_t interface
)
1114 struct qca8k_priv
*priv
= ds
->priv
;
1116 qca8k_port_set_status(priv
, port
, 0);
1120 qca8k_phylink_mac_link_up(struct dsa_switch
*ds
, int port
, unsigned int mode
,
1121 phy_interface_t interface
, struct phy_device
*phydev
,
1122 int speed
, int duplex
, bool tx_pause
, bool rx_pause
)
1124 struct qca8k_priv
*priv
= ds
->priv
;
1127 if (phylink_autoneg_inband(mode
)) {
1128 reg
= QCA8K_PORT_STATUS_LINK_AUTO
;
1132 reg
= QCA8K_PORT_STATUS_SPEED_10
;
1135 reg
= QCA8K_PORT_STATUS_SPEED_100
;
1138 reg
= QCA8K_PORT_STATUS_SPEED_1000
;
1141 reg
= QCA8K_PORT_STATUS_LINK_AUTO
;
1145 if (duplex
== DUPLEX_FULL
)
1146 reg
|= QCA8K_PORT_STATUS_DUPLEX
;
1148 if (rx_pause
|| dsa_is_cpu_port(ds
, port
))
1149 reg
|= QCA8K_PORT_STATUS_RXFLOW
;
1151 if (tx_pause
|| dsa_is_cpu_port(ds
, port
))
1152 reg
|= QCA8K_PORT_STATUS_TXFLOW
;
1155 reg
|= QCA8K_PORT_STATUS_TXMAC
| QCA8K_PORT_STATUS_RXMAC
;
1157 qca8k_write(priv
, QCA8K_REG_PORT_STATUS(port
), reg
);
1161 qca8k_get_strings(struct dsa_switch
*ds
, int port
, u32 stringset
, uint8_t *data
)
1165 if (stringset
!= ETH_SS_STATS
)
1168 for (i
= 0; i
< ARRAY_SIZE(ar8327_mib
); i
++)
1169 strncpy(data
+ i
* ETH_GSTRING_LEN
, ar8327_mib
[i
].name
,
1174 qca8k_get_ethtool_stats(struct dsa_switch
*ds
, int port
,
1177 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
1178 const struct qca8k_mib_desc
*mib
;
1183 for (i
= 0; i
< ARRAY_SIZE(ar8327_mib
); i
++) {
1184 mib
= &ar8327_mib
[i
];
1185 reg
= QCA8K_PORT_MIB_COUNTER(port
) + mib
->offset
;
1187 ret
= qca8k_read(priv
, reg
, &val
);
1191 if (mib
->size
== 2) {
1192 ret
= qca8k_read(priv
, reg
+ 4, &hi
);
1199 data
[i
] |= (u64
)hi
<< 32;
1204 qca8k_get_sset_count(struct dsa_switch
*ds
, int port
, int sset
)
1206 if (sset
!= ETH_SS_STATS
)
1209 return ARRAY_SIZE(ar8327_mib
);
1213 qca8k_set_mac_eee(struct dsa_switch
*ds
, int port
, struct ethtool_eee
*eee
)
1215 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
1216 u32 lpi_en
= QCA8K_REG_EEE_CTRL_LPI_EN(port
);
1220 mutex_lock(&priv
->reg_mutex
);
1221 ret
= qca8k_read(priv
, QCA8K_REG_EEE_CTRL
, ®
);
1225 if (eee
->eee_enabled
)
1229 ret
= qca8k_write(priv
, QCA8K_REG_EEE_CTRL
, reg
);
1232 mutex_unlock(&priv
->reg_mutex
);
1237 qca8k_get_mac_eee(struct dsa_switch
*ds
, int port
, struct ethtool_eee
*e
)
1239 /* Nothing to do on the port's MAC */
1244 qca8k_port_stp_state_set(struct dsa_switch
*ds
, int port
, u8 state
)
1246 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
1250 case BR_STATE_DISABLED
:
1251 stp_state
= QCA8K_PORT_LOOKUP_STATE_DISABLED
;
1253 case BR_STATE_BLOCKING
:
1254 stp_state
= QCA8K_PORT_LOOKUP_STATE_BLOCKING
;
1256 case BR_STATE_LISTENING
:
1257 stp_state
= QCA8K_PORT_LOOKUP_STATE_LISTENING
;
1259 case BR_STATE_LEARNING
:
1260 stp_state
= QCA8K_PORT_LOOKUP_STATE_LEARNING
;
1262 case BR_STATE_FORWARDING
:
1264 stp_state
= QCA8K_PORT_LOOKUP_STATE_FORWARD
;
1268 qca8k_rmw(priv
, QCA8K_PORT_LOOKUP_CTRL(port
),
1269 QCA8K_PORT_LOOKUP_STATE_MASK
, stp_state
);
1273 qca8k_port_bridge_join(struct dsa_switch
*ds
, int port
, struct net_device
*br
)
1275 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
1276 int port_mask
, cpu_port
;
1279 cpu_port
= dsa_to_port(ds
, port
)->cpu_dp
->index
;
1280 port_mask
= BIT(cpu_port
);
1282 for (i
= 0; i
< QCA8K_NUM_PORTS
; i
++) {
1283 if (dsa_is_cpu_port(ds
, i
))
1285 if (dsa_to_port(ds
, i
)->bridge_dev
!= br
)
1287 /* Add this port to the portvlan mask of the other ports
1290 ret
= qca8k_reg_set(priv
,
1291 QCA8K_PORT_LOOKUP_CTRL(i
),
1296 port_mask
|= BIT(i
);
1299 /* Add all other ports to this ports portvlan mask */
1300 ret
= qca8k_rmw(priv
, QCA8K_PORT_LOOKUP_CTRL(port
),
1301 QCA8K_PORT_LOOKUP_MEMBER
, port_mask
);
1307 qca8k_port_bridge_leave(struct dsa_switch
*ds
, int port
, struct net_device
*br
)
1309 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
1312 cpu_port
= dsa_to_port(ds
, port
)->cpu_dp
->index
;
1314 for (i
= 0; i
< QCA8K_NUM_PORTS
; i
++) {
1315 if (dsa_is_cpu_port(ds
, i
))
1317 if (dsa_to_port(ds
, i
)->bridge_dev
!= br
)
1319 /* Remove this port to the portvlan mask of the other ports
1322 qca8k_reg_clear(priv
,
1323 QCA8K_PORT_LOOKUP_CTRL(i
),
1327 /* Set the cpu port to be the only one in the portvlan mask of
1330 qca8k_rmw(priv
, QCA8K_PORT_LOOKUP_CTRL(port
),
1331 QCA8K_PORT_LOOKUP_MEMBER
, BIT(cpu_port
));
1334 void qca8k_port_fast_age(struct dsa_switch
*ds
, int port
)
1336 struct qca8k_priv
*priv
= ds
->priv
;
1338 mutex_lock(&priv
->reg_mutex
);
1339 qca8k_fdb_access(priv
, QCA8K_FDB_FLUSH_PORT
, port
);
1340 mutex_unlock(&priv
->reg_mutex
);
1343 int qca8k_set_ageing_time(struct dsa_switch
*ds
, unsigned int msecs
)
1345 struct qca8k_priv
*priv
= ds
->priv
;
1346 unsigned int secs
= msecs
/ 1000;
1349 /* AGE_TIME reg is set in 7s step */
1352 /* Handle case with 0 as val to NOT disable
1358 return qca8k_rmw(priv
, QCA8K_REG_ATU_CTRL
,
1359 QCA8K_ATU_AGE_TIME_MASK
,
1360 QCA8K_ATU_AGE_TIME(val
));
1364 qca8k_port_enable(struct dsa_switch
*ds
, int port
,
1365 struct phy_device
*phy
)
1367 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
1369 qca8k_port_set_status(priv
, port
, 1);
1370 priv
->port_sts
[port
].enabled
= 1;
1372 if (dsa_is_user_port(ds
, port
))
1373 phy_support_asym_pause(phy
);
1379 qca8k_port_disable(struct dsa_switch
*ds
, int port
)
1381 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
1383 qca8k_port_set_status(priv
, port
, 0);
1384 priv
->port_sts
[port
].enabled
= 0;
1388 qca8k_port_change_mtu(struct dsa_switch
*ds
, int port
, int new_mtu
)
1390 struct qca8k_priv
*priv
= ds
->priv
;
1393 priv
->port_mtu
[port
] = new_mtu
;
1395 for (i
= 0; i
< QCA8K_NUM_PORTS
; i
++)
1396 if (priv
->port_mtu
[i
] > mtu
)
1397 mtu
= priv
->port_mtu
[i
];
1399 /* Include L2 header / FCS length */
1400 return qca8k_write(priv
, QCA8K_MAX_FRAME_SIZE
, mtu
+ ETH_HLEN
+ ETH_FCS_LEN
);
1404 qca8k_port_max_mtu(struct dsa_switch
*ds
, int port
)
1406 return QCA8K_MAX_MTU
;
1410 qca8k_port_fdb_insert(struct qca8k_priv
*priv
, const u8
*addr
,
1411 u16 port_mask
, u16 vid
)
1413 /* Set the vid to the port vlan id if no vid is set */
1415 vid
= QCA8K_PORT_VID_DEF
;
1417 return qca8k_fdb_add(priv
, addr
, port_mask
, vid
,
1418 QCA8K_ATU_STATUS_STATIC
);
1422 qca8k_port_fdb_add(struct dsa_switch
*ds
, int port
,
1423 const unsigned char *addr
, u16 vid
)
1425 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
1426 u16 port_mask
= BIT(port
);
1428 return qca8k_port_fdb_insert(priv
, addr
, port_mask
, vid
);
1432 qca8k_port_fdb_del(struct dsa_switch
*ds
, int port
,
1433 const unsigned char *addr
, u16 vid
)
1435 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
1436 u16 port_mask
= BIT(port
);
1439 vid
= QCA8K_PORT_VID_DEF
;
1441 return qca8k_fdb_del(priv
, addr
, port_mask
, vid
);
1445 qca8k_port_fdb_dump(struct dsa_switch
*ds
, int port
,
1446 dsa_fdb_dump_cb_t
*cb
, void *data
)
1448 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
1449 struct qca8k_fdb _fdb
= { 0 };
1450 int cnt
= QCA8K_NUM_FDB_RECORDS
;
1454 mutex_lock(&priv
->reg_mutex
);
1455 while (cnt
-- && !qca8k_fdb_next(priv
, &_fdb
, port
)) {
1458 is_static
= (_fdb
.aging
== QCA8K_ATU_STATUS_STATIC
);
1459 ret
= cb(_fdb
.mac
, _fdb
.vid
, is_static
, data
);
1463 mutex_unlock(&priv
->reg_mutex
);
1469 qca8k_port_vlan_filtering(struct dsa_switch
*ds
, int port
, bool vlan_filtering
,
1470 struct netlink_ext_ack
*extack
)
1472 struct qca8k_priv
*priv
= ds
->priv
;
1474 if (vlan_filtering
) {
1475 qca8k_rmw(priv
, QCA8K_PORT_LOOKUP_CTRL(port
),
1476 QCA8K_PORT_LOOKUP_VLAN_MODE
,
1477 QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE
);
1479 qca8k_rmw(priv
, QCA8K_PORT_LOOKUP_CTRL(port
),
1480 QCA8K_PORT_LOOKUP_VLAN_MODE
,
1481 QCA8K_PORT_LOOKUP_VLAN_MODE_NONE
);
1488 qca8k_port_vlan_add(struct dsa_switch
*ds
, int port
,
1489 const struct switchdev_obj_port_vlan
*vlan
,
1490 struct netlink_ext_ack
*extack
)
1492 bool untagged
= vlan
->flags
& BRIDGE_VLAN_INFO_UNTAGGED
;
1493 bool pvid
= vlan
->flags
& BRIDGE_VLAN_INFO_PVID
;
1494 struct qca8k_priv
*priv
= ds
->priv
;
1497 ret
= qca8k_vlan_add(priv
, port
, vlan
->vid
, untagged
);
1499 dev_err(priv
->dev
, "Failed to add VLAN to port %d (%d)", port
, ret
);
1504 int shift
= 16 * (port
% 2);
1506 qca8k_rmw(priv
, QCA8K_EGRESS_VLAN(port
),
1507 0xfff << shift
, vlan
->vid
<< shift
);
1508 qca8k_write(priv
, QCA8K_REG_PORT_VLAN_CTRL0(port
),
1509 QCA8K_PORT_VLAN_CVID(vlan
->vid
) |
1510 QCA8K_PORT_VLAN_SVID(vlan
->vid
));
1516 qca8k_port_vlan_del(struct dsa_switch
*ds
, int port
,
1517 const struct switchdev_obj_port_vlan
*vlan
)
1519 struct qca8k_priv
*priv
= ds
->priv
;
1522 ret
= qca8k_vlan_del(priv
, port
, vlan
->vid
);
1524 dev_err(priv
->dev
, "Failed to delete VLAN from port %d (%d)", port
, ret
);
1529 static enum dsa_tag_protocol
1530 qca8k_get_tag_protocol(struct dsa_switch
*ds
, int port
,
1531 enum dsa_tag_protocol mp
)
1533 return DSA_TAG_PROTO_IPQ4019
;
1536 static const struct dsa_switch_ops qca8k_switch_ops
= {
1537 .get_tag_protocol
= qca8k_get_tag_protocol
,
1538 .setup
= qca8k_setup
,
1539 .get_strings
= qca8k_get_strings
,
1540 .get_ethtool_stats
= qca8k_get_ethtool_stats
,
1541 .get_sset_count
= qca8k_get_sset_count
,
1542 .set_ageing_time
= qca8k_set_ageing_time
,
1543 .get_mac_eee
= qca8k_get_mac_eee
,
1544 .set_mac_eee
= qca8k_set_mac_eee
,
1545 .port_enable
= qca8k_port_enable
,
1546 .port_disable
= qca8k_port_disable
,
1547 .port_change_mtu
= qca8k_port_change_mtu
,
1548 .port_max_mtu
= qca8k_port_max_mtu
,
1549 .port_stp_state_set
= qca8k_port_stp_state_set
,
1550 .port_bridge_join
= qca8k_port_bridge_join
,
1551 .port_bridge_leave
= qca8k_port_bridge_leave
,
1552 .port_fast_age
= qca8k_port_fast_age
,
1553 .port_fdb_add
= qca8k_port_fdb_add
,
1554 .port_fdb_del
= qca8k_port_fdb_del
,
1555 .port_fdb_dump
= qca8k_port_fdb_dump
,
1556 .port_vlan_filtering
= qca8k_port_vlan_filtering
,
1557 .port_vlan_add
= qca8k_port_vlan_add
,
1558 .port_vlan_del
= qca8k_port_vlan_del
,
1559 .phylink_validate
= qca8k_phylink_validate
,
1560 .phylink_mac_link_state
= qca8k_phylink_mac_link_state
,
1561 .phylink_mac_config
= qca8k_phylink_mac_config
,
1562 .phylink_mac_link_down
= qca8k_phylink_mac_link_down
,
1563 .phylink_mac_link_up
= qca8k_phylink_mac_link_up
,
1567 qca8k_ipq4019_probe(struct platform_device
*pdev
)
1569 struct qca8k_priv
*priv
;
1570 void __iomem
*base
, *psgmii
;
1571 struct device_node
*np
= pdev
->dev
.of_node
, *mdio_np
, *psgmii_ethphy_np
;
1574 priv
= devm_kzalloc(&pdev
->dev
, sizeof(*priv
), GFP_KERNEL
);
1578 priv
->dev
= &pdev
->dev
;
1580 base
= devm_platform_ioremap_resource_byname(pdev
, "base");
1582 return PTR_ERR(base
);
1584 priv
->regmap
= devm_regmap_init_mmio(priv
->dev
, base
,
1585 &qca8k_ipq4019_regmap_config
);
1586 if (IS_ERR(priv
->regmap
)) {
1587 ret
= PTR_ERR(priv
->regmap
);
1588 dev_err(priv
->dev
, "base regmap initialization failed, %d\n", ret
);
1592 psgmii
= devm_platform_ioremap_resource_byname(pdev
, "psgmii_phy");
1594 return PTR_ERR(psgmii
);
1596 priv
->psgmii
= devm_regmap_init_mmio(priv
->dev
, psgmii
,
1597 &qca8k_ipq4019_psgmii_phy_regmap_config
);
1598 if (IS_ERR(priv
->psgmii
)) {
1599 ret
= PTR_ERR(priv
->psgmii
);
1600 dev_err(priv
->dev
, "PSGMII regmap initialization failed, %d\n", ret
);
1604 mdio_np
= of_parse_phandle(np
, "mdio", 0);
1606 dev_err(&pdev
->dev
, "unable to get MDIO bus phandle\n");
1607 of_node_put(mdio_np
);
1611 priv
->bus
= of_mdio_find_bus(mdio_np
);
1612 of_node_put(mdio_np
);
1614 dev_err(&pdev
->dev
, "unable to find MDIO bus\n");
1615 return -EPROBE_DEFER
;
1618 psgmii_ethphy_np
= of_parse_phandle(np
, "psgmii-ethphy", 0);
1619 if (!psgmii_ethphy_np
) {
1620 dev_dbg(&pdev
->dev
, "unable to get PSGMII eth PHY phandle\n");
1621 of_node_put(psgmii_ethphy_np
);
1624 if (psgmii_ethphy_np
) {
1625 priv
->psgmii_ethphy
= of_phy_find_device(psgmii_ethphy_np
);
1626 of_node_put(psgmii_ethphy_np
);
1627 if (!priv
->psgmii_ethphy
) {
1628 dev_err(&pdev
->dev
, "unable to get PSGMII eth PHY\n");
1633 priv
->ds
= devm_kzalloc(priv
->dev
, sizeof(*priv
->ds
), GFP_KERNEL
);
1637 priv
->ds
->dev
= priv
->dev
;
1638 priv
->ds
->num_ports
= QCA8K_NUM_PORTS
;
1639 priv
->ds
->priv
= priv
;
1640 priv
->ops
= qca8k_switch_ops
;
1641 priv
->ds
->ops
= &priv
->ops
;
1643 mutex_init(&priv
->reg_mutex
);
1644 platform_set_drvdata(pdev
, priv
);
1646 return dsa_register_switch(priv
->ds
);
1650 qca8k_ipq4019_remove(struct platform_device
*pdev
)
1652 struct qca8k_priv
*priv
= dev_get_drvdata(&pdev
->dev
);
1658 for (i
= 0; i
< QCA8K_NUM_PORTS
; i
++)
1659 qca8k_port_set_status(priv
, i
, 0);
1661 dsa_unregister_switch(priv
->ds
);
1663 dev_set_drvdata(&pdev
->dev
, NULL
);
1668 static const struct of_device_id qca8k_ipq4019_of_match
[] = {
1669 { .compatible
= "qca,ipq4019-qca8337n" },
1673 static struct platform_driver qca8k_ipq4019_driver
= {
1674 .probe
= qca8k_ipq4019_probe
,
1675 .remove
= qca8k_ipq4019_remove
,
1677 .name
= "qca8k-ipq4019",
1678 .of_match_table
= qca8k_ipq4019_of_match
,
1682 module_platform_driver(qca8k_ipq4019_driver
);
1684 MODULE_AUTHOR("Mathieu Olivari, John Crispin <john@phrozen.org>");
1685 MODULE_AUTHOR("Gabor Juhos <j4g8y7@gmail.com>, Robert Marko <robert.marko@sartura.hr>");
1686 MODULE_DESCRIPTION("Qualcomm IPQ4019 built-in switch driver");
1687 MODULE_LICENSE("GPL v2");