1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
4 * Copyright (C) 2011-2012, 2020-2021 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (c) 2015, 2019, The Linux Foundation. All rights reserved.
6 * Copyright (c) 2016 John Crispin <john@phrozen.org>
7 * Copyright (c) 2021 Robert Marko <robert.marko@sartura.hr>
10 #include <linux/version.h>
11 #include <linux/etherdevice.h>
12 #include <linux/if_bridge.h>
13 #include <linux/mdio.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/module.h>
16 #include <linux/netdevice.h>
17 #include <linux/of_mdio.h>
18 #include <linux/of_net.h>
19 #include <linux/of_platform.h>
20 #include <linux/phy.h>
21 #include <linux/phylink.h>
22 #include <linux/reset.h>
25 #include "qca8k-ipq4019.h"
27 #define MIB_DESC(_s, _o, _n) \
34 static const struct qca8k_mib_desc ar8327_mib
[] = {
35 MIB_DESC(1, 0x00, "RxBroad"),
36 MIB_DESC(1, 0x04, "RxPause"),
37 MIB_DESC(1, 0x08, "RxMulti"),
38 MIB_DESC(1, 0x0c, "RxFcsErr"),
39 MIB_DESC(1, 0x10, "RxAlignErr"),
40 MIB_DESC(1, 0x14, "RxRunt"),
41 MIB_DESC(1, 0x18, "RxFragment"),
42 MIB_DESC(1, 0x1c, "Rx64Byte"),
43 MIB_DESC(1, 0x20, "Rx128Byte"),
44 MIB_DESC(1, 0x24, "Rx256Byte"),
45 MIB_DESC(1, 0x28, "Rx512Byte"),
46 MIB_DESC(1, 0x2c, "Rx1024Byte"),
47 MIB_DESC(1, 0x30, "Rx1518Byte"),
48 MIB_DESC(1, 0x34, "RxMaxByte"),
49 MIB_DESC(1, 0x38, "RxTooLong"),
50 MIB_DESC(2, 0x3c, "RxGoodByte"),
51 MIB_DESC(2, 0x44, "RxBadByte"),
52 MIB_DESC(1, 0x4c, "RxOverFlow"),
53 MIB_DESC(1, 0x50, "Filtered"),
54 MIB_DESC(1, 0x54, "TxBroad"),
55 MIB_DESC(1, 0x58, "TxPause"),
56 MIB_DESC(1, 0x5c, "TxMulti"),
57 MIB_DESC(1, 0x60, "TxUnderRun"),
58 MIB_DESC(1, 0x64, "Tx64Byte"),
59 MIB_DESC(1, 0x68, "Tx128Byte"),
60 MIB_DESC(1, 0x6c, "Tx256Byte"),
61 MIB_DESC(1, 0x70, "Tx512Byte"),
62 MIB_DESC(1, 0x74, "Tx1024Byte"),
63 MIB_DESC(1, 0x78, "Tx1518Byte"),
64 MIB_DESC(1, 0x7c, "TxMaxByte"),
65 MIB_DESC(1, 0x80, "TxOverSize"),
66 MIB_DESC(2, 0x84, "TxByte"),
67 MIB_DESC(1, 0x8c, "TxCollision"),
68 MIB_DESC(1, 0x90, "TxAbortCol"),
69 MIB_DESC(1, 0x94, "TxMultiCol"),
70 MIB_DESC(1, 0x98, "TxSingleCol"),
71 MIB_DESC(1, 0x9c, "TxExcDefer"),
72 MIB_DESC(1, 0xa0, "TxDefer"),
73 MIB_DESC(1, 0xa4, "TxLateCol"),
74 MIB_DESC(1, 0xa8, "RXUnicast"),
75 MIB_DESC(1, 0xac, "TXunicast"),
79 qca8k_read(struct qca8k_priv
*priv
, u32 reg
, u32
*val
)
81 return regmap_read(priv
->regmap
, reg
, val
);
85 qca8k_write(struct qca8k_priv
*priv
, u32 reg
, u32 val
)
87 return regmap_write(priv
->regmap
, reg
, val
);
91 qca8k_rmw(struct qca8k_priv
*priv
, u32 reg
, u32 mask
, u32 write_val
)
93 return regmap_update_bits(priv
->regmap
, reg
, mask
, write_val
);
97 qca8k_reg_set(struct qca8k_priv
*priv
, u32 reg
, u32 val
)
99 return regmap_set_bits(priv
->regmap
, reg
, val
);
103 qca8k_reg_clear(struct qca8k_priv
*priv
, u32 reg
, u32 val
)
105 return regmap_clear_bits(priv
->regmap
, reg
, val
);
108 static const struct regmap_range qca8k_readable_ranges
[] = {
109 regmap_reg_range(0x0000, 0x00e4), /* Global control */
110 regmap_reg_range(0x0100, 0x0168), /* EEE control */
111 regmap_reg_range(0x0200, 0x0270), /* Parser control */
112 regmap_reg_range(0x0400, 0x0454), /* ACL */
113 regmap_reg_range(0x0600, 0x0718), /* Lookup */
114 regmap_reg_range(0x0800, 0x0b70), /* QM */
115 regmap_reg_range(0x0c00, 0x0c80), /* PKT */
116 regmap_reg_range(0x0e00, 0x0e98), /* L3 */
117 regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */
118 regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */
119 regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */
120 regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */
121 regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */
122 regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */
123 regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */
127 static const struct regmap_access_table qca8k_readable_table
= {
128 .yes_ranges
= qca8k_readable_ranges
,
129 .n_yes_ranges
= ARRAY_SIZE(qca8k_readable_ranges
),
132 static struct regmap_config qca8k_ipq4019_regmap_config
= {
136 .max_register
= 0x16ac, /* end MIB - Port6 range */
137 .rd_table
= &qca8k_readable_table
,
140 static struct regmap_config qca8k_ipq4019_psgmii_phy_regmap_config
= {
141 .name
= "psgmii-phy",
145 .max_register
= 0x7fc,
149 qca8k_busy_wait(struct qca8k_priv
*priv
, u32 reg
, u32 mask
)
153 return regmap_read_poll_timeout(priv
->regmap
, reg
, val
,
156 QCA8K_BUSY_WAIT_TIMEOUT
);
160 qca8k_fdb_read(struct qca8k_priv
*priv
, struct qca8k_fdb
*fdb
)
165 /* load the ARL table into an array */
166 for (i
= 0; i
< 4; i
++) {
167 ret
= qca8k_read(priv
, QCA8K_REG_ATU_DATA0
+ (i
* 4), &val
);
175 fdb
->vid
= (reg
[2] >> QCA8K_ATU_VID_S
) & QCA8K_ATU_VID_M
;
177 fdb
->aging
= reg
[2] & QCA8K_ATU_STATUS_M
;
178 /* portmask - 54:48 */
179 fdb
->port_mask
= (reg
[1] >> QCA8K_ATU_PORT_S
) & QCA8K_ATU_PORT_M
;
181 fdb
->mac
[0] = (reg
[1] >> QCA8K_ATU_ADDR0_S
) & 0xff;
182 fdb
->mac
[1] = reg
[1] & 0xff;
183 fdb
->mac
[2] = (reg
[0] >> QCA8K_ATU_ADDR2_S
) & 0xff;
184 fdb
->mac
[3] = (reg
[0] >> QCA8K_ATU_ADDR3_S
) & 0xff;
185 fdb
->mac
[4] = (reg
[0] >> QCA8K_ATU_ADDR4_S
) & 0xff;
186 fdb
->mac
[5] = reg
[0] & 0xff;
192 qca8k_fdb_write(struct qca8k_priv
*priv
, u16 vid
, u8 port_mask
, const u8
*mac
,
199 reg
[2] = (vid
& QCA8K_ATU_VID_M
) << QCA8K_ATU_VID_S
;
201 reg
[2] |= aging
& QCA8K_ATU_STATUS_M
;
202 /* portmask - 54:48 */
203 reg
[1] = (port_mask
& QCA8K_ATU_PORT_M
) << QCA8K_ATU_PORT_S
;
205 reg
[1] |= mac
[0] << QCA8K_ATU_ADDR0_S
;
207 reg
[0] |= mac
[2] << QCA8K_ATU_ADDR2_S
;
208 reg
[0] |= mac
[3] << QCA8K_ATU_ADDR3_S
;
209 reg
[0] |= mac
[4] << QCA8K_ATU_ADDR4_S
;
212 /* load the array into the ARL table */
213 for (i
= 0; i
< 3; i
++)
214 qca8k_write(priv
, QCA8K_REG_ATU_DATA0
+ (i
* 4), reg
[i
]);
218 qca8k_fdb_access(struct qca8k_priv
*priv
, enum qca8k_fdb_cmd cmd
, int port
)
223 /* Set the command and FDB index */
224 reg
= QCA8K_ATU_FUNC_BUSY
;
227 reg
|= QCA8K_ATU_FUNC_PORT_EN
;
228 reg
|= (port
& QCA8K_ATU_FUNC_PORT_M
) << QCA8K_ATU_FUNC_PORT_S
;
231 /* Write the function register triggering the table access */
232 ret
= qca8k_write(priv
, QCA8K_REG_ATU_FUNC
, reg
);
236 /* wait for completion */
237 ret
= qca8k_busy_wait(priv
, QCA8K_REG_ATU_FUNC
, QCA8K_ATU_FUNC_BUSY
);
241 /* Check for table full violation when adding an entry */
242 if (cmd
== QCA8K_FDB_LOAD
) {
243 ret
= qca8k_read(priv
, QCA8K_REG_ATU_FUNC
, ®
);
246 if (reg
& QCA8K_ATU_FUNC_FULL
)
254 qca8k_fdb_next(struct qca8k_priv
*priv
, struct qca8k_fdb
*fdb
, int port
)
258 qca8k_fdb_write(priv
, fdb
->vid
, fdb
->port_mask
, fdb
->mac
, fdb
->aging
);
259 ret
= qca8k_fdb_access(priv
, QCA8K_FDB_NEXT
, port
);
263 return qca8k_fdb_read(priv
, fdb
);
267 qca8k_fdb_add(struct qca8k_priv
*priv
, const u8
*mac
, u16 port_mask
,
272 mutex_lock(&priv
->reg_mutex
);
273 qca8k_fdb_write(priv
, vid
, port_mask
, mac
, aging
);
274 ret
= qca8k_fdb_access(priv
, QCA8K_FDB_LOAD
, -1);
275 mutex_unlock(&priv
->reg_mutex
);
281 qca8k_fdb_del(struct qca8k_priv
*priv
, const u8
*mac
, u16 port_mask
, u16 vid
)
285 mutex_lock(&priv
->reg_mutex
);
286 qca8k_fdb_write(priv
, vid
, port_mask
, mac
, 0);
287 ret
= qca8k_fdb_access(priv
, QCA8K_FDB_PURGE
, -1);
288 mutex_unlock(&priv
->reg_mutex
);
294 qca8k_fdb_flush(struct qca8k_priv
*priv
)
296 mutex_lock(&priv
->reg_mutex
);
297 qca8k_fdb_access(priv
, QCA8K_FDB_FLUSH
, -1);
298 mutex_unlock(&priv
->reg_mutex
);
302 qca8k_vlan_access(struct qca8k_priv
*priv
, enum qca8k_vlan_cmd cmd
, u16 vid
)
307 /* Set the command and VLAN index */
308 reg
= QCA8K_VTU_FUNC1_BUSY
;
310 reg
|= vid
<< QCA8K_VTU_FUNC1_VID_S
;
312 /* Write the function register triggering the table access */
313 ret
= qca8k_write(priv
, QCA8K_REG_VTU_FUNC1
, reg
);
317 /* wait for completion */
318 ret
= qca8k_busy_wait(priv
, QCA8K_REG_VTU_FUNC1
, QCA8K_VTU_FUNC1_BUSY
);
322 /* Check for table full violation when adding an entry */
323 if (cmd
== QCA8K_VLAN_LOAD
) {
324 ret
= qca8k_read(priv
, QCA8K_REG_VTU_FUNC1
, ®
);
327 if (reg
& QCA8K_VTU_FUNC1_FULL
)
335 qca8k_vlan_add(struct qca8k_priv
*priv
, u8 port
, u16 vid
, bool untagged
)
341 We do the right thing with VLAN 0 and treat it as untagged while
342 preserving the tag on egress.
347 mutex_lock(&priv
->reg_mutex
);
348 ret
= qca8k_vlan_access(priv
, QCA8K_VLAN_READ
, vid
);
352 ret
= qca8k_read(priv
, QCA8K_REG_VTU_FUNC0
, ®
);
355 reg
|= QCA8K_VTU_FUNC0_VALID
| QCA8K_VTU_FUNC0_IVL_EN
;
356 reg
&= ~(QCA8K_VTU_FUNC0_EG_MODE_MASK
<< QCA8K_VTU_FUNC0_EG_MODE_S(port
));
358 reg
|= QCA8K_VTU_FUNC0_EG_MODE_UNTAG
<<
359 QCA8K_VTU_FUNC0_EG_MODE_S(port
);
361 reg
|= QCA8K_VTU_FUNC0_EG_MODE_TAG
<<
362 QCA8K_VTU_FUNC0_EG_MODE_S(port
);
364 ret
= qca8k_write(priv
, QCA8K_REG_VTU_FUNC0
, reg
);
367 ret
= qca8k_vlan_access(priv
, QCA8K_VLAN_LOAD
, vid
);
370 mutex_unlock(&priv
->reg_mutex
);
376 qca8k_vlan_del(struct qca8k_priv
*priv
, u8 port
, u16 vid
)
382 mutex_lock(&priv
->reg_mutex
);
383 ret
= qca8k_vlan_access(priv
, QCA8K_VLAN_READ
, vid
);
387 ret
= qca8k_read(priv
, QCA8K_REG_VTU_FUNC0
, ®
);
390 reg
&= ~(3 << QCA8K_VTU_FUNC0_EG_MODE_S(port
));
391 reg
|= QCA8K_VTU_FUNC0_EG_MODE_NOT
<<
392 QCA8K_VTU_FUNC0_EG_MODE_S(port
);
394 /* Check if we're the last member to be removed */
396 for (i
= 0; i
< QCA8K_NUM_PORTS
; i
++) {
397 mask
= QCA8K_VTU_FUNC0_EG_MODE_NOT
;
398 mask
<<= QCA8K_VTU_FUNC0_EG_MODE_S(i
);
400 if ((reg
& mask
) != mask
) {
407 ret
= qca8k_vlan_access(priv
, QCA8K_VLAN_PURGE
, vid
);
409 ret
= qca8k_write(priv
, QCA8K_REG_VTU_FUNC0
, reg
);
412 ret
= qca8k_vlan_access(priv
, QCA8K_VLAN_LOAD
, vid
);
416 mutex_unlock(&priv
->reg_mutex
);
422 qca8k_mib_init(struct qca8k_priv
*priv
)
426 mutex_lock(&priv
->reg_mutex
);
427 ret
= qca8k_reg_set(priv
, QCA8K_REG_MIB
, QCA8K_MIB_FLUSH
| QCA8K_MIB_BUSY
);
431 ret
= qca8k_busy_wait(priv
, QCA8K_REG_MIB
, QCA8K_MIB_BUSY
);
435 ret
= qca8k_reg_set(priv
, QCA8K_REG_MIB
, QCA8K_MIB_CPU_KEEP
);
439 ret
= qca8k_write(priv
, QCA8K_REG_MODULE_EN
, QCA8K_MODULE_EN_MIB
);
442 mutex_unlock(&priv
->reg_mutex
);
447 qca8k_port_set_status(struct qca8k_priv
*priv
, int port
, int enable
)
449 u32 mask
= QCA8K_PORT_STATUS_TXMAC
| QCA8K_PORT_STATUS_RXMAC
;
451 /* Port 0 is internally connected to the CPU
452 * TODO: Probably check for RGMII as well if it doesnt work
455 if (port
> QCA8K_CPU_PORT
)
456 mask
|= QCA8K_PORT_STATUS_LINK_AUTO
;
459 qca8k_reg_set(priv
, QCA8K_REG_PORT_STATUS(port
), mask
);
461 qca8k_reg_clear(priv
, QCA8K_REG_PORT_STATUS(port
), mask
);
465 qca8k_setup_port(struct dsa_switch
*ds
, int port
)
467 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
470 /* CPU port gets connected to all user ports of the switch */
471 if (dsa_is_cpu_port(ds
, port
)) {
472 ret
= qca8k_rmw(priv
, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT
),
473 QCA8K_PORT_LOOKUP_MEMBER
, dsa_user_ports(ds
));
477 /* Disable CPU ARP Auto-learning by default */
478 ret
= qca8k_reg_clear(priv
, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT
),
479 QCA8K_PORT_LOOKUP_LEARN
);
484 /* Individual user ports get connected to CPU port only */
485 if (dsa_is_user_port(ds
, port
)) {
486 int shift
= 16 * (port
% 2);
488 ret
= qca8k_rmw(priv
, QCA8K_PORT_LOOKUP_CTRL(port
),
489 QCA8K_PORT_LOOKUP_MEMBER
,
490 BIT(QCA8K_CPU_PORT
));
494 /* Enable ARP Auto-learning by default */
495 ret
= qca8k_reg_set(priv
, QCA8K_PORT_LOOKUP_CTRL(port
),
496 QCA8K_PORT_LOOKUP_LEARN
);
500 /* For port based vlans to work we need to set the
503 ret
= qca8k_rmw(priv
, QCA8K_EGRESS_VLAN(port
),
505 QCA8K_PORT_VID_DEF
<< shift
);
509 ret
= qca8k_write(priv
, QCA8K_REG_PORT_VLAN_CTRL0(port
),
510 QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF
) |
511 QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF
));
520 qca8k_setup(struct dsa_switch
*ds
)
522 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
525 /* Make sure that port 0 is the cpu port */
526 if (!dsa_is_cpu_port(ds
, 0)) {
527 dev_err(priv
->dev
, "port 0 is not the CPU port");
531 /* Enable CPU Port */
532 ret
= qca8k_reg_set(priv
, QCA8K_REG_GLOBAL_FW_CTRL0
,
533 QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN
);
535 dev_err(priv
->dev
, "failed enabling CPU port");
539 /* Enable MIB counters */
540 ret
= qca8k_mib_init(priv
);
542 dev_warn(priv
->dev
, "MIB init failed");
544 /* Enable QCA header mode on the cpu port */
545 ret
= qca8k_write(priv
, QCA8K_REG_PORT_HDR_CTRL(QCA8K_CPU_PORT
),
546 QCA8K_PORT_HDR_CTRL_ALL
<< QCA8K_PORT_HDR_CTRL_TX_S
|
547 QCA8K_PORT_HDR_CTRL_ALL
<< QCA8K_PORT_HDR_CTRL_RX_S
);
549 dev_err(priv
->dev
, "failed enabling QCA header mode");
553 /* Disable forwarding by default on all ports */
554 for (i
= 0; i
< QCA8K_NUM_PORTS
; i
++) {
555 ret
= qca8k_rmw(priv
, QCA8K_PORT_LOOKUP_CTRL(i
),
556 QCA8K_PORT_LOOKUP_MEMBER
, 0);
561 /* Disable MAC by default on all ports */
562 for (i
= 1; i
< QCA8K_NUM_PORTS
; i
++)
563 qca8k_port_set_status(priv
, i
, 0);
565 /* Forward all unknown frames to CPU port for Linux processing */
566 ret
= qca8k_write(priv
, QCA8K_REG_GLOBAL_FW_CTRL1
,
567 BIT(QCA8K_CPU_PORT
) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S
|
568 BIT(QCA8K_CPU_PORT
) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S
|
569 BIT(QCA8K_CPU_PORT
) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S
|
570 BIT(QCA8K_CPU_PORT
) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S
);
574 /* Setup connection between CPU port & user ports */
575 for (i
= 0; i
< QCA8K_NUM_PORTS
; i
++) {
576 ret
= qca8k_setup_port(ds
, i
);
581 /* Setup our port MTUs to match power on defaults */
582 for (i
= 0; i
< QCA8K_NUM_PORTS
; i
++)
583 /* Set per port MTU to 1500 as the MTU change function
584 * will add the overhead and if its set to 1518 then it
585 * will apply the overhead again and we will end up with
586 * MTU of 1536 instead of 1518
588 priv
->port_mtu
[i
] = ETH_DATA_LEN
;
589 ret
= qca8k_write(priv
, QCA8K_MAX_FRAME_SIZE
, ETH_FRAME_LEN
+ ETH_FCS_LEN
);
591 dev_warn(priv
->dev
, "failed setting MTU settings");
593 /* Flush the FDB table */
594 qca8k_fdb_flush(priv
);
596 /* We don't have interrupts for link changes, so we need to poll */
599 /* CPU port HW learning doesnt work correctly, so let DSA handle it */
600 ds
->assisted_learning_on_cpu_port
= true;
605 static int psgmii_vco_calibrate(struct qca8k_priv
*priv
)
609 if (!priv
->psgmii_ethphy
) {
610 dev_err(priv
->dev
, "PSGMII eth PHY missing, calibration failed!\n");
614 /* Fix PSGMII RX 20bit */
615 ret
= phy_write(priv
->psgmii_ethphy
, MII_BMCR
, 0x5b);
616 /* Reset PHY PSGMII */
617 ret
= phy_write(priv
->psgmii_ethphy
, MII_BMCR
, 0x1b);
618 /* Release PHY PSGMII reset */
619 ret
= phy_write(priv
->psgmii_ethphy
, MII_BMCR
, 0x5b);
621 /* Poll for VCO PLL calibration finish - Malibu(QCA8075) */
622 ret
= phy_read_mmd_poll_timeout(priv
->psgmii_ethphy
,
629 dev_err(priv
->dev
, "QCA807x PSGMII VCO calibration PLL not ready\n");
634 /* Freeze PSGMII RX CDR */
635 ret
= phy_write(priv
->psgmii_ethphy
, MII_RESV2
, 0x2230);
637 /* Start PSGMIIPHY VCO PLL calibration */
638 ret
= regmap_set_bits(priv
->psgmii
,
639 PSGMIIPHY_VCO_CALIBRATION_CONTROL_REGISTER_1
,
640 PSGMIIPHY_REG_PLL_VCO_CALIB_RESTART
);
642 /* Poll for PSGMIIPHY PLL calibration finish - Dakota(IPQ40xx) */
643 ret
= regmap_read_poll_timeout(priv
->psgmii
,
644 PSGMIIPHY_VCO_CALIBRATION_CONTROL_REGISTER_2
,
645 val
, val
& PSGMIIPHY_REG_PLL_VCO_CALIB_READY
,
648 dev_err(priv
->dev
, "IPQ PSGMIIPHY VCO calibration PLL not ready\n");
653 /* Release PSGMII RX CDR */
654 ret
= phy_write(priv
->psgmii_ethphy
, MII_RESV2
, 0x3230);
655 /* Release PSGMII RX 20bit */
656 ret
= phy_write(priv
->psgmii_ethphy
, MII_BMCR
, 0x5f);
663 qca8k_switch_port_loopback_on_off(struct qca8k_priv
*priv
, int port
, int on
)
665 u32 val
= QCA8K_PORT_LOOKUP_LOOPBACK
;
670 qca8k_rmw(priv
, QCA8K_PORT_LOOKUP_CTRL(port
),
671 QCA8K_PORT_LOOKUP_LOOPBACK
, val
);
675 qca8k_wait_for_phy_link_state(struct phy_device
*phy
, int need_status
)
680 for (a
= 0; a
< 100; a
++) {
681 status
= phy_read(phy
, MII_QCA8075_SSTATUS
);
682 status
&= QCA8075_PHY_SPEC_STATUS_LINK
;
684 if (status
== need_status
)
693 qca8k_phy_loopback_on_off(struct qca8k_priv
*priv
, struct phy_device
*phy
,
697 phy_write(phy
, MII_BMCR
, BMCR_ANENABLE
| BMCR_RESET
);
698 phy_modify(phy
, MII_BMCR
, BMCR_PDOWN
, BMCR_PDOWN
);
699 qca8k_wait_for_phy_link_state(phy
, 0);
700 qca8k_write(priv
, QCA8K_REG_PORT_STATUS(sw_port
), 0);
701 phy_write(phy
, MII_BMCR
,
705 qca8k_wait_for_phy_link_state(phy
, 1);
706 qca8k_write(priv
, QCA8K_REG_PORT_STATUS(sw_port
),
707 QCA8K_PORT_STATUS_SPEED_1000
|
708 QCA8K_PORT_STATUS_TXMAC
|
709 QCA8K_PORT_STATUS_RXMAC
|
710 QCA8K_PORT_STATUS_DUPLEX
);
711 qca8k_rmw(priv
, QCA8K_PORT_LOOKUP_CTRL(sw_port
),
712 QCA8K_PORT_LOOKUP_STATE_FORWARD
,
713 QCA8K_PORT_LOOKUP_STATE_FORWARD
);
715 qca8k_write(priv
, QCA8K_REG_PORT_STATUS(sw_port
), 0);
716 qca8k_rmw(priv
, QCA8K_PORT_LOOKUP_CTRL(sw_port
),
717 QCA8K_PORT_LOOKUP_STATE_DISABLED
,
718 QCA8K_PORT_LOOKUP_STATE_DISABLED
);
719 phy_write(phy
, MII_BMCR
, BMCR_SPEED1000
| BMCR_ANENABLE
| BMCR_RESET
);
720 /* turn off the power of the phys - so that unused
721 ports do not raise links */
722 phy_modify(phy
, MII_BMCR
, BMCR_PDOWN
, BMCR_PDOWN
);
727 qca8k_phy_pkt_gen_prep(struct qca8k_priv
*priv
, struct phy_device
*phy
,
728 int pkts_num
, int on
)
731 /* enable CRC checker and packets counters */
732 phy_write_mmd(phy
, MDIO_MMD_AN
, QCA8075_MMD7_CRC_AND_PKTS_COUNT
, 0);
733 phy_write_mmd(phy
, MDIO_MMD_AN
, QCA8075_MMD7_CRC_AND_PKTS_COUNT
,
734 QCA8075_MMD7_CNT_FRAME_CHK_EN
| QCA8075_MMD7_CNT_SELFCLR
);
735 qca8k_wait_for_phy_link_state(phy
, 1);
737 phy_write_mmd(phy
, MDIO_MMD_AN
, QCA8075_MMD7_PKT_GEN_PKT_NUMB
, pkts_num
);
738 /* pkt size - 1504 bytes + 20 bytes */
739 phy_write_mmd(phy
, MDIO_MMD_AN
, QCA8075_MMD7_PKT_GEN_PKT_SIZE
, 1504);
742 phy_write_mmd(phy
, MDIO_MMD_AN
, QCA8075_MMD7_PKT_GEN_PKT_NUMB
, 0);
743 /* disable CRC checker and packet counter */
744 phy_write_mmd(phy
, MDIO_MMD_AN
, QCA8075_MMD7_CRC_AND_PKTS_COUNT
, 0);
745 /* disable traffic gen */
746 phy_write_mmd(phy
, MDIO_MMD_AN
, QCA8075_MMD7_PKT_GEN_CTRL
, 0);
751 qca8k_wait_for_phy_pkt_gen_fin(struct qca8k_priv
*priv
, struct phy_device
*phy
)
754 /* wait for all traffic end: 4096(pkt num)*1524(size)*8ns(125MHz)=49938us */
755 phy_read_mmd_poll_timeout(phy
, MDIO_MMD_AN
, QCA8075_MMD7_PKT_GEN_CTRL
,
756 val
, !(val
& QCA8075_MMD7_PKT_GEN_INPROGR
),
757 50000, 1000000, true);
761 qca8k_start_phy_pkt_gen(struct phy_device
*phy
)
763 /* start traffic gen */
764 phy_write_mmd(phy
, MDIO_MMD_AN
, QCA8075_MMD7_PKT_GEN_CTRL
,
765 QCA8075_MMD7_PKT_GEN_START
| QCA8075_MMD7_PKT_GEN_INPROGR
);
769 qca8k_start_all_phys_pkt_gens(struct qca8k_priv
*priv
)
771 struct phy_device
*phy
;
772 phy
= phy_device_create(priv
->bus
, QCA8075_MDIO_BRDCST_PHY_ADDR
,
775 dev_err(priv
->dev
, "unable to create mdio broadcast PHY(0x%x)\n",
776 QCA8075_MDIO_BRDCST_PHY_ADDR
);
780 qca8k_start_phy_pkt_gen(phy
);
782 phy_device_free(phy
);
787 qca8k_get_phy_pkt_gen_test_result(struct phy_device
*phy
, int pkts_num
)
793 u32 tx_all_ok
, rx_all_ok
;
796 tx_ok
= phy_read_mmd(phy
, MDIO_MMD_AN
, QCA8075_MMD7_EG_FRAME_RECV_CNT_LO
);
797 tx_ok_high16
= phy_read_mmd(phy
, MDIO_MMD_AN
, QCA8075_MMD7_EG_FRAME_RECV_CNT_HI
);
798 tx_error
= phy_read_mmd(phy
, MDIO_MMD_AN
, QCA8075_MMD7_EG_FRAME_ERR_CNT
);
799 rx_ok
= phy_read_mmd(phy
, MDIO_MMD_AN
, QCA8075_MMD7_IG_FRAME_RECV_CNT_LO
);
800 rx_ok_high16
= phy_read_mmd(phy
, MDIO_MMD_AN
, QCA8075_MMD7_IG_FRAME_RECV_CNT_HI
);
801 rx_error
= phy_read_mmd(phy
, MDIO_MMD_AN
, QCA8075_MMD7_IG_FRAME_ERR_CNT
);
802 tx_all_ok
= tx_ok
+ (tx_ok_high16
<< 16);
803 rx_all_ok
= rx_ok
+ (rx_ok_high16
<< 16);
805 if (tx_all_ok
< pkts_num
)
807 if(rx_all_ok
< pkts_num
)
813 return 0; /* test is ok */
817 void qca8k_phy_broadcast_write_on_off(struct qca8k_priv
*priv
,
818 struct phy_device
*phy
, int on
)
822 val
= phy_read_mmd(phy
, MDIO_MMD_AN
, QCA8075_MMD7_MDIO_BRDCST_WRITE
);
825 val
&= ~QCA8075_MMD7_MDIO_BRDCST_WRITE_EN
;
827 val
|= QCA8075_MMD7_MDIO_BRDCST_WRITE_EN
;
829 phy_write_mmd(phy
, MDIO_MMD_AN
, QCA8075_MMD7_MDIO_BRDCST_WRITE
, val
);
833 qca8k_test_dsa_port_for_errors(struct qca8k_priv
*priv
, struct phy_device
*phy
,
834 int port
, int test_phase
)
837 const int test_pkts_num
= QCA8075_PKT_GEN_PKTS_COUNT
;
839 if (test_phase
== 1) { /* start test preps */
840 qca8k_phy_loopback_on_off(priv
, phy
, port
, 1);
841 qca8k_switch_port_loopback_on_off(priv
, port
, 1);
842 qca8k_phy_broadcast_write_on_off(priv
, phy
, 1);
843 qca8k_phy_pkt_gen_prep(priv
, phy
, test_pkts_num
, 1);
844 } else if (test_phase
== 2) {
845 /* wait for test results, collect it and cleanup */
846 qca8k_wait_for_phy_pkt_gen_fin(priv
, phy
);
847 res
= qca8k_get_phy_pkt_gen_test_result(phy
, test_pkts_num
);
848 qca8k_phy_pkt_gen_prep(priv
, phy
, test_pkts_num
, 0);
849 qca8k_phy_broadcast_write_on_off(priv
, phy
, 0);
850 qca8k_switch_port_loopback_on_off(priv
, port
, 0);
851 qca8k_phy_loopback_on_off(priv
, phy
, port
, 0);
858 qca8k_do_dsa_sw_ports_self_test(struct qca8k_priv
*priv
, int parallel_test
)
860 struct device_node
*dn
= priv
->dev
->of_node
;
861 struct device_node
*ports
, *port
;
862 struct device_node
*phy_dn
;
863 struct phy_device
*phy
;
864 int reg
, err
= 0, test_phase
;
865 u32 tests_result
= 0;
867 ports
= of_get_child_by_name(dn
, "ports");
869 dev_err(priv
->dev
, "no ports child node found\n");
873 for (test_phase
= 1; test_phase
<= 2; test_phase
++) {
874 if (parallel_test
&& test_phase
== 2) {
875 err
= qca8k_start_all_phys_pkt_gens(priv
);
879 for_each_available_child_of_node(ports
, port
) {
880 err
= of_property_read_u32(port
, "reg", ®
);
883 if (reg
>= QCA8K_NUM_PORTS
) {
887 phy_dn
= of_parse_phandle(port
, "phy-handle", 0);
889 phy
= of_phy_find_device(phy_dn
);
893 result
= qca8k_test_dsa_port_for_errors(priv
,
894 phy
, reg
, test_phase
);
895 if (!parallel_test
&& test_phase
== 1)
896 qca8k_start_phy_pkt_gen(phy
);
897 put_device(&phy
->mdio
.dev
);
898 if (test_phase
== 2) {
910 qca8k_fdb_flush(priv
);
913 tests_result
|= 0xf000;
918 psgmii_vco_calibrate_and_test(struct dsa_switch
*ds
)
920 int ret
, a
, test_result
;
921 struct qca8k_priv
*priv
= ds
->priv
;
923 for (a
= 0; a
<= QCA8K_PSGMII_CALB_NUM
; a
++) {
924 ret
= psgmii_vco_calibrate(priv
);
927 /* first we run serial test */
928 test_result
= qca8k_do_dsa_sw_ports_self_test(priv
, 0);
929 /* and if it is ok then we run the test in parallel */
931 test_result
= qca8k_do_dsa_sw_ports_self_test(priv
, 1);
934 dev_warn(priv
->dev
, "PSGMII work was stabilized after %d "
935 "calibration retries !\n", a
);
940 if (a
> 0 && a
% 10 == 0) {
941 dev_err(priv
->dev
, "PSGMII work is unstable !!! "
942 "Let's try to wait a bit ... %d\n", a
);
943 set_current_state(TASK_INTERRUPTIBLE
);
944 schedule_timeout(msecs_to_jiffies(a
* 100));
949 panic("PSGMII work is unstable !!! "
950 "Repeated recalibration attempts did not help(0x%x) !\n",
957 ipq4019_psgmii_configure(struct dsa_switch
*ds
)
959 struct qca8k_priv
*priv
= ds
->priv
;
962 if (!priv
->psgmii_calibrated
) {
963 ret
= psgmii_vco_calibrate_and_test(ds
);
965 ret
= regmap_clear_bits(priv
->psgmii
, PSGMIIPHY_MODE_CONTROL
,
966 PSGMIIPHY_MODE_ATHR_CSCO_MODE_25M
);
967 ret
= regmap_write(priv
->psgmii
, PSGMIIPHY_TX_CONTROL
,
968 PSGMIIPHY_TX_CONTROL_MAGIC_VALUE
);
970 priv
->psgmii_calibrated
= true;
979 qca8k_phylink_mac_config(struct dsa_switch
*ds
, int port
, unsigned int mode
,
980 const struct phylink_link_state
*state
)
982 struct qca8k_priv
*priv
= ds
->priv
;
986 /* CPU port, no configuration needed */
991 if (state
->interface
== PHY_INTERFACE_MODE_PSGMII
)
992 if (ipq4019_psgmii_configure(ds
))
993 dev_err(ds
->dev
, "PSGMII configuration failed!\n");
997 if (state
->interface
== PHY_INTERFACE_MODE_RGMII
||
998 state
->interface
== PHY_INTERFACE_MODE_RGMII_ID
||
999 state
->interface
== PHY_INTERFACE_MODE_RGMII_RXID
||
1000 state
->interface
== PHY_INTERFACE_MODE_RGMII_TXID
) {
1001 qca8k_reg_set(priv
, QCA8K_REG_RGMII_CTRL
, QCA8K_RGMII_CTRL_CLK
);
1004 if (state
->interface
== PHY_INTERFACE_MODE_PSGMII
)
1005 if (ipq4019_psgmii_configure(ds
))
1006 dev_err(ds
->dev
, "PSGMII configuration failed!\n");
1009 dev_err(ds
->dev
, "%s: unsupported port: %i\n", __func__
, port
);
1015 qca8k_phylink_validate(struct dsa_switch
*ds
, int port
,
1016 unsigned long *supported
,
1017 struct phylink_link_state
*state
)
1019 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask
) = { 0, };
1022 case 0: /* CPU port */
1023 if (state
->interface
!= PHY_INTERFACE_MODE_INTERNAL
)
1029 /* Only PSGMII mode is supported */
1030 if (state
->interface
!= PHY_INTERFACE_MODE_PSGMII
)
1035 /* PSGMII and RGMII modes are supported */
1036 if (state
->interface
!= PHY_INTERFACE_MODE_PSGMII
&&
1037 state
->interface
!= PHY_INTERFACE_MODE_RGMII
&&
1038 state
->interface
!= PHY_INTERFACE_MODE_RGMII_ID
&&
1039 state
->interface
!= PHY_INTERFACE_MODE_RGMII_RXID
&&
1040 state
->interface
!= PHY_INTERFACE_MODE_RGMII_TXID
)
1045 dev_warn(ds
->dev
, "interface '%s' (%d) on port %d is not supported\n",
1046 phy_modes(state
->interface
), state
->interface
, port
);
1047 linkmode_zero(supported
);
1052 phylink_set_port_modes(mask
);
1054 phylink_set(mask
, 1000baseT_Full
);
1056 phylink_set(mask
, Pause
);
1057 phylink_set(mask
, Asym_Pause
);
1059 linkmode_and(supported
, supported
, mask
);
1060 linkmode_and(state
->advertising
, state
->advertising
, mask
);
1062 /* Simply copy what PHYs tell us */
1063 linkmode_copy(state
->advertising
, supported
);
1068 qca8k_phylink_mac_link_state(struct dsa_switch
*ds
, int port
,
1069 struct phylink_link_state
*state
)
1071 struct qca8k_priv
*priv
= ds
->priv
;
1075 ret
= qca8k_read(priv
, QCA8K_REG_PORT_STATUS(port
), ®
);
1079 state
->link
= !!(reg
& QCA8K_PORT_STATUS_LINK_UP
);
1080 state
->an_complete
= state
->link
;
1081 state
->an_enabled
= !!(reg
& QCA8K_PORT_STATUS_LINK_AUTO
);
1082 state
->duplex
= (reg
& QCA8K_PORT_STATUS_DUPLEX
) ? DUPLEX_FULL
:
1085 switch (reg
& QCA8K_PORT_STATUS_SPEED
) {
1086 case QCA8K_PORT_STATUS_SPEED_10
:
1087 state
->speed
= SPEED_10
;
1089 case QCA8K_PORT_STATUS_SPEED_100
:
1090 state
->speed
= SPEED_100
;
1092 case QCA8K_PORT_STATUS_SPEED_1000
:
1093 state
->speed
= SPEED_1000
;
1096 state
->speed
= SPEED_UNKNOWN
;
1100 state
->pause
= MLO_PAUSE_NONE
;
1101 if (reg
& QCA8K_PORT_STATUS_RXFLOW
)
1102 state
->pause
|= MLO_PAUSE_RX
;
1103 if (reg
& QCA8K_PORT_STATUS_TXFLOW
)
1104 state
->pause
|= MLO_PAUSE_TX
;
1110 qca8k_phylink_mac_link_down(struct dsa_switch
*ds
, int port
, unsigned int mode
,
1111 phy_interface_t interface
)
1113 struct qca8k_priv
*priv
= ds
->priv
;
1115 qca8k_port_set_status(priv
, port
, 0);
1119 qca8k_phylink_mac_link_up(struct dsa_switch
*ds
, int port
, unsigned int mode
,
1120 phy_interface_t interface
, struct phy_device
*phydev
,
1121 int speed
, int duplex
, bool tx_pause
, bool rx_pause
)
1123 struct qca8k_priv
*priv
= ds
->priv
;
1126 if (phylink_autoneg_inband(mode
)) {
1127 reg
= QCA8K_PORT_STATUS_LINK_AUTO
;
1131 reg
= QCA8K_PORT_STATUS_SPEED_10
;
1134 reg
= QCA8K_PORT_STATUS_SPEED_100
;
1137 reg
= QCA8K_PORT_STATUS_SPEED_1000
;
1140 reg
= QCA8K_PORT_STATUS_LINK_AUTO
;
1144 if (duplex
== DUPLEX_FULL
)
1145 reg
|= QCA8K_PORT_STATUS_DUPLEX
;
1147 if (rx_pause
|| dsa_is_cpu_port(ds
, port
))
1148 reg
|= QCA8K_PORT_STATUS_RXFLOW
;
1150 if (tx_pause
|| dsa_is_cpu_port(ds
, port
))
1151 reg
|= QCA8K_PORT_STATUS_TXFLOW
;
1154 reg
|= QCA8K_PORT_STATUS_TXMAC
| QCA8K_PORT_STATUS_RXMAC
;
1156 qca8k_write(priv
, QCA8K_REG_PORT_STATUS(port
), reg
);
1160 qca8k_get_strings(struct dsa_switch
*ds
, int port
, u32 stringset
, uint8_t *data
)
1164 if (stringset
!= ETH_SS_STATS
)
1167 for (i
= 0; i
< ARRAY_SIZE(ar8327_mib
); i
++)
1168 strncpy(data
+ i
* ETH_GSTRING_LEN
, ar8327_mib
[i
].name
,
1173 qca8k_get_ethtool_stats(struct dsa_switch
*ds
, int port
,
1176 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
1177 const struct qca8k_mib_desc
*mib
;
1182 for (i
= 0; i
< ARRAY_SIZE(ar8327_mib
); i
++) {
1183 mib
= &ar8327_mib
[i
];
1184 reg
= QCA8K_PORT_MIB_COUNTER(port
) + mib
->offset
;
1186 ret
= qca8k_read(priv
, reg
, &val
);
1190 if (mib
->size
== 2) {
1191 ret
= qca8k_read(priv
, reg
+ 4, &hi
);
1198 data
[i
] |= (u64
)hi
<< 32;
1203 qca8k_get_sset_count(struct dsa_switch
*ds
, int port
, int sset
)
1205 if (sset
!= ETH_SS_STATS
)
1208 return ARRAY_SIZE(ar8327_mib
);
1212 qca8k_set_mac_eee(struct dsa_switch
*ds
, int port
, struct ethtool_eee
*eee
)
1214 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
1215 u32 lpi_en
= QCA8K_REG_EEE_CTRL_LPI_EN(port
);
1219 mutex_lock(&priv
->reg_mutex
);
1220 ret
= qca8k_read(priv
, QCA8K_REG_EEE_CTRL
, ®
);
1224 if (eee
->eee_enabled
)
1228 ret
= qca8k_write(priv
, QCA8K_REG_EEE_CTRL
, reg
);
1231 mutex_unlock(&priv
->reg_mutex
);
1236 qca8k_get_mac_eee(struct dsa_switch
*ds
, int port
, struct ethtool_eee
*e
)
1238 /* Nothing to do on the port's MAC */
1243 qca8k_port_stp_state_set(struct dsa_switch
*ds
, int port
, u8 state
)
1245 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
1249 case BR_STATE_DISABLED
:
1250 stp_state
= QCA8K_PORT_LOOKUP_STATE_DISABLED
;
1252 case BR_STATE_BLOCKING
:
1253 stp_state
= QCA8K_PORT_LOOKUP_STATE_BLOCKING
;
1255 case BR_STATE_LISTENING
:
1256 stp_state
= QCA8K_PORT_LOOKUP_STATE_LISTENING
;
1258 case BR_STATE_LEARNING
:
1259 stp_state
= QCA8K_PORT_LOOKUP_STATE_LEARNING
;
1261 case BR_STATE_FORWARDING
:
1263 stp_state
= QCA8K_PORT_LOOKUP_STATE_FORWARD
;
1267 qca8k_rmw(priv
, QCA8K_PORT_LOOKUP_CTRL(port
),
1268 QCA8K_PORT_LOOKUP_STATE_MASK
, stp_state
);
1272 qca8k_port_bridge_join(struct dsa_switch
*ds
, int port
, struct net_device
*br
)
1274 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
1275 int port_mask
, cpu_port
;
1278 cpu_port
= dsa_to_port(ds
, port
)->cpu_dp
->index
;
1279 port_mask
= BIT(cpu_port
);
1281 for (i
= 0; i
< QCA8K_NUM_PORTS
; i
++) {
1282 if (dsa_is_cpu_port(ds
, i
))
1284 if (dsa_to_port(ds
, i
)->bridge_dev
!= br
)
1286 /* Add this port to the portvlan mask of the other ports
1289 ret
= qca8k_reg_set(priv
,
1290 QCA8K_PORT_LOOKUP_CTRL(i
),
1295 port_mask
|= BIT(i
);
1298 /* Add all other ports to this ports portvlan mask */
1299 ret
= qca8k_rmw(priv
, QCA8K_PORT_LOOKUP_CTRL(port
),
1300 QCA8K_PORT_LOOKUP_MEMBER
, port_mask
);
1306 qca8k_port_bridge_leave(struct dsa_switch
*ds
, int port
, struct net_device
*br
)
1308 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
1311 cpu_port
= dsa_to_port(ds
, port
)->cpu_dp
->index
;
1313 for (i
= 0; i
< QCA8K_NUM_PORTS
; i
++) {
1314 if (dsa_is_cpu_port(ds
, i
))
1316 if (dsa_to_port(ds
, i
)->bridge_dev
!= br
)
1318 /* Remove this port to the portvlan mask of the other ports
1321 qca8k_reg_clear(priv
,
1322 QCA8K_PORT_LOOKUP_CTRL(i
),
1326 /* Set the cpu port to be the only one in the portvlan mask of
1329 qca8k_rmw(priv
, QCA8K_PORT_LOOKUP_CTRL(port
),
1330 QCA8K_PORT_LOOKUP_MEMBER
, BIT(cpu_port
));
1334 qca8k_port_enable(struct dsa_switch
*ds
, int port
,
1335 struct phy_device
*phy
)
1337 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
1339 qca8k_port_set_status(priv
, port
, 1);
1340 priv
->port_sts
[port
].enabled
= 1;
1342 if (dsa_is_user_port(ds
, port
))
1343 phy_support_asym_pause(phy
);
1349 qca8k_port_disable(struct dsa_switch
*ds
, int port
)
1351 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
1353 qca8k_port_set_status(priv
, port
, 0);
1354 priv
->port_sts
[port
].enabled
= 0;
1358 qca8k_port_change_mtu(struct dsa_switch
*ds
, int port
, int new_mtu
)
1360 struct qca8k_priv
*priv
= ds
->priv
;
1363 priv
->port_mtu
[port
] = new_mtu
;
1365 for (i
= 0; i
< QCA8K_NUM_PORTS
; i
++)
1366 if (priv
->port_mtu
[i
] > mtu
)
1367 mtu
= priv
->port_mtu
[i
];
1369 /* Include L2 header / FCS length */
1370 return qca8k_write(priv
, QCA8K_MAX_FRAME_SIZE
, mtu
+ ETH_HLEN
+ ETH_FCS_LEN
);
1374 qca8k_port_max_mtu(struct dsa_switch
*ds
, int port
)
1376 return QCA8K_MAX_MTU
;
1380 qca8k_port_fdb_insert(struct qca8k_priv
*priv
, const u8
*addr
,
1381 u16 port_mask
, u16 vid
)
1383 /* Set the vid to the port vlan id if no vid is set */
1385 vid
= QCA8K_PORT_VID_DEF
;
1387 return qca8k_fdb_add(priv
, addr
, port_mask
, vid
,
1388 QCA8K_ATU_STATUS_STATIC
);
1392 qca8k_port_fdb_add(struct dsa_switch
*ds
, int port
,
1393 const unsigned char *addr
, u16 vid
)
1395 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
1396 u16 port_mask
= BIT(port
);
1398 return qca8k_port_fdb_insert(priv
, addr
, port_mask
, vid
);
1402 qca8k_port_fdb_del(struct dsa_switch
*ds
, int port
,
1403 const unsigned char *addr
, u16 vid
)
1405 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
1406 u16 port_mask
= BIT(port
);
1409 vid
= QCA8K_PORT_VID_DEF
;
1411 return qca8k_fdb_del(priv
, addr
, port_mask
, vid
);
1415 qca8k_port_fdb_dump(struct dsa_switch
*ds
, int port
,
1416 dsa_fdb_dump_cb_t
*cb
, void *data
)
1418 struct qca8k_priv
*priv
= (struct qca8k_priv
*)ds
->priv
;
1419 struct qca8k_fdb _fdb
= { 0 };
1420 int cnt
= QCA8K_NUM_FDB_RECORDS
;
1424 mutex_lock(&priv
->reg_mutex
);
1425 while (cnt
-- && !qca8k_fdb_next(priv
, &_fdb
, port
)) {
1428 is_static
= (_fdb
.aging
== QCA8K_ATU_STATUS_STATIC
);
1429 ret
= cb(_fdb
.mac
, _fdb
.vid
, is_static
, data
);
1433 mutex_unlock(&priv
->reg_mutex
);
1439 qca8k_port_vlan_filtering(struct dsa_switch
*ds
, int port
, bool vlan_filtering
,
1440 struct netlink_ext_ack
*extack
)
1442 struct qca8k_priv
*priv
= ds
->priv
;
1444 if (vlan_filtering
) {
1445 qca8k_rmw(priv
, QCA8K_PORT_LOOKUP_CTRL(port
),
1446 QCA8K_PORT_LOOKUP_VLAN_MODE
,
1447 QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE
);
1449 qca8k_rmw(priv
, QCA8K_PORT_LOOKUP_CTRL(port
),
1450 QCA8K_PORT_LOOKUP_VLAN_MODE
,
1451 QCA8K_PORT_LOOKUP_VLAN_MODE_NONE
);
1458 qca8k_port_vlan_add(struct dsa_switch
*ds
, int port
,
1459 const struct switchdev_obj_port_vlan
*vlan
,
1460 struct netlink_ext_ack
*extack
)
1462 bool untagged
= vlan
->flags
& BRIDGE_VLAN_INFO_UNTAGGED
;
1463 bool pvid
= vlan
->flags
& BRIDGE_VLAN_INFO_PVID
;
1464 struct qca8k_priv
*priv
= ds
->priv
;
1467 ret
= qca8k_vlan_add(priv
, port
, vlan
->vid
, untagged
);
1469 dev_err(priv
->dev
, "Failed to add VLAN to port %d (%d)", port
, ret
);
1474 int shift
= 16 * (port
% 2);
1476 qca8k_rmw(priv
, QCA8K_EGRESS_VLAN(port
),
1477 0xfff << shift
, vlan
->vid
<< shift
);
1478 qca8k_write(priv
, QCA8K_REG_PORT_VLAN_CTRL0(port
),
1479 QCA8K_PORT_VLAN_CVID(vlan
->vid
) |
1480 QCA8K_PORT_VLAN_SVID(vlan
->vid
));
1486 qca8k_port_vlan_del(struct dsa_switch
*ds
, int port
,
1487 const struct switchdev_obj_port_vlan
*vlan
)
1489 struct qca8k_priv
*priv
= ds
->priv
;
1492 ret
= qca8k_vlan_del(priv
, port
, vlan
->vid
);
1494 dev_err(priv
->dev
, "Failed to delete VLAN from port %d (%d)", port
, ret
);
1499 static enum dsa_tag_protocol
1500 qca8k_get_tag_protocol(struct dsa_switch
*ds
, int port
,
1501 enum dsa_tag_protocol mp
)
1503 return DSA_TAG_PROTO_IPQ4019
;
1506 static const struct dsa_switch_ops qca8k_switch_ops
= {
1507 .get_tag_protocol
= qca8k_get_tag_protocol
,
1508 .setup
= qca8k_setup
,
1509 .get_strings
= qca8k_get_strings
,
1510 .get_ethtool_stats
= qca8k_get_ethtool_stats
,
1511 .get_sset_count
= qca8k_get_sset_count
,
1512 .get_mac_eee
= qca8k_get_mac_eee
,
1513 .set_mac_eee
= qca8k_set_mac_eee
,
1514 .port_enable
= qca8k_port_enable
,
1515 .port_disable
= qca8k_port_disable
,
1516 .port_change_mtu
= qca8k_port_change_mtu
,
1517 .port_max_mtu
= qca8k_port_max_mtu
,
1518 .port_stp_state_set
= qca8k_port_stp_state_set
,
1519 .port_bridge_join
= qca8k_port_bridge_join
,
1520 .port_bridge_leave
= qca8k_port_bridge_leave
,
1521 .port_fdb_add
= qca8k_port_fdb_add
,
1522 .port_fdb_del
= qca8k_port_fdb_del
,
1523 .port_fdb_dump
= qca8k_port_fdb_dump
,
1524 .port_vlan_filtering
= qca8k_port_vlan_filtering
,
1525 .port_vlan_add
= qca8k_port_vlan_add
,
1526 .port_vlan_del
= qca8k_port_vlan_del
,
1527 .phylink_validate
= qca8k_phylink_validate
,
1528 .phylink_mac_link_state
= qca8k_phylink_mac_link_state
,
1529 .phylink_mac_config
= qca8k_phylink_mac_config
,
1530 .phylink_mac_link_down
= qca8k_phylink_mac_link_down
,
1531 .phylink_mac_link_up
= qca8k_phylink_mac_link_up
,
1535 qca8k_ipq4019_probe(struct platform_device
*pdev
)
1537 struct qca8k_priv
*priv
;
1538 void __iomem
*base
, *psgmii
;
1539 struct device_node
*np
= pdev
->dev
.of_node
, *mdio_np
, *psgmii_ethphy_np
;
1542 priv
= devm_kzalloc(&pdev
->dev
, sizeof(*priv
), GFP_KERNEL
);
1546 priv
->dev
= &pdev
->dev
;
1548 base
= devm_platform_ioremap_resource_byname(pdev
, "base");
1550 return PTR_ERR(base
);
1552 priv
->regmap
= devm_regmap_init_mmio(priv
->dev
, base
,
1553 &qca8k_ipq4019_regmap_config
);
1554 if (IS_ERR(priv
->regmap
)) {
1555 ret
= PTR_ERR(priv
->regmap
);
1556 dev_err(priv
->dev
, "base regmap initialization failed, %d\n", ret
);
1560 psgmii
= devm_platform_ioremap_resource_byname(pdev
, "psgmii_phy");
1562 return PTR_ERR(psgmii
);
1564 priv
->psgmii
= devm_regmap_init_mmio(priv
->dev
, psgmii
,
1565 &qca8k_ipq4019_psgmii_phy_regmap_config
);
1566 if (IS_ERR(priv
->psgmii
)) {
1567 ret
= PTR_ERR(priv
->psgmii
);
1568 dev_err(priv
->dev
, "PSGMII regmap initialization failed, %d\n", ret
);
1572 mdio_np
= of_parse_phandle(np
, "mdio", 0);
1574 dev_err(&pdev
->dev
, "unable to get MDIO bus phandle\n");
1575 of_node_put(mdio_np
);
1579 priv
->bus
= of_mdio_find_bus(mdio_np
);
1580 of_node_put(mdio_np
);
1582 dev_err(&pdev
->dev
, "unable to find MDIO bus\n");
1583 return -EPROBE_DEFER
;
1586 psgmii_ethphy_np
= of_parse_phandle(np
, "psgmii-ethphy", 0);
1587 if (!psgmii_ethphy_np
) {
1588 dev_dbg(&pdev
->dev
, "unable to get PSGMII eth PHY phandle\n");
1589 of_node_put(psgmii_ethphy_np
);
1592 if (psgmii_ethphy_np
) {
1593 priv
->psgmii_ethphy
= of_phy_find_device(psgmii_ethphy_np
);
1594 of_node_put(psgmii_ethphy_np
);
1595 if (!priv
->psgmii_ethphy
) {
1596 dev_err(&pdev
->dev
, "unable to get PSGMII eth PHY\n");
1601 priv
->ds
= devm_kzalloc(priv
->dev
, sizeof(*priv
->ds
), GFP_KERNEL
);
1605 priv
->ds
->dev
= priv
->dev
;
1606 priv
->ds
->num_ports
= QCA8K_NUM_PORTS
;
1607 priv
->ds
->priv
= priv
;
1608 priv
->ops
= qca8k_switch_ops
;
1609 priv
->ds
->ops
= &priv
->ops
;
1611 mutex_init(&priv
->reg_mutex
);
1612 platform_set_drvdata(pdev
, priv
);
1614 return dsa_register_switch(priv
->ds
);
1618 qca8k_ipq4019_remove(struct platform_device
*pdev
)
1620 struct qca8k_priv
*priv
= dev_get_drvdata(&pdev
->dev
);
1626 for (i
= 0; i
< QCA8K_NUM_PORTS
; i
++)
1627 qca8k_port_set_status(priv
, i
, 0);
1629 dsa_unregister_switch(priv
->ds
);
1631 dev_set_drvdata(&pdev
->dev
, NULL
);
1636 static const struct of_device_id qca8k_ipq4019_of_match
[] = {
1637 { .compatible
= "qca,ipq4019-qca8337n" },
1641 static struct platform_driver qca8k_ipq4019_driver
= {
1642 .probe
= qca8k_ipq4019_probe
,
1643 .remove
= qca8k_ipq4019_remove
,
1645 .name
= "qca8k-ipq4019",
1646 .of_match_table
= qca8k_ipq4019_of_match
,
1650 module_platform_driver(qca8k_ipq4019_driver
);
1652 MODULE_AUTHOR("Mathieu Olivari, John Crispin <john@phrozen.org>");
1653 MODULE_AUTHOR("Gabor Juhos <j4g8y7@gmail.com>, Robert Marko <robert.marko@sartura.hr>");
1654 MODULE_DESCRIPTION("Qualcomm IPQ4019 built-in switch driver");
1655 MODULE_LICENSE("GPL v2");