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ipq40xx: import qca8k from generic
[openwrt/staging/jow.git] / target / linux / ipq40xx / files / drivers / net / dsa / qca / qca8k-ipq4019.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
4 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (c) 2015, 2019, The Linux Foundation. All rights reserved.
6 * Copyright (c) 2016 John Crispin <john@phrozen.org>
7 */
8
9 #include <linux/module.h>
10 #include <linux/phy.h>
11 #include <linux/netdevice.h>
12 #include <net/dsa.h>
13 #include <linux/of_net.h>
14 #include <linux/of_mdio.h>
15 #include <linux/of_platform.h>
16 #include <linux/if_bridge.h>
17 #include <linux/mdio.h>
18 #include <linux/phylink.h>
19 #include <linux/gpio/consumer.h>
20 #include <linux/etherdevice.h>
21
22 #include "qca8k.h"
23
24 #define MIB_DESC(_s, _o, _n) \
25 { \
26 .size = (_s), \
27 .offset = (_o), \
28 .name = (_n), \
29 }
30
31 static const struct qca8k_mib_desc ar8327_mib[] = {
32 MIB_DESC(1, 0x00, "RxBroad"),
33 MIB_DESC(1, 0x04, "RxPause"),
34 MIB_DESC(1, 0x08, "RxMulti"),
35 MIB_DESC(1, 0x0c, "RxFcsErr"),
36 MIB_DESC(1, 0x10, "RxAlignErr"),
37 MIB_DESC(1, 0x14, "RxRunt"),
38 MIB_DESC(1, 0x18, "RxFragment"),
39 MIB_DESC(1, 0x1c, "Rx64Byte"),
40 MIB_DESC(1, 0x20, "Rx128Byte"),
41 MIB_DESC(1, 0x24, "Rx256Byte"),
42 MIB_DESC(1, 0x28, "Rx512Byte"),
43 MIB_DESC(1, 0x2c, "Rx1024Byte"),
44 MIB_DESC(1, 0x30, "Rx1518Byte"),
45 MIB_DESC(1, 0x34, "RxMaxByte"),
46 MIB_DESC(1, 0x38, "RxTooLong"),
47 MIB_DESC(2, 0x3c, "RxGoodByte"),
48 MIB_DESC(2, 0x44, "RxBadByte"),
49 MIB_DESC(1, 0x4c, "RxOverFlow"),
50 MIB_DESC(1, 0x50, "Filtered"),
51 MIB_DESC(1, 0x54, "TxBroad"),
52 MIB_DESC(1, 0x58, "TxPause"),
53 MIB_DESC(1, 0x5c, "TxMulti"),
54 MIB_DESC(1, 0x60, "TxUnderRun"),
55 MIB_DESC(1, 0x64, "Tx64Byte"),
56 MIB_DESC(1, 0x68, "Tx128Byte"),
57 MIB_DESC(1, 0x6c, "Tx256Byte"),
58 MIB_DESC(1, 0x70, "Tx512Byte"),
59 MIB_DESC(1, 0x74, "Tx1024Byte"),
60 MIB_DESC(1, 0x78, "Tx1518Byte"),
61 MIB_DESC(1, 0x7c, "TxMaxByte"),
62 MIB_DESC(1, 0x80, "TxOverSize"),
63 MIB_DESC(2, 0x84, "TxByte"),
64 MIB_DESC(1, 0x8c, "TxCollision"),
65 MIB_DESC(1, 0x90, "TxAbortCol"),
66 MIB_DESC(1, 0x94, "TxMultiCol"),
67 MIB_DESC(1, 0x98, "TxSingleCol"),
68 MIB_DESC(1, 0x9c, "TxExcDefer"),
69 MIB_DESC(1, 0xa0, "TxDefer"),
70 MIB_DESC(1, 0xa4, "TxLateCol"),
71 };
72
73 /* The 32bit switch registers are accessed indirectly. To achieve this we need
74 * to set the page of the register. Track the last page that was set to reduce
75 * mdio writes
76 */
77 static u16 qca8k_current_page = 0xffff;
78
79 static void
80 qca8k_split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
81 {
82 regaddr >>= 1;
83 *r1 = regaddr & 0x1e;
84
85 regaddr >>= 5;
86 *r2 = regaddr & 0x7;
87
88 regaddr >>= 3;
89 *page = regaddr & 0x3ff;
90 }
91
92 static int
93 qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
94 {
95 int ret;
96
97 ret = bus->read(bus, phy_id, regnum);
98 if (ret >= 0) {
99 *val = ret;
100 ret = bus->read(bus, phy_id, regnum + 1);
101 *val |= ret << 16;
102 }
103
104 if (ret < 0) {
105 dev_err_ratelimited(&bus->dev,
106 "failed to read qca8k 32bit register\n");
107 *val = 0;
108 return ret;
109 }
110
111 return 0;
112 }
113
114 static void
115 qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
116 {
117 u16 lo, hi;
118 int ret;
119
120 lo = val & 0xffff;
121 hi = (u16)(val >> 16);
122
123 ret = bus->write(bus, phy_id, regnum, lo);
124 if (ret >= 0)
125 ret = bus->write(bus, phy_id, regnum + 1, hi);
126 if (ret < 0)
127 dev_err_ratelimited(&bus->dev,
128 "failed to write qca8k 32bit register\n");
129 }
130
131 static int
132 qca8k_set_page(struct mii_bus *bus, u16 page)
133 {
134 int ret;
135
136 if (page == qca8k_current_page)
137 return 0;
138
139 ret = bus->write(bus, 0x18, 0, page);
140 if (ret < 0) {
141 dev_err_ratelimited(&bus->dev,
142 "failed to set qca8k page\n");
143 return ret;
144 }
145
146 qca8k_current_page = page;
147 usleep_range(1000, 2000);
148 return 0;
149 }
150
151 static int
152 qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val)
153 {
154 struct mii_bus *bus = priv->bus;
155 u16 r1, r2, page;
156 int ret;
157
158 qca8k_split_addr(reg, &r1, &r2, &page);
159
160 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
161
162 ret = qca8k_set_page(bus, page);
163 if (ret < 0)
164 goto exit;
165
166 ret = qca8k_mii_read32(bus, 0x10 | r2, r1, val);
167
168 exit:
169 mutex_unlock(&bus->mdio_lock);
170 return ret;
171 }
172
173 static int
174 qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)
175 {
176 struct mii_bus *bus = priv->bus;
177 u16 r1, r2, page;
178 int ret;
179
180 qca8k_split_addr(reg, &r1, &r2, &page);
181
182 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
183
184 ret = qca8k_set_page(bus, page);
185 if (ret < 0)
186 goto exit;
187
188 qca8k_mii_write32(bus, 0x10 | r2, r1, val);
189
190 exit:
191 mutex_unlock(&bus->mdio_lock);
192 return ret;
193 }
194
195 static int
196 qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)
197 {
198 struct mii_bus *bus = priv->bus;
199 u16 r1, r2, page;
200 u32 val;
201 int ret;
202
203 qca8k_split_addr(reg, &r1, &r2, &page);
204
205 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
206
207 ret = qca8k_set_page(bus, page);
208 if (ret < 0)
209 goto exit;
210
211 ret = qca8k_mii_read32(bus, 0x10 | r2, r1, &val);
212 if (ret < 0)
213 goto exit;
214
215 val &= ~mask;
216 val |= write_val;
217 qca8k_mii_write32(bus, 0x10 | r2, r1, val);
218
219 exit:
220 mutex_unlock(&bus->mdio_lock);
221
222 return ret;
223 }
224
225 static int
226 qca8k_reg_set(struct qca8k_priv *priv, u32 reg, u32 val)
227 {
228 return qca8k_rmw(priv, reg, 0, val);
229 }
230
231 static int
232 qca8k_reg_clear(struct qca8k_priv *priv, u32 reg, u32 val)
233 {
234 return qca8k_rmw(priv, reg, val, 0);
235 }
236
237 static int
238 qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val)
239 {
240 struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
241
242 return qca8k_read(priv, reg, val);
243 }
244
245 static int
246 qca8k_regmap_write(void *ctx, uint32_t reg, uint32_t val)
247 {
248 struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
249
250 return qca8k_write(priv, reg, val);
251 }
252
253 static const struct regmap_range qca8k_readable_ranges[] = {
254 regmap_reg_range(0x0000, 0x00e4), /* Global control */
255 regmap_reg_range(0x0100, 0x0168), /* EEE control */
256 regmap_reg_range(0x0200, 0x0270), /* Parser control */
257 regmap_reg_range(0x0400, 0x0454), /* ACL */
258 regmap_reg_range(0x0600, 0x0718), /* Lookup */
259 regmap_reg_range(0x0800, 0x0b70), /* QM */
260 regmap_reg_range(0x0c00, 0x0c80), /* PKT */
261 regmap_reg_range(0x0e00, 0x0e98), /* L3 */
262 regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */
263 regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */
264 regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */
265 regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */
266 regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */
267 regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */
268 regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */
269
270 };
271
272 static const struct regmap_access_table qca8k_readable_table = {
273 .yes_ranges = qca8k_readable_ranges,
274 .n_yes_ranges = ARRAY_SIZE(qca8k_readable_ranges),
275 };
276
277 static struct regmap_config qca8k_regmap_config = {
278 .reg_bits = 16,
279 .val_bits = 32,
280 .reg_stride = 4,
281 .max_register = 0x16ac, /* end MIB - Port6 range */
282 .reg_read = qca8k_regmap_read,
283 .reg_write = qca8k_regmap_write,
284 .rd_table = &qca8k_readable_table,
285 };
286
287 static int
288 qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask)
289 {
290 int ret, ret1;
291 u32 val;
292
293 ret = read_poll_timeout(qca8k_read, ret1, !(val & mask),
294 0, QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false,
295 priv, reg, &val);
296
297 /* Check if qca8k_read has failed for a different reason
298 * before returning -ETIMEDOUT
299 */
300 if (ret < 0 && ret1 < 0)
301 return ret1;
302
303 return ret;
304 }
305
306 static int
307 qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb)
308 {
309 u32 reg[4], val;
310 int i, ret;
311
312 /* load the ARL table into an array */
313 for (i = 0; i < 4; i++) {
314 ret = qca8k_read(priv, QCA8K_REG_ATU_DATA0 + (i * 4), &val);
315 if (ret < 0)
316 return ret;
317
318 reg[i] = val;
319 }
320
321 /* vid - 83:72 */
322 fdb->vid = (reg[2] >> QCA8K_ATU_VID_S) & QCA8K_ATU_VID_M;
323 /* aging - 67:64 */
324 fdb->aging = reg[2] & QCA8K_ATU_STATUS_M;
325 /* portmask - 54:48 */
326 fdb->port_mask = (reg[1] >> QCA8K_ATU_PORT_S) & QCA8K_ATU_PORT_M;
327 /* mac - 47:0 */
328 fdb->mac[0] = (reg[1] >> QCA8K_ATU_ADDR0_S) & 0xff;
329 fdb->mac[1] = reg[1] & 0xff;
330 fdb->mac[2] = (reg[0] >> QCA8K_ATU_ADDR2_S) & 0xff;
331 fdb->mac[3] = (reg[0] >> QCA8K_ATU_ADDR3_S) & 0xff;
332 fdb->mac[4] = (reg[0] >> QCA8K_ATU_ADDR4_S) & 0xff;
333 fdb->mac[5] = reg[0] & 0xff;
334
335 return 0;
336 }
337
338 static void
339 qca8k_fdb_write(struct qca8k_priv *priv, u16 vid, u8 port_mask, const u8 *mac,
340 u8 aging)
341 {
342 u32 reg[3] = { 0 };
343 int i;
344
345 /* vid - 83:72 */
346 reg[2] = (vid & QCA8K_ATU_VID_M) << QCA8K_ATU_VID_S;
347 /* aging - 67:64 */
348 reg[2] |= aging & QCA8K_ATU_STATUS_M;
349 /* portmask - 54:48 */
350 reg[1] = (port_mask & QCA8K_ATU_PORT_M) << QCA8K_ATU_PORT_S;
351 /* mac - 47:0 */
352 reg[1] |= mac[0] << QCA8K_ATU_ADDR0_S;
353 reg[1] |= mac[1];
354 reg[0] |= mac[2] << QCA8K_ATU_ADDR2_S;
355 reg[0] |= mac[3] << QCA8K_ATU_ADDR3_S;
356 reg[0] |= mac[4] << QCA8K_ATU_ADDR4_S;
357 reg[0] |= mac[5];
358
359 /* load the array into the ARL table */
360 for (i = 0; i < 3; i++)
361 qca8k_write(priv, QCA8K_REG_ATU_DATA0 + (i * 4), reg[i]);
362 }
363
364 static int
365 qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd, int port)
366 {
367 u32 reg;
368 int ret;
369
370 /* Set the command and FDB index */
371 reg = QCA8K_ATU_FUNC_BUSY;
372 reg |= cmd;
373 if (port >= 0) {
374 reg |= QCA8K_ATU_FUNC_PORT_EN;
375 reg |= (port & QCA8K_ATU_FUNC_PORT_M) << QCA8K_ATU_FUNC_PORT_S;
376 }
377
378 /* Write the function register triggering the table access */
379 ret = qca8k_write(priv, QCA8K_REG_ATU_FUNC, reg);
380 if (ret)
381 return ret;
382
383 /* wait for completion */
384 ret = qca8k_busy_wait(priv, QCA8K_REG_ATU_FUNC, QCA8K_ATU_FUNC_BUSY);
385 if (ret)
386 return ret;
387
388 /* Check for table full violation when adding an entry */
389 if (cmd == QCA8K_FDB_LOAD) {
390 ret = qca8k_read(priv, QCA8K_REG_ATU_FUNC, &reg);
391 if (ret < 0)
392 return ret;
393 if (reg & QCA8K_ATU_FUNC_FULL)
394 return -1;
395 }
396
397 return 0;
398 }
399
400 static int
401 qca8k_fdb_next(struct qca8k_priv *priv, struct qca8k_fdb *fdb, int port)
402 {
403 int ret;
404
405 qca8k_fdb_write(priv, fdb->vid, fdb->port_mask, fdb->mac, fdb->aging);
406 ret = qca8k_fdb_access(priv, QCA8K_FDB_NEXT, port);
407 if (ret < 0)
408 return ret;
409
410 return qca8k_fdb_read(priv, fdb);
411 }
412
413 static int
414 qca8k_fdb_add(struct qca8k_priv *priv, const u8 *mac, u16 port_mask,
415 u16 vid, u8 aging)
416 {
417 int ret;
418
419 mutex_lock(&priv->reg_mutex);
420 qca8k_fdb_write(priv, vid, port_mask, mac, aging);
421 ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1);
422 mutex_unlock(&priv->reg_mutex);
423
424 return ret;
425 }
426
427 static int
428 qca8k_fdb_del(struct qca8k_priv *priv, const u8 *mac, u16 port_mask, u16 vid)
429 {
430 int ret;
431
432 mutex_lock(&priv->reg_mutex);
433 qca8k_fdb_write(priv, vid, port_mask, mac, 0);
434 ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1);
435 mutex_unlock(&priv->reg_mutex);
436
437 return ret;
438 }
439
440 static void
441 qca8k_fdb_flush(struct qca8k_priv *priv)
442 {
443 mutex_lock(&priv->reg_mutex);
444 qca8k_fdb_access(priv, QCA8K_FDB_FLUSH, -1);
445 mutex_unlock(&priv->reg_mutex);
446 }
447
448 static int
449 qca8k_vlan_access(struct qca8k_priv *priv, enum qca8k_vlan_cmd cmd, u16 vid)
450 {
451 u32 reg;
452 int ret;
453
454 /* Set the command and VLAN index */
455 reg = QCA8K_VTU_FUNC1_BUSY;
456 reg |= cmd;
457 reg |= vid << QCA8K_VTU_FUNC1_VID_S;
458
459 /* Write the function register triggering the table access */
460 ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC1, reg);
461 if (ret)
462 return ret;
463
464 /* wait for completion */
465 ret = qca8k_busy_wait(priv, QCA8K_REG_VTU_FUNC1, QCA8K_VTU_FUNC1_BUSY);
466 if (ret)
467 return ret;
468
469 /* Check for table full violation when adding an entry */
470 if (cmd == QCA8K_VLAN_LOAD) {
471 ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC1, &reg);
472 if (ret < 0)
473 return ret;
474 if (reg & QCA8K_VTU_FUNC1_FULL)
475 return -ENOMEM;
476 }
477
478 return 0;
479 }
480
481 static int
482 qca8k_vlan_add(struct qca8k_priv *priv, u8 port, u16 vid, bool untagged)
483 {
484 u32 reg;
485 int ret;
486
487 /*
488 We do the right thing with VLAN 0 and treat it as untagged while
489 preserving the tag on egress.
490 */
491 if (vid == 0)
492 return 0;
493
494 mutex_lock(&priv->reg_mutex);
495 ret = qca8k_vlan_access(priv, QCA8K_VLAN_READ, vid);
496 if (ret < 0)
497 goto out;
498
499 ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, &reg);
500 if (ret < 0)
501 goto out;
502 reg |= QCA8K_VTU_FUNC0_VALID | QCA8K_VTU_FUNC0_IVL_EN;
503 reg &= ~(QCA8K_VTU_FUNC0_EG_MODE_MASK << QCA8K_VTU_FUNC0_EG_MODE_S(port));
504 if (untagged)
505 reg |= QCA8K_VTU_FUNC0_EG_MODE_UNTAG <<
506 QCA8K_VTU_FUNC0_EG_MODE_S(port);
507 else
508 reg |= QCA8K_VTU_FUNC0_EG_MODE_TAG <<
509 QCA8K_VTU_FUNC0_EG_MODE_S(port);
510
511 ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);
512 if (ret)
513 goto out;
514 ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid);
515
516 out:
517 mutex_unlock(&priv->reg_mutex);
518
519 return ret;
520 }
521
522 static int
523 qca8k_vlan_del(struct qca8k_priv *priv, u8 port, u16 vid)
524 {
525 u32 reg, mask;
526 int ret, i;
527 bool del;
528
529 mutex_lock(&priv->reg_mutex);
530 ret = qca8k_vlan_access(priv, QCA8K_VLAN_READ, vid);
531 if (ret < 0)
532 goto out;
533
534 ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, &reg);
535 if (ret < 0)
536 goto out;
537 reg &= ~(3 << QCA8K_VTU_FUNC0_EG_MODE_S(port));
538 reg |= QCA8K_VTU_FUNC0_EG_MODE_NOT <<
539 QCA8K_VTU_FUNC0_EG_MODE_S(port);
540
541 /* Check if we're the last member to be removed */
542 del = true;
543 for (i = 0; i < QCA8K_NUM_PORTS; i++) {
544 mask = QCA8K_VTU_FUNC0_EG_MODE_NOT;
545 mask <<= QCA8K_VTU_FUNC0_EG_MODE_S(i);
546
547 if ((reg & mask) != mask) {
548 del = false;
549 break;
550 }
551 }
552
553 if (del) {
554 ret = qca8k_vlan_access(priv, QCA8K_VLAN_PURGE, vid);
555 } else {
556 ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);
557 if (ret)
558 goto out;
559 ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid);
560 }
561
562 out:
563 mutex_unlock(&priv->reg_mutex);
564
565 return ret;
566 }
567
568 static int
569 qca8k_mib_init(struct qca8k_priv *priv)
570 {
571 int ret;
572
573 mutex_lock(&priv->reg_mutex);
574 ret = qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY);
575 if (ret)
576 goto exit;
577
578 ret = qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY);
579 if (ret)
580 goto exit;
581
582 ret = qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP);
583 if (ret)
584 goto exit;
585
586 ret = qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB);
587
588 exit:
589 mutex_unlock(&priv->reg_mutex);
590 return ret;
591 }
592
593 static void
594 qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable)
595 {
596 u32 mask = QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
597
598 /* Port 0 and 6 have no internal PHY */
599 if (port > 0 && port < 6)
600 mask |= QCA8K_PORT_STATUS_LINK_AUTO;
601
602 if (enable)
603 qca8k_reg_set(priv, QCA8K_REG_PORT_STATUS(port), mask);
604 else
605 qca8k_reg_clear(priv, QCA8K_REG_PORT_STATUS(port), mask);
606 }
607
608 static u32
609 qca8k_port_to_phy(int port)
610 {
611 /* From Andrew Lunn:
612 * Port 0 has no internal phy.
613 * Port 1 has an internal PHY at MDIO address 0.
614 * Port 2 has an internal PHY at MDIO address 1.
615 * ...
616 * Port 5 has an internal PHY at MDIO address 4.
617 * Port 6 has no internal PHY.
618 */
619
620 return port - 1;
621 }
622
623 static int
624 qca8k_mdio_busy_wait(struct mii_bus *bus, u32 reg, u32 mask)
625 {
626 u16 r1, r2, page;
627 u32 val;
628 int ret, ret1;
629
630 qca8k_split_addr(reg, &r1, &r2, &page);
631
632 ret = read_poll_timeout(qca8k_mii_read32, ret1, !(val & mask), 0,
633 QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false,
634 bus, 0x10 | r2, r1, &val);
635
636 /* Check if qca8k_read has failed for a different reason
637 * before returnting -ETIMEDOUT
638 */
639 if (ret < 0 && ret1 < 0)
640 return ret1;
641
642 return ret;
643 }
644
645 static int
646 qca8k_mdio_write(struct mii_bus *bus, int phy, int regnum, u16 data)
647 {
648 u16 r1, r2, page;
649 u32 val;
650 int ret;
651
652 if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
653 return -EINVAL;
654
655 val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN |
656 QCA8K_MDIO_MASTER_WRITE | QCA8K_MDIO_MASTER_PHY_ADDR(phy) |
657 QCA8K_MDIO_MASTER_REG_ADDR(regnum) |
658 QCA8K_MDIO_MASTER_DATA(data);
659
660 qca8k_split_addr(QCA8K_MDIO_MASTER_CTRL, &r1, &r2, &page);
661
662 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
663
664 ret = qca8k_set_page(bus, page);
665 if (ret)
666 goto exit;
667
668 qca8k_mii_write32(bus, 0x10 | r2, r1, val);
669
670 ret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL,
671 QCA8K_MDIO_MASTER_BUSY);
672
673 exit:
674 /* even if the busy_wait timeouts try to clear the MASTER_EN */
675 qca8k_mii_write32(bus, 0x10 | r2, r1, 0);
676
677 mutex_unlock(&bus->mdio_lock);
678
679 return ret;
680 }
681
682 static int
683 qca8k_mdio_read(struct mii_bus *bus, int phy, int regnum)
684 {
685 u16 r1, r2, page;
686 u32 val;
687 int ret;
688
689 if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
690 return -EINVAL;
691
692 val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN |
693 QCA8K_MDIO_MASTER_READ | QCA8K_MDIO_MASTER_PHY_ADDR(phy) |
694 QCA8K_MDIO_MASTER_REG_ADDR(regnum);
695
696 qca8k_split_addr(QCA8K_MDIO_MASTER_CTRL, &r1, &r2, &page);
697
698 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
699
700 ret = qca8k_set_page(bus, page);
701 if (ret)
702 goto exit;
703
704 qca8k_mii_write32(bus, 0x10 | r2, r1, val);
705
706 ret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL,
707 QCA8K_MDIO_MASTER_BUSY);
708 if (ret)
709 goto exit;
710
711 ret = qca8k_mii_read32(bus, 0x10 | r2, r1, &val);
712
713 exit:
714 /* even if the busy_wait timeouts try to clear the MASTER_EN */
715 qca8k_mii_write32(bus, 0x10 | r2, r1, 0);
716
717 mutex_unlock(&bus->mdio_lock);
718
719 if (ret >= 0)
720 ret = val & QCA8K_MDIO_MASTER_DATA_MASK;
721
722 return ret;
723 }
724
725 static int
726 qca8k_internal_mdio_write(struct mii_bus *slave_bus, int phy, int regnum, u16 data)
727 {
728 struct qca8k_priv *priv = slave_bus->priv;
729 struct mii_bus *bus = priv->bus;
730
731 return qca8k_mdio_write(bus, phy, regnum, data);
732 }
733
734 static int
735 qca8k_internal_mdio_read(struct mii_bus *slave_bus, int phy, int regnum)
736 {
737 struct qca8k_priv *priv = slave_bus->priv;
738 struct mii_bus *bus = priv->bus;
739
740 return qca8k_mdio_read(bus, phy, regnum);
741 }
742
743 static int
744 qca8k_phy_write(struct dsa_switch *ds, int port, int regnum, u16 data)
745 {
746 struct qca8k_priv *priv = ds->priv;
747
748 /* Check if the legacy mapping should be used and the
749 * port is not correctly mapped to the right PHY in the
750 * devicetree
751 */
752 if (priv->legacy_phy_port_mapping)
753 port = qca8k_port_to_phy(port) % PHY_MAX_ADDR;
754
755 return qca8k_mdio_write(priv->bus, port, regnum, data);
756 }
757
758 static int
759 qca8k_phy_read(struct dsa_switch *ds, int port, int regnum)
760 {
761 struct qca8k_priv *priv = ds->priv;
762 int ret;
763
764 /* Check if the legacy mapping should be used and the
765 * port is not correctly mapped to the right PHY in the
766 * devicetree
767 */
768 if (priv->legacy_phy_port_mapping)
769 port = qca8k_port_to_phy(port) % PHY_MAX_ADDR;
770
771 ret = qca8k_mdio_read(priv->bus, port, regnum);
772
773 if (ret < 0)
774 return 0xffff;
775
776 return ret;
777 }
778
779 static int
780 qca8k_mdio_register(struct qca8k_priv *priv, struct device_node *mdio)
781 {
782 struct dsa_switch *ds = priv->ds;
783 struct mii_bus *bus;
784
785 bus = devm_mdiobus_alloc(ds->dev);
786
787 if (!bus)
788 return -ENOMEM;
789
790 bus->priv = (void *)priv;
791 bus->name = "qca8k slave mii";
792 bus->read = qca8k_internal_mdio_read;
793 bus->write = qca8k_internal_mdio_write;
794 snprintf(bus->id, MII_BUS_ID_SIZE, "qca8k-%d",
795 ds->index);
796
797 bus->parent = ds->dev;
798 bus->phy_mask = ~ds->phys_mii_mask;
799
800 ds->slave_mii_bus = bus;
801
802 return devm_of_mdiobus_register(priv->dev, bus, mdio);
803 }
804
805 static int
806 qca8k_setup_mdio_bus(struct qca8k_priv *priv)
807 {
808 u32 internal_mdio_mask = 0, external_mdio_mask = 0, reg;
809 struct device_node *ports, *port, *mdio;
810 phy_interface_t mode;
811 int err;
812
813 ports = of_get_child_by_name(priv->dev->of_node, "ports");
814 if (!ports)
815 ports = of_get_child_by_name(priv->dev->of_node, "ethernet-ports");
816
817 if (!ports)
818 return -EINVAL;
819
820 for_each_available_child_of_node(ports, port) {
821 err = of_property_read_u32(port, "reg", &reg);
822 if (err) {
823 of_node_put(port);
824 of_node_put(ports);
825 return err;
826 }
827
828 if (!dsa_is_user_port(priv->ds, reg))
829 continue;
830
831 of_get_phy_mode(port, &mode);
832
833 if (of_property_read_bool(port, "phy-handle") &&
834 mode != PHY_INTERFACE_MODE_INTERNAL)
835 external_mdio_mask |= BIT(reg);
836 else
837 internal_mdio_mask |= BIT(reg);
838 }
839
840 of_node_put(ports);
841 if (!external_mdio_mask && !internal_mdio_mask) {
842 dev_err(priv->dev, "no PHYs are defined.\n");
843 return -EINVAL;
844 }
845
846 /* The QCA8K_MDIO_MASTER_EN Bit, which grants access to PHYs through
847 * the MDIO_MASTER register also _disconnects_ the external MDC
848 * passthrough to the internal PHYs. It's not possible to use both
849 * configurations at the same time!
850 *
851 * Because this came up during the review process:
852 * If the external mdio-bus driver is capable magically disabling
853 * the QCA8K_MDIO_MASTER_EN and mutex/spin-locking out the qca8k's
854 * accessors for the time being, it would be possible to pull this
855 * off.
856 */
857 if (!!external_mdio_mask && !!internal_mdio_mask) {
858 dev_err(priv->dev, "either internal or external mdio bus configuration is supported.\n");
859 return -EINVAL;
860 }
861
862 if (external_mdio_mask) {
863 /* Make sure to disable the internal mdio bus in cases
864 * a dt-overlay and driver reload changed the configuration
865 */
866
867 return qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL,
868 QCA8K_MDIO_MASTER_EN);
869 }
870
871 /* Check if the devicetree declare the port:phy mapping */
872 mdio = of_get_child_by_name(priv->dev->of_node, "mdio");
873 if (of_device_is_available(mdio)) {
874 err = qca8k_mdio_register(priv, mdio);
875 if (err)
876 of_node_put(mdio);
877
878 return err;
879 }
880
881 /* If a mapping can't be found the legacy mapping is used,
882 * using the qca8k_port_to_phy function
883 */
884 priv->legacy_phy_port_mapping = true;
885 priv->ops.phy_read = qca8k_phy_read;
886 priv->ops.phy_write = qca8k_phy_write;
887
888 return 0;
889 }
890
891 static int
892 qca8k_setup_mac_pwr_sel(struct qca8k_priv *priv)
893 {
894 u32 mask = 0;
895 int ret = 0;
896
897 /* SoC specific settings for ipq8064.
898 * If more device require this consider adding
899 * a dedicated binding.
900 */
901 if (of_machine_is_compatible("qcom,ipq8064"))
902 mask |= QCA8K_MAC_PWR_RGMII0_1_8V;
903
904 /* SoC specific settings for ipq8065 */
905 if (of_machine_is_compatible("qcom,ipq8065"))
906 mask |= QCA8K_MAC_PWR_RGMII1_1_8V;
907
908 if (mask) {
909 ret = qca8k_rmw(priv, QCA8K_REG_MAC_PWR_SEL,
910 QCA8K_MAC_PWR_RGMII0_1_8V |
911 QCA8K_MAC_PWR_RGMII1_1_8V,
912 mask);
913 }
914
915 return ret;
916 }
917
918 static int qca8k_find_cpu_port(struct dsa_switch *ds)
919 {
920 struct qca8k_priv *priv = ds->priv;
921
922 /* Find the connected cpu port. Valid port are 0 or 6 */
923 if (dsa_is_cpu_port(ds, 0))
924 return 0;
925
926 dev_dbg(priv->dev, "port 0 is not the CPU port. Checking port 6");
927
928 if (dsa_is_cpu_port(ds, 6))
929 return 6;
930
931 return -EINVAL;
932 }
933
934 static int
935 qca8k_setup_of_pws_reg(struct qca8k_priv *priv)
936 {
937 struct device_node *node = priv->dev->of_node;
938 const struct qca8k_match_data *data;
939 u32 val = 0;
940 int ret;
941
942 /* QCA8327 require to set to the correct mode.
943 * His bigger brother QCA8328 have the 172 pin layout.
944 * Should be applied by default but we set this just to make sure.
945 */
946 if (priv->switch_id == QCA8K_ID_QCA8327) {
947 data = of_device_get_match_data(priv->dev);
948
949 /* Set the correct package of 148 pin for QCA8327 */
950 if (data->reduced_package)
951 val |= QCA8327_PWS_PACKAGE148_EN;
952
953 ret = qca8k_rmw(priv, QCA8K_REG_PWS, QCA8327_PWS_PACKAGE148_EN,
954 val);
955 if (ret)
956 return ret;
957 }
958
959 if (of_property_read_bool(node, "qca,ignore-power-on-sel"))
960 val |= QCA8K_PWS_POWER_ON_SEL;
961
962 if (of_property_read_bool(node, "qca,led-open-drain")) {
963 if (!(val & QCA8K_PWS_POWER_ON_SEL)) {
964 dev_err(priv->dev, "qca,led-open-drain require qca,ignore-power-on-sel to be set.");
965 return -EINVAL;
966 }
967
968 val |= QCA8K_PWS_LED_OPEN_EN_CSR;
969 }
970
971 return qca8k_rmw(priv, QCA8K_REG_PWS,
972 QCA8K_PWS_LED_OPEN_EN_CSR | QCA8K_PWS_POWER_ON_SEL,
973 val);
974 }
975
976 static int
977 qca8k_parse_port_config(struct qca8k_priv *priv)
978 {
979 int port, cpu_port_index = -1, ret;
980 struct device_node *port_dn;
981 phy_interface_t mode;
982 struct dsa_port *dp;
983 u32 delay;
984
985 /* We have 2 CPU port. Check them */
986 for (port = 0; port < QCA8K_NUM_PORTS && cpu_port_index < QCA8K_NUM_CPU_PORTS; port++) {
987 /* Skip every other port */
988 if (port != 0 && port != 6)
989 continue;
990
991 dp = dsa_to_port(priv->ds, port);
992 port_dn = dp->dn;
993 cpu_port_index++;
994
995 if (!of_device_is_available(port_dn))
996 continue;
997
998 ret = of_get_phy_mode(port_dn, &mode);
999 if (ret)
1000 continue;
1001
1002 switch (mode) {
1003 case PHY_INTERFACE_MODE_RGMII:
1004 case PHY_INTERFACE_MODE_RGMII_ID:
1005 case PHY_INTERFACE_MODE_RGMII_TXID:
1006 case PHY_INTERFACE_MODE_RGMII_RXID:
1007 case PHY_INTERFACE_MODE_SGMII:
1008 delay = 0;
1009
1010 if (!of_property_read_u32(port_dn, "tx-internal-delay-ps", &delay))
1011 /* Switch regs accept value in ns, convert ps to ns */
1012 delay = delay / 1000;
1013 else if (mode == PHY_INTERFACE_MODE_RGMII_ID ||
1014 mode == PHY_INTERFACE_MODE_RGMII_TXID)
1015 delay = 1;
1016
1017 if (delay > QCA8K_MAX_DELAY) {
1018 dev_err(priv->dev, "rgmii tx delay is limited to a max value of 3ns, setting to the max value");
1019 delay = 3;
1020 }
1021
1022 priv->ports_config.rgmii_tx_delay[cpu_port_index] = delay;
1023
1024 delay = 0;
1025
1026 if (!of_property_read_u32(port_dn, "rx-internal-delay-ps", &delay))
1027 /* Switch regs accept value in ns, convert ps to ns */
1028 delay = delay / 1000;
1029 else if (mode == PHY_INTERFACE_MODE_RGMII_ID ||
1030 mode == PHY_INTERFACE_MODE_RGMII_RXID)
1031 delay = 2;
1032
1033 if (delay > QCA8K_MAX_DELAY) {
1034 dev_err(priv->dev, "rgmii rx delay is limited to a max value of 3ns, setting to the max value");
1035 delay = 3;
1036 }
1037
1038 priv->ports_config.rgmii_rx_delay[cpu_port_index] = delay;
1039
1040 /* Skip sgmii parsing for rgmii* mode */
1041 if (mode == PHY_INTERFACE_MODE_RGMII ||
1042 mode == PHY_INTERFACE_MODE_RGMII_ID ||
1043 mode == PHY_INTERFACE_MODE_RGMII_TXID ||
1044 mode == PHY_INTERFACE_MODE_RGMII_RXID)
1045 break;
1046
1047 if (of_property_read_bool(port_dn, "qca,sgmii-txclk-falling-edge"))
1048 priv->ports_config.sgmii_tx_clk_falling_edge = true;
1049
1050 if (of_property_read_bool(port_dn, "qca,sgmii-rxclk-falling-edge"))
1051 priv->ports_config.sgmii_rx_clk_falling_edge = true;
1052
1053 if (of_property_read_bool(port_dn, "qca,sgmii-enable-pll")) {
1054 priv->ports_config.sgmii_enable_pll = true;
1055
1056 if (priv->switch_id == QCA8K_ID_QCA8327) {
1057 dev_err(priv->dev, "SGMII PLL should NOT be enabled for qca8327. Aborting enabling");
1058 priv->ports_config.sgmii_enable_pll = false;
1059 }
1060
1061 if (priv->switch_revision < 2)
1062 dev_warn(priv->dev, "SGMII PLL should NOT be enabled for qca8337 with revision 2 or more.");
1063 }
1064
1065 break;
1066 default:
1067 continue;
1068 }
1069 }
1070
1071 return 0;
1072 }
1073
1074 static int
1075 qca8k_setup(struct dsa_switch *ds)
1076 {
1077 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1078 int cpu_port, ret, i;
1079 u32 mask;
1080
1081 cpu_port = qca8k_find_cpu_port(ds);
1082 if (cpu_port < 0) {
1083 dev_err(priv->dev, "No cpu port configured in both cpu port0 and port6");
1084 return cpu_port;
1085 }
1086
1087 /* Parse CPU port config to be later used in phy_link mac_config */
1088 ret = qca8k_parse_port_config(priv);
1089 if (ret)
1090 return ret;
1091
1092 mutex_init(&priv->reg_mutex);
1093
1094 /* Start by setting up the register mapping */
1095 priv->regmap = devm_regmap_init(ds->dev, NULL, priv,
1096 &qca8k_regmap_config);
1097 if (IS_ERR(priv->regmap))
1098 dev_warn(priv->dev, "regmap initialization failed");
1099
1100 ret = qca8k_setup_mdio_bus(priv);
1101 if (ret)
1102 return ret;
1103
1104 ret = qca8k_setup_of_pws_reg(priv);
1105 if (ret)
1106 return ret;
1107
1108 ret = qca8k_setup_mac_pwr_sel(priv);
1109 if (ret)
1110 return ret;
1111
1112 /* Enable CPU Port */
1113 ret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,
1114 QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
1115 if (ret) {
1116 dev_err(priv->dev, "failed enabling CPU port");
1117 return ret;
1118 }
1119
1120 /* Enable MIB counters */
1121 ret = qca8k_mib_init(priv);
1122 if (ret)
1123 dev_warn(priv->dev, "mib init failed");
1124
1125 /* Initial setup of all ports */
1126 for (i = 0; i < QCA8K_NUM_PORTS; i++) {
1127 /* Disable forwarding by default on all ports */
1128 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
1129 QCA8K_PORT_LOOKUP_MEMBER, 0);
1130 if (ret)
1131 return ret;
1132
1133 /* Enable QCA header mode on all cpu ports */
1134 if (dsa_is_cpu_port(ds, i)) {
1135 ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(i),
1136 QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S |
1137 QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S);
1138 if (ret) {
1139 dev_err(priv->dev, "failed enabling QCA header mode");
1140 return ret;
1141 }
1142 }
1143
1144 /* Disable MAC by default on all user ports */
1145 if (dsa_is_user_port(ds, i))
1146 qca8k_port_set_status(priv, i, 0);
1147 }
1148
1149 /* Forward all unknown frames to CPU port for Linux processing
1150 * Notice that in multi-cpu config only one port should be set
1151 * for igmp, unknown, multicast and broadcast packet
1152 */
1153 ret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,
1154 BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S |
1155 BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S |
1156 BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S |
1157 BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S);
1158 if (ret)
1159 return ret;
1160
1161 /* Setup connection between CPU port & user ports
1162 * Configure specific switch configuration for ports
1163 */
1164 for (i = 0; i < QCA8K_NUM_PORTS; i++) {
1165 /* CPU port gets connected to all user ports of the switch */
1166 if (dsa_is_cpu_port(ds, i)) {
1167 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
1168 QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds));
1169 if (ret)
1170 return ret;
1171 }
1172
1173 /* Individual user ports get connected to CPU port only */
1174 if (dsa_is_user_port(ds, i)) {
1175 int shift = 16 * (i % 2);
1176
1177 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
1178 QCA8K_PORT_LOOKUP_MEMBER,
1179 BIT(cpu_port));
1180 if (ret)
1181 return ret;
1182
1183 /* Enable ARP Auto-learning by default */
1184 ret = qca8k_reg_set(priv, QCA8K_PORT_LOOKUP_CTRL(i),
1185 QCA8K_PORT_LOOKUP_LEARN);
1186 if (ret)
1187 return ret;
1188
1189 /* For port based vlans to work we need to set the
1190 * default egress vid
1191 */
1192 ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i),
1193 0xfff << shift,
1194 QCA8K_PORT_VID_DEF << shift);
1195 if (ret)
1196 return ret;
1197
1198 ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i),
1199 QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF) |
1200 QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF));
1201 if (ret)
1202 return ret;
1203 }
1204
1205 /* The port 5 of the qca8337 have some problem in flood condition. The
1206 * original legacy driver had some specific buffer and priority settings
1207 * for the different port suggested by the QCA switch team. Add this
1208 * missing settings to improve switch stability under load condition.
1209 * This problem is limited to qca8337 and other qca8k switch are not affected.
1210 */
1211 if (priv->switch_id == QCA8K_ID_QCA8337) {
1212 switch (i) {
1213 /* The 2 CPU port and port 5 requires some different
1214 * priority than any other ports.
1215 */
1216 case 0:
1217 case 5:
1218 case 6:
1219 mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) |
1220 QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) |
1221 QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x4) |
1222 QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x4) |
1223 QCA8K_PORT_HOL_CTRL0_EG_PRI4(0x6) |
1224 QCA8K_PORT_HOL_CTRL0_EG_PRI5(0x8) |
1225 QCA8K_PORT_HOL_CTRL0_EG_PORT(0x1e);
1226 break;
1227 default:
1228 mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) |
1229 QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) |
1230 QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x6) |
1231 QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x8) |
1232 QCA8K_PORT_HOL_CTRL0_EG_PORT(0x19);
1233 }
1234 qca8k_write(priv, QCA8K_REG_PORT_HOL_CTRL0(i), mask);
1235
1236 mask = QCA8K_PORT_HOL_CTRL1_ING(0x6) |
1237 QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |
1238 QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
1239 QCA8K_PORT_HOL_CTRL1_WRED_EN;
1240 qca8k_rmw(priv, QCA8K_REG_PORT_HOL_CTRL1(i),
1241 QCA8K_PORT_HOL_CTRL1_ING_BUF |
1242 QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |
1243 QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
1244 QCA8K_PORT_HOL_CTRL1_WRED_EN,
1245 mask);
1246 }
1247
1248 /* Set initial MTU for every port.
1249 * We have only have a general MTU setting. So track
1250 * every port and set the max across all port.
1251 */
1252 priv->port_mtu[i] = ETH_FRAME_LEN + ETH_FCS_LEN;
1253 }
1254
1255 /* Special GLOBAL_FC_THRESH value are needed for ar8327 switch */
1256 if (priv->switch_id == QCA8K_ID_QCA8327) {
1257 mask = QCA8K_GLOBAL_FC_GOL_XON_THRES(288) |
1258 QCA8K_GLOBAL_FC_GOL_XOFF_THRES(496);
1259 qca8k_rmw(priv, QCA8K_REG_GLOBAL_FC_THRESH,
1260 QCA8K_GLOBAL_FC_GOL_XON_THRES_S |
1261 QCA8K_GLOBAL_FC_GOL_XOFF_THRES_S,
1262 mask);
1263 }
1264
1265 /* Setup our port MTUs to match power on defaults */
1266 ret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN);
1267 if (ret)
1268 dev_warn(priv->dev, "failed setting MTU settings");
1269
1270 /* Flush the FDB table */
1271 qca8k_fdb_flush(priv);
1272
1273 /* We don't have interrupts for link changes, so we need to poll */
1274 ds->pcs_poll = true;
1275
1276 return 0;
1277 }
1278
1279 static void
1280 qca8k_mac_config_setup_internal_delay(struct qca8k_priv *priv, int cpu_port_index,
1281 u32 reg)
1282 {
1283 u32 delay, val = 0;
1284 int ret;
1285
1286 /* Delay can be declared in 3 different way.
1287 * Mode to rgmii and internal-delay standard binding defined
1288 * rgmii-id or rgmii-tx/rx phy mode set.
1289 * The parse logic set a delay different than 0 only when one
1290 * of the 3 different way is used. In all other case delay is
1291 * not enabled. With ID or TX/RXID delay is enabled and set
1292 * to the default and recommended value.
1293 */
1294 if (priv->ports_config.rgmii_tx_delay[cpu_port_index]) {
1295 delay = priv->ports_config.rgmii_tx_delay[cpu_port_index];
1296
1297 val |= QCA8K_PORT_PAD_RGMII_TX_DELAY(delay) |
1298 QCA8K_PORT_PAD_RGMII_TX_DELAY_EN;
1299 }
1300
1301 if (priv->ports_config.rgmii_rx_delay[cpu_port_index]) {
1302 delay = priv->ports_config.rgmii_rx_delay[cpu_port_index];
1303
1304 val |= QCA8K_PORT_PAD_RGMII_RX_DELAY(delay) |
1305 QCA8K_PORT_PAD_RGMII_RX_DELAY_EN;
1306 }
1307
1308 /* Set RGMII delay based on the selected values */
1309 ret = qca8k_rmw(priv, reg,
1310 QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK |
1311 QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK |
1312 QCA8K_PORT_PAD_RGMII_TX_DELAY_EN |
1313 QCA8K_PORT_PAD_RGMII_RX_DELAY_EN,
1314 val);
1315 if (ret)
1316 dev_err(priv->dev, "Failed to set internal delay for CPU port%d",
1317 cpu_port_index == QCA8K_CPU_PORT0 ? 0 : 6);
1318 }
1319
1320 static void
1321 qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
1322 const struct phylink_link_state *state)
1323 {
1324 struct qca8k_priv *priv = ds->priv;
1325 int cpu_port_index, ret;
1326 u32 reg, val;
1327
1328 switch (port) {
1329 case 0: /* 1st CPU port */
1330 if (state->interface != PHY_INTERFACE_MODE_RGMII &&
1331 state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
1332 state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
1333 state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
1334 state->interface != PHY_INTERFACE_MODE_SGMII)
1335 return;
1336
1337 reg = QCA8K_REG_PORT0_PAD_CTRL;
1338 cpu_port_index = QCA8K_CPU_PORT0;
1339 break;
1340 case 1:
1341 case 2:
1342 case 3:
1343 case 4:
1344 case 5:
1345 /* Internal PHY, nothing to do */
1346 return;
1347 case 6: /* 2nd CPU port / external PHY */
1348 if (state->interface != PHY_INTERFACE_MODE_RGMII &&
1349 state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
1350 state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
1351 state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
1352 state->interface != PHY_INTERFACE_MODE_SGMII &&
1353 state->interface != PHY_INTERFACE_MODE_1000BASEX)
1354 return;
1355
1356 reg = QCA8K_REG_PORT6_PAD_CTRL;
1357 cpu_port_index = QCA8K_CPU_PORT6;
1358 break;
1359 default:
1360 dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
1361 return;
1362 }
1363
1364 if (port != 6 && phylink_autoneg_inband(mode)) {
1365 dev_err(ds->dev, "%s: in-band negotiation unsupported\n",
1366 __func__);
1367 return;
1368 }
1369
1370 switch (state->interface) {
1371 case PHY_INTERFACE_MODE_RGMII:
1372 case PHY_INTERFACE_MODE_RGMII_ID:
1373 case PHY_INTERFACE_MODE_RGMII_TXID:
1374 case PHY_INTERFACE_MODE_RGMII_RXID:
1375 qca8k_write(priv, reg, QCA8K_PORT_PAD_RGMII_EN);
1376
1377 /* Configure rgmii delay */
1378 qca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg);
1379
1380 /* QCA8337 requires to set rgmii rx delay for all ports.
1381 * This is enabled through PORT5_PAD_CTRL for all ports,
1382 * rather than individual port registers.
1383 */
1384 if (priv->switch_id == QCA8K_ID_QCA8337)
1385 qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
1386 QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
1387 break;
1388 case PHY_INTERFACE_MODE_SGMII:
1389 case PHY_INTERFACE_MODE_1000BASEX:
1390 /* Enable SGMII on the port */
1391 qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
1392
1393 /* Enable/disable SerDes auto-negotiation as necessary */
1394 ret = qca8k_read(priv, QCA8K_REG_PWS, &val);
1395 if (ret)
1396 return;
1397 if (phylink_autoneg_inband(mode))
1398 val &= ~QCA8K_PWS_SERDES_AEN_DIS;
1399 else
1400 val |= QCA8K_PWS_SERDES_AEN_DIS;
1401 qca8k_write(priv, QCA8K_REG_PWS, val);
1402
1403 /* Configure the SGMII parameters */
1404 ret = qca8k_read(priv, QCA8K_REG_SGMII_CTRL, &val);
1405 if (ret)
1406 return;
1407
1408 val |= QCA8K_SGMII_EN_SD;
1409
1410 if (priv->ports_config.sgmii_enable_pll)
1411 val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |
1412 QCA8K_SGMII_EN_TX;
1413
1414 if (dsa_is_cpu_port(ds, port)) {
1415 /* CPU port, we're talking to the CPU MAC, be a PHY */
1416 val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
1417 val |= QCA8K_SGMII_MODE_CTRL_PHY;
1418 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
1419 val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
1420 val |= QCA8K_SGMII_MODE_CTRL_MAC;
1421 } else if (state->interface == PHY_INTERFACE_MODE_1000BASEX) {
1422 val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
1423 val |= QCA8K_SGMII_MODE_CTRL_BASEX;
1424 }
1425
1426 qca8k_write(priv, QCA8K_REG_SGMII_CTRL, val);
1427
1428 /* For qca8327/qca8328/qca8334/qca8338 sgmii is unique and
1429 * falling edge is set writing in the PORT0 PAD reg
1430 */
1431 if (priv->switch_id == QCA8K_ID_QCA8327 ||
1432 priv->switch_id == QCA8K_ID_QCA8337)
1433 reg = QCA8K_REG_PORT0_PAD_CTRL;
1434
1435 val = 0;
1436
1437 /* SGMII Clock phase configuration */
1438 if (priv->ports_config.sgmii_rx_clk_falling_edge)
1439 val |= QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE;
1440
1441 if (priv->ports_config.sgmii_tx_clk_falling_edge)
1442 val |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE;
1443
1444 if (val)
1445 ret = qca8k_rmw(priv, reg,
1446 QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE |
1447 QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE,
1448 val);
1449
1450 /* From original code is reported port instability as SGMII also
1451 * require delay set. Apply advised values here or take them from DT.
1452 */
1453 if (state->interface == PHY_INTERFACE_MODE_SGMII)
1454 qca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg);
1455
1456 break;
1457 default:
1458 dev_err(ds->dev, "xMII mode %s not supported for port %d\n",
1459 phy_modes(state->interface), port);
1460 return;
1461 }
1462 }
1463
1464 static void
1465 qca8k_phylink_validate(struct dsa_switch *ds, int port,
1466 unsigned long *supported,
1467 struct phylink_link_state *state)
1468 {
1469 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1470
1471 switch (port) {
1472 case 0: /* 1st CPU port */
1473 if (state->interface != PHY_INTERFACE_MODE_NA &&
1474 state->interface != PHY_INTERFACE_MODE_RGMII &&
1475 state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
1476 state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
1477 state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
1478 state->interface != PHY_INTERFACE_MODE_SGMII)
1479 goto unsupported;
1480 break;
1481 case 1:
1482 case 2:
1483 case 3:
1484 case 4:
1485 case 5:
1486 /* Internal PHY */
1487 if (state->interface != PHY_INTERFACE_MODE_NA &&
1488 state->interface != PHY_INTERFACE_MODE_GMII &&
1489 state->interface != PHY_INTERFACE_MODE_INTERNAL)
1490 goto unsupported;
1491 break;
1492 case 6: /* 2nd CPU port / external PHY */
1493 if (state->interface != PHY_INTERFACE_MODE_NA &&
1494 state->interface != PHY_INTERFACE_MODE_RGMII &&
1495 state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
1496 state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
1497 state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
1498 state->interface != PHY_INTERFACE_MODE_SGMII &&
1499 state->interface != PHY_INTERFACE_MODE_1000BASEX)
1500 goto unsupported;
1501 break;
1502 default:
1503 unsupported:
1504 linkmode_zero(supported);
1505 return;
1506 }
1507
1508 phylink_set_port_modes(mask);
1509 phylink_set(mask, Autoneg);
1510
1511 phylink_set(mask, 1000baseT_Full);
1512 phylink_set(mask, 10baseT_Half);
1513 phylink_set(mask, 10baseT_Full);
1514 phylink_set(mask, 100baseT_Half);
1515 phylink_set(mask, 100baseT_Full);
1516
1517 if (state->interface == PHY_INTERFACE_MODE_1000BASEX)
1518 phylink_set(mask, 1000baseX_Full);
1519
1520 phylink_set(mask, Pause);
1521 phylink_set(mask, Asym_Pause);
1522
1523 linkmode_and(supported, supported, mask);
1524 linkmode_and(state->advertising, state->advertising, mask);
1525 }
1526
1527 static int
1528 qca8k_phylink_mac_link_state(struct dsa_switch *ds, int port,
1529 struct phylink_link_state *state)
1530 {
1531 struct qca8k_priv *priv = ds->priv;
1532 u32 reg;
1533 int ret;
1534
1535 ret = qca8k_read(priv, QCA8K_REG_PORT_STATUS(port), &reg);
1536 if (ret < 0)
1537 return ret;
1538
1539 state->link = !!(reg & QCA8K_PORT_STATUS_LINK_UP);
1540 state->an_complete = state->link;
1541 state->an_enabled = !!(reg & QCA8K_PORT_STATUS_LINK_AUTO);
1542 state->duplex = (reg & QCA8K_PORT_STATUS_DUPLEX) ? DUPLEX_FULL :
1543 DUPLEX_HALF;
1544
1545 switch (reg & QCA8K_PORT_STATUS_SPEED) {
1546 case QCA8K_PORT_STATUS_SPEED_10:
1547 state->speed = SPEED_10;
1548 break;
1549 case QCA8K_PORT_STATUS_SPEED_100:
1550 state->speed = SPEED_100;
1551 break;
1552 case QCA8K_PORT_STATUS_SPEED_1000:
1553 state->speed = SPEED_1000;
1554 break;
1555 default:
1556 state->speed = SPEED_UNKNOWN;
1557 break;
1558 }
1559
1560 state->pause = MLO_PAUSE_NONE;
1561 if (reg & QCA8K_PORT_STATUS_RXFLOW)
1562 state->pause |= MLO_PAUSE_RX;
1563 if (reg & QCA8K_PORT_STATUS_TXFLOW)
1564 state->pause |= MLO_PAUSE_TX;
1565
1566 return 1;
1567 }
1568
1569 static void
1570 qca8k_phylink_mac_link_down(struct dsa_switch *ds, int port, unsigned int mode,
1571 phy_interface_t interface)
1572 {
1573 struct qca8k_priv *priv = ds->priv;
1574
1575 qca8k_port_set_status(priv, port, 0);
1576 }
1577
1578 static void
1579 qca8k_phylink_mac_link_up(struct dsa_switch *ds, int port, unsigned int mode,
1580 phy_interface_t interface, struct phy_device *phydev,
1581 int speed, int duplex, bool tx_pause, bool rx_pause)
1582 {
1583 struct qca8k_priv *priv = ds->priv;
1584 u32 reg;
1585
1586 if (phylink_autoneg_inband(mode)) {
1587 reg = QCA8K_PORT_STATUS_LINK_AUTO;
1588 } else {
1589 switch (speed) {
1590 case SPEED_10:
1591 reg = QCA8K_PORT_STATUS_SPEED_10;
1592 break;
1593 case SPEED_100:
1594 reg = QCA8K_PORT_STATUS_SPEED_100;
1595 break;
1596 case SPEED_1000:
1597 reg = QCA8K_PORT_STATUS_SPEED_1000;
1598 break;
1599 default:
1600 reg = QCA8K_PORT_STATUS_LINK_AUTO;
1601 break;
1602 }
1603
1604 if (duplex == DUPLEX_FULL)
1605 reg |= QCA8K_PORT_STATUS_DUPLEX;
1606
1607 if (rx_pause || dsa_is_cpu_port(ds, port))
1608 reg |= QCA8K_PORT_STATUS_RXFLOW;
1609
1610 if (tx_pause || dsa_is_cpu_port(ds, port))
1611 reg |= QCA8K_PORT_STATUS_TXFLOW;
1612 }
1613
1614 reg |= QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
1615
1616 qca8k_write(priv, QCA8K_REG_PORT_STATUS(port), reg);
1617 }
1618
1619 static void
1620 qca8k_get_strings(struct dsa_switch *ds, int port, u32 stringset, uint8_t *data)
1621 {
1622 int i;
1623
1624 if (stringset != ETH_SS_STATS)
1625 return;
1626
1627 for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++)
1628 strncpy(data + i * ETH_GSTRING_LEN, ar8327_mib[i].name,
1629 ETH_GSTRING_LEN);
1630 }
1631
1632 static void
1633 qca8k_get_ethtool_stats(struct dsa_switch *ds, int port,
1634 uint64_t *data)
1635 {
1636 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1637 const struct qca8k_mib_desc *mib;
1638 u32 reg, i, val;
1639 u32 hi = 0;
1640 int ret;
1641
1642 for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) {
1643 mib = &ar8327_mib[i];
1644 reg = QCA8K_PORT_MIB_COUNTER(port) + mib->offset;
1645
1646 ret = qca8k_read(priv, reg, &val);
1647 if (ret < 0)
1648 continue;
1649
1650 if (mib->size == 2) {
1651 ret = qca8k_read(priv, reg + 4, &hi);
1652 if (ret < 0)
1653 continue;
1654 }
1655
1656 data[i] = val;
1657 if (mib->size == 2)
1658 data[i] |= (u64)hi << 32;
1659 }
1660 }
1661
1662 static int
1663 qca8k_get_sset_count(struct dsa_switch *ds, int port, int sset)
1664 {
1665 if (sset != ETH_SS_STATS)
1666 return 0;
1667
1668 return ARRAY_SIZE(ar8327_mib);
1669 }
1670
1671 static int
1672 qca8k_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *eee)
1673 {
1674 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1675 u32 lpi_en = QCA8K_REG_EEE_CTRL_LPI_EN(port);
1676 u32 reg;
1677 int ret;
1678
1679 mutex_lock(&priv->reg_mutex);
1680 ret = qca8k_read(priv, QCA8K_REG_EEE_CTRL, &reg);
1681 if (ret < 0)
1682 goto exit;
1683
1684 if (eee->eee_enabled)
1685 reg |= lpi_en;
1686 else
1687 reg &= ~lpi_en;
1688 ret = qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg);
1689
1690 exit:
1691 mutex_unlock(&priv->reg_mutex);
1692 return ret;
1693 }
1694
1695 static int
1696 qca8k_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1697 {
1698 /* Nothing to do on the port's MAC */
1699 return 0;
1700 }
1701
1702 static void
1703 qca8k_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1704 {
1705 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1706 u32 stp_state;
1707
1708 switch (state) {
1709 case BR_STATE_DISABLED:
1710 stp_state = QCA8K_PORT_LOOKUP_STATE_DISABLED;
1711 break;
1712 case BR_STATE_BLOCKING:
1713 stp_state = QCA8K_PORT_LOOKUP_STATE_BLOCKING;
1714 break;
1715 case BR_STATE_LISTENING:
1716 stp_state = QCA8K_PORT_LOOKUP_STATE_LISTENING;
1717 break;
1718 case BR_STATE_LEARNING:
1719 stp_state = QCA8K_PORT_LOOKUP_STATE_LEARNING;
1720 break;
1721 case BR_STATE_FORWARDING:
1722 default:
1723 stp_state = QCA8K_PORT_LOOKUP_STATE_FORWARD;
1724 break;
1725 }
1726
1727 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
1728 QCA8K_PORT_LOOKUP_STATE_MASK, stp_state);
1729 }
1730
1731 static int
1732 qca8k_port_bridge_join(struct dsa_switch *ds, int port, struct net_device *br)
1733 {
1734 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1735 int port_mask, cpu_port;
1736 int i, ret;
1737
1738 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
1739 port_mask = BIT(cpu_port);
1740
1741 for (i = 0; i < QCA8K_NUM_PORTS; i++) {
1742 if (dsa_is_cpu_port(ds, i))
1743 continue;
1744 if (dsa_to_port(ds, i)->bridge_dev != br)
1745 continue;
1746 /* Add this port to the portvlan mask of the other ports
1747 * in the bridge
1748 */
1749 ret = qca8k_reg_set(priv,
1750 QCA8K_PORT_LOOKUP_CTRL(i),
1751 BIT(port));
1752 if (ret)
1753 return ret;
1754 if (i != port)
1755 port_mask |= BIT(i);
1756 }
1757
1758 /* Add all other ports to this ports portvlan mask */
1759 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
1760 QCA8K_PORT_LOOKUP_MEMBER, port_mask);
1761
1762 return ret;
1763 }
1764
1765 static void
1766 qca8k_port_bridge_leave(struct dsa_switch *ds, int port, struct net_device *br)
1767 {
1768 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1769 int cpu_port, i;
1770
1771 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
1772
1773 for (i = 0; i < QCA8K_NUM_PORTS; i++) {
1774 if (dsa_is_cpu_port(ds, i))
1775 continue;
1776 if (dsa_to_port(ds, i)->bridge_dev != br)
1777 continue;
1778 /* Remove this port to the portvlan mask of the other ports
1779 * in the bridge
1780 */
1781 qca8k_reg_clear(priv,
1782 QCA8K_PORT_LOOKUP_CTRL(i),
1783 BIT(port));
1784 }
1785
1786 /* Set the cpu port to be the only one in the portvlan mask of
1787 * this port
1788 */
1789 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
1790 QCA8K_PORT_LOOKUP_MEMBER, BIT(cpu_port));
1791 }
1792
1793 static int
1794 qca8k_port_enable(struct dsa_switch *ds, int port,
1795 struct phy_device *phy)
1796 {
1797 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1798
1799 qca8k_port_set_status(priv, port, 1);
1800 priv->port_sts[port].enabled = 1;
1801
1802 if (dsa_is_user_port(ds, port))
1803 phy_support_asym_pause(phy);
1804
1805 return 0;
1806 }
1807
1808 static void
1809 qca8k_port_disable(struct dsa_switch *ds, int port)
1810 {
1811 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1812
1813 qca8k_port_set_status(priv, port, 0);
1814 priv->port_sts[port].enabled = 0;
1815 }
1816
1817 static int
1818 qca8k_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
1819 {
1820 struct qca8k_priv *priv = ds->priv;
1821 int i, mtu = 0;
1822
1823 priv->port_mtu[port] = new_mtu;
1824
1825 for (i = 0; i < QCA8K_NUM_PORTS; i++)
1826 if (priv->port_mtu[i] > mtu)
1827 mtu = priv->port_mtu[i];
1828
1829 /* Include L2 header / FCS length */
1830 return qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, mtu + ETH_HLEN + ETH_FCS_LEN);
1831 }
1832
1833 static int
1834 qca8k_port_max_mtu(struct dsa_switch *ds, int port)
1835 {
1836 return QCA8K_MAX_MTU;
1837 }
1838
1839 static int
1840 qca8k_port_fdb_insert(struct qca8k_priv *priv, const u8 *addr,
1841 u16 port_mask, u16 vid)
1842 {
1843 /* Set the vid to the port vlan id if no vid is set */
1844 if (!vid)
1845 vid = QCA8K_PORT_VID_DEF;
1846
1847 return qca8k_fdb_add(priv, addr, port_mask, vid,
1848 QCA8K_ATU_STATUS_STATIC);
1849 }
1850
1851 static int
1852 qca8k_port_fdb_add(struct dsa_switch *ds, int port,
1853 const unsigned char *addr, u16 vid)
1854 {
1855 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1856 u16 port_mask = BIT(port);
1857
1858 return qca8k_port_fdb_insert(priv, addr, port_mask, vid);
1859 }
1860
1861 static int
1862 qca8k_port_fdb_del(struct dsa_switch *ds, int port,
1863 const unsigned char *addr, u16 vid)
1864 {
1865 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1866 u16 port_mask = BIT(port);
1867
1868 if (!vid)
1869 vid = QCA8K_PORT_VID_DEF;
1870
1871 return qca8k_fdb_del(priv, addr, port_mask, vid);
1872 }
1873
1874 static int
1875 qca8k_port_fdb_dump(struct dsa_switch *ds, int port,
1876 dsa_fdb_dump_cb_t *cb, void *data)
1877 {
1878 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1879 struct qca8k_fdb _fdb = { 0 };
1880 int cnt = QCA8K_NUM_FDB_RECORDS;
1881 bool is_static;
1882 int ret = 0;
1883
1884 mutex_lock(&priv->reg_mutex);
1885 while (cnt-- && !qca8k_fdb_next(priv, &_fdb, port)) {
1886 if (!_fdb.aging)
1887 break;
1888 is_static = (_fdb.aging == QCA8K_ATU_STATUS_STATIC);
1889 ret = cb(_fdb.mac, _fdb.vid, is_static, data);
1890 if (ret)
1891 break;
1892 }
1893 mutex_unlock(&priv->reg_mutex);
1894
1895 return 0;
1896 }
1897
1898 static int
1899 qca8k_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
1900 struct switchdev_trans *trans)
1901 {
1902 struct qca8k_priv *priv = ds->priv;
1903
1904 if (switchdev_trans_ph_prepare(trans))
1905 return 0;
1906
1907 if (vlan_filtering) {
1908 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
1909 QCA8K_PORT_LOOKUP_VLAN_MODE,
1910 QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE);
1911 } else {
1912 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
1913 QCA8K_PORT_LOOKUP_VLAN_MODE,
1914 QCA8K_PORT_LOOKUP_VLAN_MODE_NONE);
1915 }
1916
1917 return 0;
1918 }
1919
1920 static int
1921 qca8k_port_vlan_prepare(struct dsa_switch *ds, int port,
1922 const struct switchdev_obj_port_vlan *vlan)
1923 {
1924 return 0;
1925 }
1926
1927 static void
1928 qca8k_port_vlan_add(struct dsa_switch *ds, int port,
1929 const struct switchdev_obj_port_vlan *vlan)
1930 {
1931 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1932 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1933 struct qca8k_priv *priv = ds->priv;
1934 int ret = 0;
1935 u16 vid;
1936
1937 for (vid = vlan->vid_begin; vid <= vlan->vid_end && !ret; ++vid)
1938 ret = qca8k_vlan_add(priv, port, vid, untagged);
1939
1940 if (ret)
1941 dev_err(priv->dev, "Failed to add VLAN to port %d (%d)", port, ret);
1942
1943 if (pvid) {
1944 int shift = 16 * (port % 2);
1945
1946 qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port),
1947 0xfff << shift,
1948 vlan->vid_end << shift);
1949 qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(port),
1950 QCA8K_PORT_VLAN_CVID(vlan->vid_end) |
1951 QCA8K_PORT_VLAN_SVID(vlan->vid_end));
1952 }
1953 }
1954
1955 static int
1956 qca8k_port_vlan_del(struct dsa_switch *ds, int port,
1957 const struct switchdev_obj_port_vlan *vlan)
1958 {
1959 struct qca8k_priv *priv = ds->priv;
1960 int ret = 0;
1961 u16 vid;
1962
1963 for (vid = vlan->vid_begin; vid <= vlan->vid_end && !ret; ++vid)
1964 ret = qca8k_vlan_del(priv, port, vid);
1965
1966 if (ret)
1967 dev_err(priv->dev, "Failed to delete VLAN from port %d (%d)", port, ret);
1968
1969 return ret;
1970 }
1971
1972 static u32 qca8k_get_phy_flags(struct dsa_switch *ds, int port)
1973 {
1974 struct qca8k_priv *priv = ds->priv;
1975
1976 /* Communicate to the phy internal driver the switch revision.
1977 * Based on the switch revision different values needs to be
1978 * set to the dbg and mmd reg on the phy.
1979 * The first 2 bit are used to communicate the switch revision
1980 * to the phy driver.
1981 */
1982 if (port > 0 && port < 6)
1983 return priv->switch_revision;
1984
1985 return 0;
1986 }
1987
1988 static enum dsa_tag_protocol
1989 qca8k_get_tag_protocol(struct dsa_switch *ds, int port,
1990 enum dsa_tag_protocol mp)
1991 {
1992 return DSA_TAG_PROTO_QCA;
1993 }
1994
1995 static const struct dsa_switch_ops qca8k_switch_ops = {
1996 .get_tag_protocol = qca8k_get_tag_protocol,
1997 .setup = qca8k_setup,
1998 .get_strings = qca8k_get_strings,
1999 .get_ethtool_stats = qca8k_get_ethtool_stats,
2000 .get_sset_count = qca8k_get_sset_count,
2001 .get_mac_eee = qca8k_get_mac_eee,
2002 .set_mac_eee = qca8k_set_mac_eee,
2003 .port_enable = qca8k_port_enable,
2004 .port_disable = qca8k_port_disable,
2005 .port_change_mtu = qca8k_port_change_mtu,
2006 .port_max_mtu = qca8k_port_max_mtu,
2007 .port_stp_state_set = qca8k_port_stp_state_set,
2008 .port_bridge_join = qca8k_port_bridge_join,
2009 .port_bridge_leave = qca8k_port_bridge_leave,
2010 .port_fdb_add = qca8k_port_fdb_add,
2011 .port_fdb_del = qca8k_port_fdb_del,
2012 .port_fdb_dump = qca8k_port_fdb_dump,
2013 .port_vlan_filtering = qca8k_port_vlan_filtering,
2014 .port_vlan_prepare = qca8k_port_vlan_prepare,
2015 .port_vlan_add = qca8k_port_vlan_add,
2016 .port_vlan_del = qca8k_port_vlan_del,
2017 .phylink_validate = qca8k_phylink_validate,
2018 .phylink_mac_link_state = qca8k_phylink_mac_link_state,
2019 .phylink_mac_config = qca8k_phylink_mac_config,
2020 .phylink_mac_link_down = qca8k_phylink_mac_link_down,
2021 .phylink_mac_link_up = qca8k_phylink_mac_link_up,
2022 .get_phy_flags = qca8k_get_phy_flags,
2023 };
2024
2025 static int qca8k_read_switch_id(struct qca8k_priv *priv)
2026 {
2027 const struct qca8k_match_data *data;
2028 u32 val;
2029 u8 id;
2030 int ret;
2031
2032 /* get the switches ID from the compatible */
2033 data = of_device_get_match_data(priv->dev);
2034 if (!data)
2035 return -ENODEV;
2036
2037 ret = qca8k_read(priv, QCA8K_REG_MASK_CTRL, &val);
2038 if (ret < 0)
2039 return -ENODEV;
2040
2041 id = QCA8K_MASK_CTRL_DEVICE_ID(val & QCA8K_MASK_CTRL_DEVICE_ID_MASK);
2042 if (id != data->id) {
2043 dev_err(priv->dev, "Switch id detected %x but expected %x", id, data->id);
2044 return -ENODEV;
2045 }
2046
2047 priv->switch_id = id;
2048
2049 /* Save revision to communicate to the internal PHY driver */
2050 priv->switch_revision = (val & QCA8K_MASK_CTRL_REV_ID_MASK);
2051
2052 return 0;
2053 }
2054
2055 static int
2056 qca8k_sw_probe(struct mdio_device *mdiodev)
2057 {
2058 struct qca8k_priv *priv;
2059 int ret;
2060
2061 /* allocate the private data struct so that we can probe the switches
2062 * ID register
2063 */
2064 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
2065 if (!priv)
2066 return -ENOMEM;
2067
2068 priv->bus = mdiodev->bus;
2069 priv->dev = &mdiodev->dev;
2070
2071 priv->reset_gpio = devm_gpiod_get_optional(priv->dev, "reset",
2072 GPIOD_ASIS);
2073 if (IS_ERR(priv->reset_gpio))
2074 return PTR_ERR(priv->reset_gpio);
2075
2076 if (priv->reset_gpio) {
2077 gpiod_set_value_cansleep(priv->reset_gpio, 1);
2078 /* The active low duration must be greater than 10 ms
2079 * and checkpatch.pl wants 20 ms.
2080 */
2081 msleep(20);
2082 gpiod_set_value_cansleep(priv->reset_gpio, 0);
2083 }
2084
2085 /* Check the detected switch id */
2086 ret = qca8k_read_switch_id(priv);
2087 if (ret)
2088 return ret;
2089
2090 priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL);
2091 if (!priv->ds)
2092 return -ENOMEM;
2093
2094 priv->ds->dev = &mdiodev->dev;
2095 priv->ds->num_ports = QCA8K_NUM_PORTS;
2096 priv->ds->configure_vlan_while_not_filtering = true;
2097 priv->ds->priv = priv;
2098 priv->ops = qca8k_switch_ops;
2099 priv->ds->ops = &priv->ops;
2100 mutex_init(&priv->reg_mutex);
2101 dev_set_drvdata(&mdiodev->dev, priv);
2102
2103 return dsa_register_switch(priv->ds);
2104 }
2105
2106 static void
2107 qca8k_sw_remove(struct mdio_device *mdiodev)
2108 {
2109 struct qca8k_priv *priv = dev_get_drvdata(&mdiodev->dev);
2110 int i;
2111
2112 for (i = 0; i < QCA8K_NUM_PORTS; i++)
2113 qca8k_port_set_status(priv, i, 0);
2114
2115 dsa_unregister_switch(priv->ds);
2116 }
2117
2118 #ifdef CONFIG_PM_SLEEP
2119 static void
2120 qca8k_set_pm(struct qca8k_priv *priv, int enable)
2121 {
2122 int i;
2123
2124 for (i = 0; i < QCA8K_NUM_PORTS; i++) {
2125 if (!priv->port_sts[i].enabled)
2126 continue;
2127
2128 qca8k_port_set_status(priv, i, enable);
2129 }
2130 }
2131
2132 static int qca8k_suspend(struct device *dev)
2133 {
2134 struct qca8k_priv *priv = dev_get_drvdata(dev);
2135
2136 qca8k_set_pm(priv, 0);
2137
2138 return dsa_switch_suspend(priv->ds);
2139 }
2140
2141 static int qca8k_resume(struct device *dev)
2142 {
2143 struct qca8k_priv *priv = dev_get_drvdata(dev);
2144
2145 qca8k_set_pm(priv, 1);
2146
2147 return dsa_switch_resume(priv->ds);
2148 }
2149 #endif /* CONFIG_PM_SLEEP */
2150
2151 static SIMPLE_DEV_PM_OPS(qca8k_pm_ops,
2152 qca8k_suspend, qca8k_resume);
2153
2154 static const struct qca8k_match_data qca8327 = {
2155 .id = QCA8K_ID_QCA8327,
2156 .reduced_package = true,
2157 };
2158
2159 static const struct qca8k_match_data qca8328 = {
2160 .id = QCA8K_ID_QCA8327,
2161 };
2162
2163 static const struct qca8k_match_data qca833x = {
2164 .id = QCA8K_ID_QCA8337,
2165 };
2166
2167 static const struct of_device_id qca8k_of_match[] = {
2168 { .compatible = "qca,qca8327", .data = &qca8327 },
2169 { .compatible = "qca,qca8328", .data = &qca8328 },
2170 { .compatible = "qca,qca8334", .data = &qca833x },
2171 { .compatible = "qca,qca8337", .data = &qca833x },
2172 { /* sentinel */ },
2173 };
2174
2175 static struct mdio_driver qca8kmdio_driver = {
2176 .probe = qca8k_sw_probe,
2177 .remove = qca8k_sw_remove,
2178 .mdiodrv.driver = {
2179 .name = "qca8k",
2180 .of_match_table = qca8k_of_match,
2181 .pm = &qca8k_pm_ops,
2182 },
2183 };
2184
2185 mdio_module_driver(qca8kmdio_driver);
2186
2187 MODULE_AUTHOR("Mathieu Olivari, John Crispin <john@phrozen.org>");
2188 MODULE_DESCRIPTION("Driver for QCA8K ethernet switch family");
2189 MODULE_LICENSE("GPL v2");
2190 MODULE_ALIAS("platform:qca8k");
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