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[openwrt/staging/jow.git] / target / linux / ipq40xx / files / drivers / net / dsa / qca / qca8k-ipq4019.h
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
4 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
6 */
7
8 #ifndef __QCA8K_H
9 #define __QCA8K_H
10
11 #include <linux/regmap.h>
12
13 #define QCA8K_NUM_PORTS 6
14 #define QCA8K_CPU_PORT 0
15 #define QCA8K_MAX_MTU 9000
16
17 #define QCA8K_BUSY_WAIT_TIMEOUT 2000
18
19 #define QCA8K_NUM_FDB_RECORDS 2048
20
21 #define QCA8K_PORT_VID_DEF 1
22
23 /* Global control registers */
24 #define QCA8K_REG_MASK_CTRL 0x000
25 #define QCA8K_MASK_CTRL_REV_ID_MASK GENMASK(7, 0)
26 #define QCA8K_MASK_CTRL_REV_ID(x) ((x) >> 0)
27 #define QCA8K_MASK_CTRL_DEVICE_ID_MASK GENMASK(15, 8)
28 #define QCA8K_MASK_CTRL_DEVICE_ID(x) ((x) >> 8)
29 #define QCA8K_REG_RGMII_CTRL 0x004
30 #define QCA8K_RGMII_CTRL_RGMII_RXC GENMASK(1, 0)
31 #define QCA8K_RGMII_CTRL_RGMII_TXC GENMASK(9, 8)
32 /* Some kind of CLK selection
33 * 0: gcc_ess_dly2ns
34 * 1: gcc_ess_clk
35 */
36 #define QCA8K_RGMII_CTRL_CLK BIT(10)
37 #define QCA8K_RGMII_CTRL_DELAY_RMII0 GENMASK(17, 16)
38 #define QCA8K_RGMII_CTRL_INVERT_RMII0_REF_CLK BIT(18)
39 #define QCA8K_RGMII_CTRL_DELAY_RMII1 GENMASK(20, 19)
40 #define QCA8K_RGMII_CTRL_INVERT_RMII1_REF_CLK BIT(21)
41 #define QCA8K_RGMII_CTRL_INVERT_RMII0_MASTER_EN BIT(24)
42 #define QCA8K_RGMII_CTRL_INVERT_RMII1_MASTER_EN BIT(25)
43 #define QCA8K_REG_MODULE_EN 0x030
44 #define QCA8K_MODULE_EN_MIB BIT(0)
45 #define QCA8K_REG_MIB 0x034
46 #define QCA8K_MIB_FLUSH BIT(24)
47 #define QCA8K_MIB_CPU_KEEP BIT(20)
48 #define QCA8K_MIB_BUSY BIT(17)
49 #define QCA8K_GOL_MAC_ADDR0 0x60
50 #define QCA8K_GOL_MAC_ADDR1 0x64
51 #define QCA8K_MAX_FRAME_SIZE 0x78
52 #define QCA8K_REG_PORT_STATUS(_i) (0x07c + (_i) * 4)
53 #define QCA8K_PORT_STATUS_SPEED GENMASK(1, 0)
54 #define QCA8K_PORT_STATUS_SPEED_10 0
55 #define QCA8K_PORT_STATUS_SPEED_100 0x1
56 #define QCA8K_PORT_STATUS_SPEED_1000 0x2
57 #define QCA8K_PORT_STATUS_TXMAC BIT(2)
58 #define QCA8K_PORT_STATUS_RXMAC BIT(3)
59 #define QCA8K_PORT_STATUS_TXFLOW BIT(4)
60 #define QCA8K_PORT_STATUS_RXFLOW BIT(5)
61 #define QCA8K_PORT_STATUS_DUPLEX BIT(6)
62 #define QCA8K_PORT_STATUS_LINK_UP BIT(8)
63 #define QCA8K_PORT_STATUS_LINK_AUTO BIT(9)
64 #define QCA8K_PORT_STATUS_LINK_PAUSE BIT(10)
65 #define QCA8K_PORT_STATUS_FLOW_AUTO BIT(12)
66 #define QCA8K_REG_PORT_HDR_CTRL(_i) (0x9c + (_i * 4))
67 #define QCA8K_PORT_HDR_CTRL_RX_MASK GENMASK(3, 2)
68 #define QCA8K_PORT_HDR_CTRL_RX_S 2
69 #define QCA8K_PORT_HDR_CTRL_TX_MASK GENMASK(1, 0)
70 #define QCA8K_PORT_HDR_CTRL_TX_S 0
71 #define QCA8K_PORT_HDR_CTRL_ALL 2
72 #define QCA8K_PORT_HDR_CTRL_MGMT 1
73 #define QCA8K_PORT_HDR_CTRL_NONE 0
74 #define QCA8K_REG_SGMII_CTRL 0x0e0
75 #define QCA8K_SGMII_EN_PLL BIT(1)
76 #define QCA8K_SGMII_EN_RX BIT(2)
77 #define QCA8K_SGMII_EN_TX BIT(3)
78 #define QCA8K_SGMII_EN_SD BIT(4)
79 #define QCA8K_SGMII_CLK125M_DELAY BIT(7)
80 #define QCA8K_SGMII_MODE_CTRL_MASK (BIT(22) | BIT(23))
81 #define QCA8K_SGMII_MODE_CTRL_BASEX (0 << 22)
82 #define QCA8K_SGMII_MODE_CTRL_PHY (1 << 22)
83 #define QCA8K_SGMII_MODE_CTRL_MAC (2 << 22)
84
85 /* EEE control registers */
86 #define QCA8K_REG_EEE_CTRL 0x100
87 #define QCA8K_REG_EEE_CTRL_LPI_EN(_i) ((_i + 1) * 2)
88
89 /* ACL registers */
90 #define QCA8K_REG_PORT_VLAN_CTRL0(_i) (0x420 + (_i * 8))
91 #define QCA8K_PORT_VLAN_CVID(x) (x << 16)
92 #define QCA8K_PORT_VLAN_SVID(x) x
93 #define QCA8K_REG_PORT_VLAN_CTRL1(_i) (0x424 + (_i * 8))
94 #define QCA8K_REG_IPV4_PRI_BASE_ADDR 0x470
95 #define QCA8K_REG_IPV4_PRI_ADDR_MASK 0x474
96
97 /* Lookup registers */
98 #define QCA8K_REG_ATU_DATA0 0x600
99 #define QCA8K_ATU_ADDR2_S 24
100 #define QCA8K_ATU_ADDR3_S 16
101 #define QCA8K_ATU_ADDR4_S 8
102 #define QCA8K_REG_ATU_DATA1 0x604
103 #define QCA8K_ATU_PORT_M 0x7f
104 #define QCA8K_ATU_PORT_S 16
105 #define QCA8K_ATU_ADDR0_S 8
106 #define QCA8K_REG_ATU_DATA2 0x608
107 #define QCA8K_ATU_VID_M 0xfff
108 #define QCA8K_ATU_VID_S 8
109 #define QCA8K_ATU_STATUS_M 0xf
110 #define QCA8K_ATU_STATUS_STATIC 0xf
111 #define QCA8K_REG_ATU_FUNC 0x60c
112 #define QCA8K_ATU_FUNC_BUSY BIT(31)
113 #define QCA8K_ATU_FUNC_PORT_EN BIT(14)
114 #define QCA8K_ATU_FUNC_MULTI_EN BIT(13)
115 #define QCA8K_ATU_FUNC_FULL BIT(12)
116 #define QCA8K_ATU_FUNC_PORT_M 0xf
117 #define QCA8K_ATU_FUNC_PORT_S 8
118 #define QCA8K_REG_VTU_FUNC0 0x610
119 #define QCA8K_VTU_FUNC0_VALID BIT(20)
120 #define QCA8K_VTU_FUNC0_IVL_EN BIT(19)
121 #define QCA8K_VTU_FUNC0_EG_MODE_S(_i) (4 + (_i) * 2)
122 #define QCA8K_VTU_FUNC0_EG_MODE_MASK 3
123 #define QCA8K_VTU_FUNC0_EG_MODE_UNMOD 0
124 #define QCA8K_VTU_FUNC0_EG_MODE_UNTAG 1
125 #define QCA8K_VTU_FUNC0_EG_MODE_TAG 2
126 #define QCA8K_VTU_FUNC0_EG_MODE_NOT 3
127 #define QCA8K_REG_VTU_FUNC1 0x614
128 #define QCA8K_VTU_FUNC1_BUSY BIT(31)
129 #define QCA8K_VTU_FUNC1_VID_S 16
130 #define QCA8K_VTU_FUNC1_FULL BIT(4)
131 #define QCA8K_REG_GLOBAL_FW_CTRL0 0x620
132 #define QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN BIT(10)
133 #define QCA8K_REG_GLOBAL_FW_CTRL1 0x624
134 #define QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S 24
135 #define QCA8K_GLOBAL_FW_CTRL1_BC_DP_S 16
136 #define QCA8K_GLOBAL_FW_CTRL1_MC_DP_S 8
137 #define QCA8K_GLOBAL_FW_CTRL1_UC_DP_S 0
138 #define QCA8K_PORT_LOOKUP_CTRL(_i) (0x660 + (_i) * 0xc)
139 #define QCA8K_PORT_LOOKUP_MEMBER GENMASK(6, 0)
140 #define QCA8K_PORT_LOOKUP_VLAN_MODE GENMASK(9, 8)
141 #define QCA8K_PORT_LOOKUP_VLAN_MODE_NONE (0 << 8)
142 #define QCA8K_PORT_LOOKUP_VLAN_MODE_FALLBACK (1 << 8)
143 #define QCA8K_PORT_LOOKUP_VLAN_MODE_CHECK (2 << 8)
144 #define QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE (3 << 8)
145 #define QCA8K_PORT_LOOKUP_STATE_MASK GENMASK(18, 16)
146 #define QCA8K_PORT_LOOKUP_STATE_DISABLED (0 << 16)
147 #define QCA8K_PORT_LOOKUP_STATE_BLOCKING (1 << 16)
148 #define QCA8K_PORT_LOOKUP_STATE_LISTENING (2 << 16)
149 #define QCA8K_PORT_LOOKUP_STATE_LEARNING (3 << 16)
150 #define QCA8K_PORT_LOOKUP_STATE_FORWARD (4 << 16)
151 #define QCA8K_PORT_LOOKUP_STATE GENMASK(18, 16)
152 #define QCA8K_PORT_LOOKUP_LEARN BIT(20)
153
154 #define QCA8K_REG_GLOBAL_FC_THRESH 0x800
155 #define QCA8K_GLOBAL_FC_GOL_XON_THRES(x) ((x) << 16)
156 #define QCA8K_GLOBAL_FC_GOL_XON_THRES_S GENMASK(24, 16)
157 #define QCA8K_GLOBAL_FC_GOL_XOFF_THRES(x) ((x) << 0)
158 #define QCA8K_GLOBAL_FC_GOL_XOFF_THRES_S GENMASK(8, 0)
159
160 #define QCA8K_REG_PORT_HOL_CTRL0(_i) (0x970 + (_i) * 0x8)
161 #define QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF GENMASK(3, 0)
162 #define QCA8K_PORT_HOL_CTRL0_EG_PRI0(x) ((x) << 0)
163 #define QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF GENMASK(7, 4)
164 #define QCA8K_PORT_HOL_CTRL0_EG_PRI1(x) ((x) << 4)
165 #define QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF GENMASK(11, 8)
166 #define QCA8K_PORT_HOL_CTRL0_EG_PRI2(x) ((x) << 8)
167 #define QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF GENMASK(15, 12)
168 #define QCA8K_PORT_HOL_CTRL0_EG_PRI3(x) ((x) << 12)
169 #define QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF GENMASK(19, 16)
170 #define QCA8K_PORT_HOL_CTRL0_EG_PRI4(x) ((x) << 16)
171 #define QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF GENMASK(23, 20)
172 #define QCA8K_PORT_HOL_CTRL0_EG_PRI5(x) ((x) << 20)
173 #define QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF GENMASK(29, 24)
174 #define QCA8K_PORT_HOL_CTRL0_EG_PORT(x) ((x) << 24)
175
176 #define QCA8K_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8)
177 #define QCA8K_PORT_HOL_CTRL1_ING_BUF GENMASK(3, 0)
178 #define QCA8K_PORT_HOL_CTRL1_ING(x) ((x) << 0)
179 #define QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN BIT(6)
180 #define QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN BIT(7)
181 #define QCA8K_PORT_HOL_CTRL1_WRED_EN BIT(8)
182 #define QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN BIT(16)
183
184 /* Pkt edit registers */
185 #define QCA8K_EGRESS_VLAN(x) (0x0c70 + (4 * (x / 2)))
186
187 /* L3 registers */
188 #define QCA8K_HROUTER_CONTROL 0xe00
189 #define QCA8K_HROUTER_CONTROL_GLB_LOCKTIME_M GENMASK(17, 16)
190 #define QCA8K_HROUTER_CONTROL_GLB_LOCKTIME_S 16
191 #define QCA8K_HROUTER_CONTROL_ARP_AGE_MODE 1
192 #define QCA8K_HROUTER_PBASED_CONTROL1 0xe08
193 #define QCA8K_HROUTER_PBASED_CONTROL2 0xe0c
194 #define QCA8K_HNAT_CONTROL 0xe38
195
196 /* MIB registers */
197 #define QCA8K_PORT_MIB_COUNTER(_i) (0x1000 + (_i) * 0x100)
198
199 /* IPQ4019 PSGMII PHY registers */
200 #define PSGMIIPHY_MODE_CONTROL 0x1b4
201 #define PSGMIIPHY_MODE_ATHR_CSCO_MODE_25M BIT(0)
202 #define PSGMIIPHY_TX_CONTROL 0x288
203 #define PSGMIIPHY_TX_CONTROL_MAGIC_VALUE 0x8380
204 #define PSGMIIPHY_VCO_CALIBRATION_CONTROL_REGISTER_1 0x9c
205 #define PSGMIIPHY_REG_PLL_VCO_CALIB_RESTART BIT(14)
206 #define PSGMIIPHY_VCO_CALIBRATION_CONTROL_REGISTER_2 0xa0
207 #define PSGMIIPHY_REG_PLL_VCO_CALIB_READY BIT(0)
208
209 enum {
210 QCA8K_PORT_SPEED_10M = 0,
211 QCA8K_PORT_SPEED_100M = 1,
212 QCA8K_PORT_SPEED_1000M = 2,
213 QCA8K_PORT_SPEED_ERR = 3,
214 };
215
216 enum qca8k_fdb_cmd {
217 QCA8K_FDB_FLUSH = 1,
218 QCA8K_FDB_LOAD = 2,
219 QCA8K_FDB_PURGE = 3,
220 QCA8K_FDB_NEXT = 6,
221 QCA8K_FDB_SEARCH = 7,
222 };
223
224 enum qca8k_vlan_cmd {
225 QCA8K_VLAN_FLUSH = 1,
226 QCA8K_VLAN_LOAD = 2,
227 QCA8K_VLAN_PURGE = 3,
228 QCA8K_VLAN_REMOVE_PORT = 4,
229 QCA8K_VLAN_NEXT = 5,
230 QCA8K_VLAN_READ = 6,
231 };
232
233 struct ar8xxx_port_status {
234 int enabled;
235 };
236
237 struct qca8k_priv {
238 struct regmap *regmap;
239 struct mii_bus *bus;
240 struct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS];
241 struct dsa_switch *ds;
242 struct mutex reg_mutex;
243 struct device *dev;
244 struct dsa_switch_ops ops;
245 unsigned int port_mtu[QCA8K_NUM_PORTS];
246
247 /* IPQ4019 specific */
248 struct regmap *psgmii;
249 bool psgmii_calibrated;
250 struct phy_device *psgmii_ethphy;
251 };
252
253 struct qca8k_mib_desc {
254 unsigned int size;
255 unsigned int offset;
256 const char *name;
257 };
258
259 struct qca8k_fdb {
260 u16 vid;
261 u8 port_mask;
262 u8 aging;
263 u8 mac[6];
264 };
265
266 #endif /* __QCA8K_H */
Staging tree of Jo-Philipp Wich