target/linux/ipq40xx/files/drivers/net/ethernet/qualcomm/essedma/ess_edma.h

   1 /*
   2  * Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for
   5  * any purpose with or without fee is hereby granted, provided that the
   6  * above copyright notice and this permission notice appear in all copies.
   7  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   8  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
   9  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  10  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  11  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  12  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
  13  * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  14  */
  15
  16 #ifndef _ESS_EDMA_H_
  17 #define _ESS_EDMA_H_
  18
  19 #include <linux/types.h>
  20
  21 struct edma_adapter;
  22 struct edma_hw;
  23
  24 /* register definition */
  25 #define EDMA_REG_MAS_CTRL 0x0
  26 #define EDMA_REG_TIMEOUT_CTRL 0x004
  27 #define EDMA_REG_DBG0 0x008
  28 #define EDMA_REG_DBG1 0x00C
  29 #define EDMA_REG_SW_CTRL0 0x100
  30 #define EDMA_REG_SW_CTRL1 0x104
  31
  32 /* Interrupt Status Register */
  33 #define EDMA_REG_RX_ISR 0x200
  34 #define EDMA_REG_TX_ISR 0x208
  35 #define EDMA_REG_MISC_ISR 0x210
  36 #define EDMA_REG_WOL_ISR 0x218
  37
  38 #define EDMA_MISC_ISR_RX_URG_Q(x) (1 << x)
  39
  40 #define EDMA_MISC_ISR_AXIR_TIMEOUT 0x00000100
  41 #define EDMA_MISC_ISR_AXIR_ERR 0x00000200
  42 #define EDMA_MISC_ISR_TXF_DEAD 0x00000400
  43 #define EDMA_MISC_ISR_AXIW_ERR 0x00000800
  44 #define EDMA_MISC_ISR_AXIW_TIMEOUT 0x00001000
  45
  46 #define EDMA_WOL_ISR 0x00000001
  47
  48 /* Interrupt Mask Register */
  49 #define EDMA_REG_MISC_IMR 0x214
  50 #define EDMA_REG_WOL_IMR 0x218
  51
  52 #define EDMA_RX_IMR_NORMAL_MASK 0x1
  53 #define EDMA_TX_IMR_NORMAL_MASK 0x1
  54 #define EDMA_MISC_IMR_NORMAL_MASK 0x80001FFF
  55 #define EDMA_WOL_IMR_NORMAL_MASK 0x1
  56
  57 /* Edma receive consumer index */
  58 #define EDMA_REG_RX_SW_CONS_IDX_Q(x) (0x220 + ((x) << 2)) /* x is the queue id */
  59 /* Edma transmit consumer index */
  60 #define EDMA_REG_TX_SW_CONS_IDX_Q(x) (0x240 + ((x) << 2)) /* x is the queue id */
  61
  62 /* IRQ Moderator Initial Timer Register */
  63 #define EDMA_REG_IRQ_MODRT_TIMER_INIT 0x280
  64 #define EDMA_IRQ_MODRT_TIMER_MASK 0xFFFF
  65 #define EDMA_IRQ_MODRT_RX_TIMER_SHIFT 0
  66 #define EDMA_IRQ_MODRT_TX_TIMER_SHIFT 16
  67
  68 /* Interrupt Control Register */
  69 #define EDMA_REG_INTR_CTRL 0x284
  70 #define EDMA_INTR_CLR_TYP_SHIFT 0
  71 #define EDMA_INTR_SW_IDX_W_TYP_SHIFT 1
  72 #define EDMA_INTR_CLEAR_TYPE_W1 0
  73 #define EDMA_INTR_CLEAR_TYPE_R 1
  74
  75 /* RX Interrupt Mask Register */
  76 #define EDMA_REG_RX_INT_MASK_Q(x) (0x300 + ((x) << 2)) /* x = queue id */
  77
  78 /* TX Interrupt mask register */
  79 #define EDMA_REG_TX_INT_MASK_Q(x) (0x340 + ((x) << 2)) /* x = queue id */
  80
  81 /* Load Ptr Register
  82  * Software sets this bit after the initialization of the head and tail
  83  */
  84 #define EDMA_REG_TX_SRAM_PART 0x400
  85 #define EDMA_LOAD_PTR_SHIFT 16
  86
  87 /* TXQ Control Register */
  88 #define EDMA_REG_TXQ_CTRL 0x404
  89 #define EDMA_TXQ_CTRL_IP_OPTION_EN 0x10
  90 #define EDMA_TXQ_CTRL_TXQ_EN 0x20
  91 #define EDMA_TXQ_CTRL_ENH_MODE 0x40
  92 #define EDMA_TXQ_CTRL_LS_8023_EN 0x80
  93 #define EDMA_TXQ_CTRL_TPD_BURST_EN 0x100
  94 #define EDMA_TXQ_CTRL_LSO_BREAK_EN 0x200
  95 #define EDMA_TXQ_NUM_TPD_BURST_MASK 0xF
  96 #define EDMA_TXQ_TXF_BURST_NUM_MASK 0xFFFF
  97 #define EDMA_TXQ_NUM_TPD_BURST_SHIFT 0
  98 #define EDMA_TXQ_TXF_BURST_NUM_SHIFT 16
  99
 100 #define EDMA_REG_TXF_WATER_MARK 0x408 /* In 8-bytes */
 101 #define EDMA_TXF_WATER_MARK_MASK 0x0FFF
 102 #define EDMA_TXF_LOW_WATER_MARK_SHIFT 0
 103 #define EDMA_TXF_HIGH_WATER_MARK_SHIFT 16
 104 #define EDMA_TXQ_CTRL_BURST_MODE_EN 0x80000000
 105
 106 /* WRR Control Register */
 107 #define EDMA_REG_WRR_CTRL_Q0_Q3 0x40c
 108 #define EDMA_REG_WRR_CTRL_Q4_Q7 0x410
 109 #define EDMA_REG_WRR_CTRL_Q8_Q11 0x414
 110 #define EDMA_REG_WRR_CTRL_Q12_Q15 0x418
 111
 112 /* Weight round robin(WRR), it takes queue as input, and computes
 113  * starting bits where we need to write the weight for a particular
 114  * queue
 115  */
 116 #define EDMA_WRR_SHIFT(x) (((x) * 5) % 20)
 117
 118 /* Tx Descriptor Control Register */
 119 #define EDMA_REG_TPD_RING_SIZE 0x41C
 120 #define EDMA_TPD_RING_SIZE_SHIFT 0
 121 #define EDMA_TPD_RING_SIZE_MASK 0xFFFF
 122
 123 /* Transmit descriptor base address */
 124 #define EDMA_REG_TPD_BASE_ADDR_Q(x) (0x420 + ((x) << 2)) /* x = queue id */
 125
 126 /* TPD Index Register */
 127 #define EDMA_REG_TPD_IDX_Q(x) (0x460 + ((x) << 2)) /* x = queue id */
 128
 129 #define EDMA_TPD_PROD_IDX_BITS 0x0000FFFF
 130 #define EDMA_TPD_CONS_IDX_BITS 0xFFFF0000
 131 #define EDMA_TPD_PROD_IDX_MASK 0xFFFF
 132 #define EDMA_TPD_CONS_IDX_MASK 0xFFFF
 133 #define EDMA_TPD_PROD_IDX_SHIFT 0
 134 #define EDMA_TPD_CONS_IDX_SHIFT 16
 135
 136 /* TX Virtual Queue Mapping Control Register */
 137 #define EDMA_REG_VQ_CTRL0 0x4A0
 138 #define EDMA_REG_VQ_CTRL1 0x4A4
 139
 140 /* Virtual QID shift, it takes queue as input, and computes
 141  * Virtual QID position in virtual qid control register
 142  */
 143 #define EDMA_VQ_ID_SHIFT(i) (((i) * 3) % 24)
 144
 145 /* Virtual Queue Default Value */
 146 #define EDMA_VQ_REG_VALUE 0x240240
 147
 148 /* Tx side Port Interface Control Register */
 149 #define EDMA_REG_PORT_CTRL 0x4A8
 150 #define EDMA_PAD_EN_SHIFT 15
 151
 152 /* Tx side VLAN Configuration Register */
 153 #define EDMA_REG_VLAN_CFG 0x4AC
 154
 155 #define EDMA_TX_CVLAN 16
 156 #define EDMA_TX_INS_CVLAN 17
 157 #define EDMA_TX_CVLAN_TAG_SHIFT 0
 158
 159 #define EDMA_TX_SVLAN 14
 160 #define EDMA_TX_INS_SVLAN 15
 161 #define EDMA_TX_SVLAN_TAG_SHIFT 16
 162
 163 /* Tx Queue Packet Statistic Register */
 164 #define EDMA_REG_TX_STAT_PKT_Q(x) (0x700 + ((x) << 3)) /* x = queue id */
 165
 166 #define EDMA_TX_STAT_PKT_MASK 0xFFFFFF
 167
 168 /* Tx Queue Byte Statistic Register */
 169 #define EDMA_REG_TX_STAT_BYTE_Q(x) (0x704 + ((x) << 3)) /* x = queue id */
 170
 171 /* Load Balance Based Ring Offset Register */
 172 #define EDMA_REG_LB_RING 0x800
 173 #define EDMA_LB_RING_ENTRY_MASK 0xff
 174 #define EDMA_LB_RING_ID_MASK 0x7
 175 #define EDMA_LB_RING_PROFILE_ID_MASK 0x3
 176 #define EDMA_LB_RING_ENTRY_BIT_OFFSET 8
 177 #define EDMA_LB_RING_ID_OFFSET 0
 178 #define EDMA_LB_RING_PROFILE_ID_OFFSET 3
 179 #define EDMA_LB_REG_VALUE 0x6040200
 180
 181 /* Load Balance Priority Mapping Register */
 182 #define EDMA_REG_LB_PRI_START 0x804
 183 #define EDMA_REG_LB_PRI_END 0x810
 184 #define EDMA_LB_PRI_REG_INC 4
 185 #define EDMA_LB_PRI_ENTRY_BIT_OFFSET 4
 186 #define EDMA_LB_PRI_ENTRY_MASK 0xf
 187
 188 /* RSS Priority Mapping Register */
 189 #define EDMA_REG_RSS_PRI 0x820
 190 #define EDMA_RSS_PRI_ENTRY_MASK 0xf
 191 #define EDMA_RSS_RING_ID_MASK 0x7
 192 #define EDMA_RSS_PRI_ENTRY_BIT_OFFSET 4
 193
 194 /* RSS Indirection Register */
 195 #define EDMA_REG_RSS_IDT(x) (0x840 + ((x) << 2)) /* x = No. of indirection table */
 196 #define EDMA_NUM_IDT 16
 197 #define EDMA_RSS_IDT_VALUE 0x64206420
 198
 199 /* Default RSS Ring Register */
 200 #define EDMA_REG_DEF_RSS 0x890
 201 #define EDMA_DEF_RSS_MASK 0x7
 202
 203 /* RSS Hash Function Type Register */
 204 #define EDMA_REG_RSS_TYPE 0x894
 205 #define EDMA_RSS_TYPE_NONE 0x01
 206 #define EDMA_RSS_TYPE_IPV4TCP 0x02
 207 #define EDMA_RSS_TYPE_IPV6_TCP 0x04
 208 #define EDMA_RSS_TYPE_IPV4_UDP 0x08
 209 #define EDMA_RSS_TYPE_IPV6UDP 0x10
 210 #define EDMA_RSS_TYPE_IPV4 0x20
 211 #define EDMA_RSS_TYPE_IPV6 0x40
 212 #define EDMA_RSS_HASH_MODE_MASK 0x7f
 213
 214 #define EDMA_REG_RSS_HASH_VALUE 0x8C0
 215
 216 #define EDMA_REG_RSS_TYPE_RESULT 0x8C4
 217
 218 #define EDMA_HASH_TYPE_START 0
 219 #define EDMA_HASH_TYPE_END 5
 220 #define EDMA_HASH_TYPE_SHIFT 12
 221
 222 #define EDMA_RFS_FLOW_ENTRIES 1024
 223 #define EDMA_RFS_FLOW_ENTRIES_MASK (EDMA_RFS_FLOW_ENTRIES - 1)
 224 #define EDMA_RFS_EXPIRE_COUNT_PER_CALL 128
 225
 226 /* RFD Base Address Register */
 227 #define EDMA_REG_RFD_BASE_ADDR_Q(x) (0x950 + ((x) << 2)) /* x = queue id */
 228
 229 /* RFD Index Register */
 230 #define EDMA_REG_RFD_IDX_Q(x) (0x9B0 + ((x) << 2))
 231
 232 #define EDMA_RFD_PROD_IDX_BITS 0x00000FFF
 233 #define EDMA_RFD_CONS_IDX_BITS 0x0FFF0000
 234 #define EDMA_RFD_PROD_IDX_MASK 0xFFF
 235 #define EDMA_RFD_CONS_IDX_MASK 0xFFF
 236 #define EDMA_RFD_PROD_IDX_SHIFT 0
 237 #define EDMA_RFD_CONS_IDX_SHIFT 16
 238
 239 /* Rx Descriptor Control Register */
 240 #define EDMA_REG_RX_DESC0 0xA10
 241 #define EDMA_RFD_RING_SIZE_MASK 0xFFF
 242 #define EDMA_RX_BUF_SIZE_MASK 0xFFFF
 243 #define EDMA_RFD_RING_SIZE_SHIFT 0
 244 #define EDMA_RX_BUF_SIZE_SHIFT 16
 245
 246 #define EDMA_REG_RX_DESC1 0xA14
 247 #define EDMA_RXQ_RFD_BURST_NUM_MASK 0x3F
 248 #define EDMA_RXQ_RFD_PF_THRESH_MASK 0x1F
 249 #define EDMA_RXQ_RFD_LOW_THRESH_MASK 0xFFF
 250 #define EDMA_RXQ_RFD_BURST_NUM_SHIFT 0
 251 #define EDMA_RXQ_RFD_PF_THRESH_SHIFT 8
 252 #define EDMA_RXQ_RFD_LOW_THRESH_SHIFT 16
 253
 254 /* RXQ Control Register */
 255 #define EDMA_REG_RXQ_CTRL 0xA18
 256 #define EDMA_FIFO_THRESH_TYPE_SHIF 0
 257 #define EDMA_FIFO_THRESH_128_BYTE 0x0
 258 #define EDMA_FIFO_THRESH_64_BYTE 0x1
 259 #define EDMA_RXQ_CTRL_RMV_VLAN 0x00000002
 260 #define EDMA_RXQ_CTRL_EN 0x0000FF00
 261
 262 /* AXI Burst Size Config */
 263 #define EDMA_REG_AXIW_CTRL_MAXWRSIZE 0xA1C
 264 #define EDMA_AXIW_MAXWRSIZE_VALUE 0x0
 265
 266 /* Rx Statistics Register */
 267 #define EDMA_REG_RX_STAT_BYTE_Q(x) (0xA30 + ((x) << 2)) /* x = queue id */
 268 #define EDMA_REG_RX_STAT_PKT_Q(x) (0xA50 + ((x) << 2)) /* x = queue id */
 269
 270 /* WoL Pattern Length Register */
 271 #define EDMA_REG_WOL_PATTERN_LEN0 0xC00
 272 #define EDMA_WOL_PT_LEN_MASK 0xFF
 273 #define EDMA_WOL_PT0_LEN_SHIFT 0
 274 #define EDMA_WOL_PT1_LEN_SHIFT 8
 275 #define EDMA_WOL_PT2_LEN_SHIFT 16
 276 #define EDMA_WOL_PT3_LEN_SHIFT 24
 277
 278 #define EDMA_REG_WOL_PATTERN_LEN1 0xC04
 279 #define EDMA_WOL_PT4_LEN_SHIFT 0
 280 #define EDMA_WOL_PT5_LEN_SHIFT 8
 281 #define EDMA_WOL_PT6_LEN_SHIFT 16
 282
 283 /* WoL Control Register */
 284 #define EDMA_REG_WOL_CTRL 0xC08
 285 #define EDMA_WOL_WK_EN 0x00000001
 286 #define EDMA_WOL_MG_EN 0x00000002
 287 #define EDMA_WOL_PT0_EN 0x00000004
 288 #define EDMA_WOL_PT1_EN 0x00000008
 289 #define EDMA_WOL_PT2_EN 0x00000010
 290 #define EDMA_WOL_PT3_EN 0x00000020
 291 #define EDMA_WOL_PT4_EN 0x00000040
 292 #define EDMA_WOL_PT5_EN 0x00000080
 293 #define EDMA_WOL_PT6_EN 0x00000100
 294
 295 /* MAC Control Register */
 296 #define EDMA_REG_MAC_CTRL0 0xC20
 297 #define EDMA_REG_MAC_CTRL1 0xC24
 298
 299 /* WoL Pattern Register */
 300 #define EDMA_REG_WOL_PATTERN_START 0x5000
 301 #define EDMA_PATTERN_PART_REG_OFFSET 0x40
 302
 303
 304 /* TX descriptor fields */
 305 #define EDMA_TPD_HDR_SHIFT 0
 306 #define EDMA_TPD_PPPOE_EN 0x00000100
 307 #define EDMA_TPD_IP_CSUM_EN 0x00000200
 308 #define EDMA_TPD_TCP_CSUM_EN 0x0000400
 309 #define EDMA_TPD_UDP_CSUM_EN 0x00000800
 310 #define EDMA_TPD_CUSTOM_CSUM_EN 0x00000C00
 311 #define EDMA_TPD_LSO_EN 0x00001000
 312 #define EDMA_TPD_LSO_V2_EN 0x00002000
 313 #define EDMA_TPD_IPV4_EN 0x00010000
 314 #define EDMA_TPD_MSS_MASK 0x1FFF
 315 #define EDMA_TPD_MSS_SHIFT 18
 316 #define EDMA_TPD_CUSTOM_CSUM_SHIFT 18
 317
 318 /* RRD descriptor fields */
 319 #define EDMA_RRD_NUM_RFD_MASK 0x000F
 320 #define EDMA_RRD_SVLAN 0x8000
 321 #define EDMA_RRD_FLOW_COOKIE_MASK 0x07FF;
 322
 323 #define EDMA_RRD_PKT_SIZE_MASK 0x3FFF
 324 #define EDMA_RRD_CSUM_FAIL_MASK 0xC000
 325 #define EDMA_RRD_CVLAN 0x0001
 326 #define EDMA_RRD_DESC_VALID 0x8000
 327
 328 #define EDMA_RRD_PRIORITY_SHIFT 4
 329 #define EDMA_RRD_PRIORITY_MASK 0x7
 330 #define EDMA_RRD_PORT_TYPE_SHIFT 7
 331 #define EDMA_RRD_PORT_TYPE_MASK 0x1F
 332
 333 #define ESS_RGMII_CTRL          0x0004
 334
 335 /* Port status registers */
 336 #define ESS_PORT0_STATUS        0x007C
 337 #define ESS_PORT1_STATUS        0x0080
 338 #define ESS_PORT2_STATUS        0x0084
 339 #define ESS_PORT3_STATUS        0x0088
 340 #define ESS_PORT4_STATUS        0x008C
 341 #define ESS_PORT5_STATUS        0x0090
 342
 343 #define ESS_PORT_STATUS_HDX_FLOW_CTL    0x80
 344 #define ESS_PORT_STATUS_DUPLEX_MODE     0x40
 345 #define ESS_PORT_STATUS_RX_FLOW_EN      0x20
 346 #define ESS_PORT_STATUS_TX_FLOW_EN      0x10
 347 #define ESS_PORT_STATUS_RX_MAC_EN       0x08
 348 #define ESS_PORT_STATUS_TX_MAC_EN       0x04
 349 #define ESS_PORT_STATUS_SPEED_INV       0x03
 350 #define ESS_PORT_STATUS_SPEED_1000      0x02
 351 #define ESS_PORT_STATUS_SPEED_100       0x01
 352 #define ESS_PORT_STATUS_SPEED_10        0x00
 353
 354 #define ESS_PORT_1G_FDX      (ESS_PORT_STATUS_DUPLEX_MODE | ESS_PORT_STATUS_RX_FLOW_EN | \
 355                                ESS_PORT_STATUS_TX_FLOW_EN  | ESS_PORT_STATUS_RX_MAC_EN  | \
 356                                ESS_PORT_STATUS_TX_MAC_EN   | ESS_PORT_STATUS_SPEED_1000)
 357
 358 #define PHY_STATUS_REG                  0x11
 359 #define PHY_STATUS_SPEED                0xC000
 360 #define PHY_STATUS_SPEED_SHIFT          14
 361 #define PHY_STATUS_DUPLEX               0x2000
 362 #define PHY_STATUS_DUPLEX_SHIFT 13
 363 #define PHY_STATUS_SPEED_DUPLEX_RESOLVED 0x0800
 364 #define PHY_STATUS_CARRIER              0x0400
 365 #define PHY_STATUS_CARRIER_SHIFT        10
 366
 367 /* Port lookup control registers */
 368 #define ESS_PORT0_LOOKUP_CTRL   0x0660
 369 #define ESS_PORT1_LOOKUP_CTRL   0x066C
 370 #define ESS_PORT2_LOOKUP_CTRL   0x0678
 371 #define ESS_PORT3_LOOKUP_CTRL   0x0684
 372 #define ESS_PORT4_LOOKUP_CTRL   0x0690
 373 #define ESS_PORT5_LOOKUP_CTRL   0x069C
 374
 375 #define ESS_PORT0_HEADER_CTRL   0x009C
 376
 377 #define ESS_PORTS_ALL           0x3f
 378
 379 #define ESS_FWD_CTRL1           0x0624
 380 #define   ESS_FWD_CTRL1_UC_FLOOD                BITS(0, 7)
 381 #define   ESS_FWD_CTRL1_UC_FLOOD_S              0
 382 #define   ESS_FWD_CTRL1_MC_FLOOD                BITS(8, 7)
 383 #define   ESS_FWD_CTRL1_MC_FLOOD_S              8
 384 #define   ESS_FWD_CTRL1_BC_FLOOD                BITS(16, 7)
 385 #define   ESS_FWD_CTRL1_BC_FLOOD_S              16
 386 #define   ESS_FWD_CTRL1_IGMP                    BITS(24, 7)
 387 #define   ESS_FWD_CTRL1_IGMP_S                  24
 388
 389 #endif /* _ESS_EDMA_H_ */