target/linux/ipq40xx/files/drivers/net/ethernet/qualcomm/ipqess/ipqess.h

   1 // SPDX-License-Identifier: (GPL-2.0 OR ISC)
   2 /* Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved.
   3  * Copyright (c) 2017 - 2018, John Crispin <john@phrozen.org>
   4  * Copyright (c) 2018 - 2019, Christian Lamparter <chunkeey@gmail.com>
   5  * Copyright (c) 2020 - 2021, Gabor Juhos <j4g8y7@gmail.com>
   6  *
   7  * Permission to use, copy, modify, and/or distribute this software for
   8  * any purpose with or without fee is hereby granted, provided that the
   9  * above copyright notice and this permission notice appear in all copies.
  10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
  16  * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  */
  18
  19 #ifndef _IPQESS_H_
  20 #define _IPQESS_H_
  21
  22 #define IPQESS_NETDEV_QUEUES    4
  23
  24 #define IPQESS_TPD_EOP_SHIFT 31
  25
  26 #define IPQESS_PORT_ID_SHIFT 12
  27 #define IPQESS_PORT_ID_MASK 0x7
  28
  29 /* tpd word 3 bit 18-28 */
  30 #define IPQESS_TPD_PORT_BITMAP_SHIFT 18
  31
  32 #define IPQESS_TPD_FROM_CPU_SHIFT 25
  33
  34 #define IPQESS_RX_RING_SIZE 128
  35 #define IPQESS_RX_HEAD_BUFF_SIZE 1540
  36 #define IPQESS_TX_RING_SIZE 128
  37 #define IPQESS_MAX_RX_QUEUE 8
  38 #define IPQESS_MAX_TX_QUEUE 16
  39
  40
  41 /* Configurations */
  42 #define IPQESS_INTR_CLEAR_TYPE 0
  43 #define IPQESS_INTR_SW_IDX_W_TYPE 0
  44 #define IPQESS_FIFO_THRESH_TYPE 0
  45 #define IPQESS_RSS_TYPE 0
  46 #define IPQESS_RX_IMT 0x0020
  47 #define IPQESS_TX_IMT 0x0050
  48 #define IPQESS_TPD_BURST 5
  49 #define IPQESS_TXF_BURST 0x100
  50 #define IPQESS_RFD_BURST 8
  51 #define IPQESS_RFD_THR 16
  52 #define IPQESS_RFD_LTHR 0
  53
  54 /* Flags used in transmit direction */
  55 #define IPQESS_DESC_LAST 0x1
  56 #define IPQESS_DESC_SINGLE 0x2
  57 #define IPQESS_DESC_PAGE 0x4
  58
  59 struct ipqesstool_statistics {
  60         u32 tx_q0_pkt;
  61         u32 tx_q1_pkt;
  62         u32 tx_q2_pkt;
  63         u32 tx_q3_pkt;
  64         u32 tx_q4_pkt;
  65         u32 tx_q5_pkt;
  66         u32 tx_q6_pkt;
  67         u32 tx_q7_pkt;
  68         u32 tx_q8_pkt;
  69         u32 tx_q9_pkt;
  70         u32 tx_q10_pkt;
  71         u32 tx_q11_pkt;
  72         u32 tx_q12_pkt;
  73         u32 tx_q13_pkt;
  74         u32 tx_q14_pkt;
  75         u32 tx_q15_pkt;
  76         u32 tx_q0_byte;
  77         u32 tx_q1_byte;
  78         u32 tx_q2_byte;
  79         u32 tx_q3_byte;
  80         u32 tx_q4_byte;
  81         u32 tx_q5_byte;
  82         u32 tx_q6_byte;
  83         u32 tx_q7_byte;
  84         u32 tx_q8_byte;
  85         u32 tx_q9_byte;
  86         u32 tx_q10_byte;
  87         u32 tx_q11_byte;
  88         u32 tx_q12_byte;
  89         u32 tx_q13_byte;
  90         u32 tx_q14_byte;
  91         u32 tx_q15_byte;
  92         u32 rx_q0_pkt;
  93         u32 rx_q1_pkt;
  94         u32 rx_q2_pkt;
  95         u32 rx_q3_pkt;
  96         u32 rx_q4_pkt;
  97         u32 rx_q5_pkt;
  98         u32 rx_q6_pkt;
  99         u32 rx_q7_pkt;
 100         u32 rx_q0_byte;
 101         u32 rx_q1_byte;
 102         u32 rx_q2_byte;
 103         u32 rx_q3_byte;
 104         u32 rx_q4_byte;
 105         u32 rx_q5_byte;
 106         u32 rx_q6_byte;
 107         u32 rx_q7_byte;
 108         u32 tx_desc_error;
 109 };
 110
 111 struct ipqess_tx_desc {
 112         __le16  len;
 113         __le16  svlan_tag;
 114         __le32  word1;
 115         __le32  addr;
 116         __le32  word3;
 117 } __aligned(16) __packed;
 118
 119 struct ipqess_rx_desc {
 120         u16 rrd0;
 121         u16 rrd1;
 122         u16 rrd2;
 123         u16 rrd3;
 124         u16 rrd4;
 125         u16 rrd5;
 126         u16 rrd6;
 127         u16 rrd7;
 128 } __aligned(16) __packed;
 129
 130 struct ipqess_buf {
 131         struct sk_buff *skb;
 132         dma_addr_t dma;
 133         u32 flags;
 134         u16 length;
 135 };
 136
 137 struct ipqess_tx_ring {
 138         struct napi_struct napi_tx;
 139         u32 idx;
 140         int ring_id;
 141         struct ipqess *ess;
 142         struct netdev_queue *nq;
 143         struct ipqess_tx_desc *hw_desc;
 144         struct ipqess_buf *buf;
 145         dma_addr_t dma;
 146         u16 count;
 147         u16 head;
 148         u16 tail;
 149 };
 150
 151 struct ipqess_rx_ring {
 152         struct napi_struct napi_rx;
 153         u32 idx;
 154         int ring_id;
 155         struct ipqess *ess;
 156         struct device *ppdev;
 157         struct ipqess_rx_desc **hw_desc;
 158         struct ipqess_buf *buf;
 159         dma_addr_t dma;
 160         u16 head;
 161         u16 tail;
 162         atomic_t refill_count;
 163 };
 164
 165 struct ipqess_rx_ring_refill {
 166         struct ipqess_rx_ring *rx_ring;
 167         struct work_struct refill_work;
 168 };
 169
 170 #define IPQESS_IRQ_NAME_LEN     32
 171
 172 struct ipqess {
 173         struct net_device *netdev;
 174         void __iomem *hw_addr;
 175         struct clk *ess_clk;
 176         struct reset_control *ess_rst;
 177
 178         struct ipqess_rx_ring rx_ring[IPQESS_NETDEV_QUEUES];
 179
 180         struct platform_device *pdev;
 181         struct phylink *phylink;
 182         struct phylink_config phylink_config;
 183         struct ipqess_tx_ring tx_ring[IPQESS_NETDEV_QUEUES];
 184
 185         struct ipqesstool_statistics ipqessstats;
 186         spinlock_t stats_lock;
 187         struct net_device_stats stats;
 188
 189         struct ipqess_rx_ring_refill rx_refill[IPQESS_NETDEV_QUEUES];
 190         u32 tx_irq[IPQESS_MAX_TX_QUEUE];
 191         char tx_irq_names[IPQESS_MAX_TX_QUEUE][IPQESS_IRQ_NAME_LEN];
 192         u32 rx_irq[IPQESS_MAX_RX_QUEUE];
 193         char rx_irq_names[IPQESS_MAX_TX_QUEUE][IPQESS_IRQ_NAME_LEN];
 194 };
 195
 196 static inline void build_test(void)
 197 {
 198         struct ipqess *ess;
 199         BUILD_BUG_ON(ARRAY_SIZE(ess->rx_ring) != ARRAY_SIZE(ess->rx_refill));
 200 }
 201
 202 void ipqess_set_ethtool_ops(struct net_device *netdev);
 203 void ipqess_update_hw_stats(struct ipqess *ess);
 204
 205 /* register definition */
 206 #define IPQESS_REG_MAS_CTRL 0x0
 207 #define IPQESS_REG_TIMEOUT_CTRL 0x004
 208 #define IPQESS_REG_DBG0 0x008
 209 #define IPQESS_REG_DBG1 0x00C
 210 #define IPQESS_REG_SW_CTRL0 0x100
 211 #define IPQESS_REG_SW_CTRL1 0x104
 212
 213 /* Interrupt Status Register */
 214 #define IPQESS_REG_RX_ISR 0x200
 215 #define IPQESS_REG_TX_ISR 0x208
 216 #define IPQESS_REG_MISC_ISR 0x210
 217 #define IPQESS_REG_WOL_ISR 0x218
 218
 219 #define IPQESS_MISC_ISR_RX_URG_Q(x) (1 << x)
 220
 221 #define IPQESS_MISC_ISR_AXIR_TIMEOUT 0x00000100
 222 #define IPQESS_MISC_ISR_AXIR_ERR 0x00000200
 223 #define IPQESS_MISC_ISR_TXF_DEAD 0x00000400
 224 #define IPQESS_MISC_ISR_AXIW_ERR 0x00000800
 225 #define IPQESS_MISC_ISR_AXIW_TIMEOUT 0x00001000
 226
 227 #define IPQESS_WOL_ISR 0x00000001
 228
 229 /* Interrupt Mask Register */
 230 #define IPQESS_REG_MISC_IMR 0x214
 231 #define IPQESS_REG_WOL_IMR 0x218
 232
 233 #define IPQESS_RX_IMR_NORMAL_MASK 0x1
 234 #define IPQESS_TX_IMR_NORMAL_MASK 0x1
 235 #define IPQESS_MISC_IMR_NORMAL_MASK 0x80001FFF
 236 #define IPQESS_WOL_IMR_NORMAL_MASK 0x1
 237
 238 /* Edma receive consumer index */
 239 #define IPQESS_REG_RX_SW_CONS_IDX_Q(x) (0x220 + ((x) << 2)) /* x is the queue id */
 240
 241 /* Edma transmit consumer index */
 242 #define IPQESS_REG_TX_SW_CONS_IDX_Q(x) (0x240 + ((x) << 2)) /* x is the queue id */
 243
 244 /* IRQ Moderator Initial Timer Register */
 245 #define IPQESS_REG_IRQ_MODRT_TIMER_INIT 0x280
 246 #define IPQESS_IRQ_MODRT_TIMER_MASK 0xFFFF
 247 #define IPQESS_IRQ_MODRT_RX_TIMER_SHIFT 0
 248 #define IPQESS_IRQ_MODRT_TX_TIMER_SHIFT 16
 249
 250 /* Interrupt Control Register */
 251 #define IPQESS_REG_INTR_CTRL 0x284
 252 #define IPQESS_INTR_CLR_TYP_SHIFT 0
 253 #define IPQESS_INTR_SW_IDX_W_TYP_SHIFT 1
 254 #define IPQESS_INTR_CLEAR_TYPE_W1 0
 255 #define IPQESS_INTR_CLEAR_TYPE_R 1
 256
 257 /* RX Interrupt Mask Register */
 258 #define IPQESS_REG_RX_INT_MASK_Q(x) (0x300 + ((x) << 2)) /* x = queue id */
 259
 260 /* TX Interrupt mask register */
 261 #define IPQESS_REG_TX_INT_MASK_Q(x) (0x340 + ((x) << 2)) /* x = queue id */
 262
 263 /* Load Ptr Register
 264  * Software sets this bit after the initialization of the head and tail
 265  */
 266 #define IPQESS_REG_TX_SRAM_PART 0x400
 267 #define IPQESS_LOAD_PTR_SHIFT 16
 268
 269 /* TXQ Control Register */
 270 #define IPQESS_REG_TXQ_CTRL 0x404
 271 #define IPQESS_TXQ_CTRL_IP_OPTION_EN 0x10
 272 #define IPQESS_TXQ_CTRL_TXQ_EN 0x20
 273 #define IPQESS_TXQ_CTRL_ENH_MODE 0x40
 274 #define IPQESS_TXQ_CTRL_LS_8023_EN 0x80
 275 #define IPQESS_TXQ_CTRL_TPD_BURST_EN 0x100
 276 #define IPQESS_TXQ_CTRL_LSO_BREAK_EN 0x200
 277 #define IPQESS_TXQ_NUM_TPD_BURST_MASK 0xF
 278 #define IPQESS_TXQ_TXF_BURST_NUM_MASK 0xFFFF
 279 #define IPQESS_TXQ_NUM_TPD_BURST_SHIFT 0
 280 #define IPQESS_TXQ_TXF_BURST_NUM_SHIFT 16
 281
 282 #define IPQESS_REG_TXF_WATER_MARK 0x408 /* In 8-bytes */
 283 #define IPQESS_TXF_WATER_MARK_MASK 0x0FFF
 284 #define IPQESS_TXF_LOW_WATER_MARK_SHIFT 0
 285 #define IPQESS_TXF_HIGH_WATER_MARK_SHIFT 16
 286 #define IPQESS_TXQ_CTRL_BURST_MODE_EN 0x80000000
 287
 288 /* WRR Control Register */
 289 #define IPQESS_REG_WRR_CTRL_Q0_Q3 0x40c
 290 #define IPQESS_REG_WRR_CTRL_Q4_Q7 0x410
 291 #define IPQESS_REG_WRR_CTRL_Q8_Q11 0x414
 292 #define IPQESS_REG_WRR_CTRL_Q12_Q15 0x418
 293
 294 /* Weight round robin(WRR), it takes queue as input, and computes
 295  * starting bits where we need to write the weight for a particular
 296  * queue
 297  */
 298 #define IPQESS_WRR_SHIFT(x) (((x) * 5) % 20)
 299
 300 /* Tx Descriptor Control Register */
 301 #define IPQESS_REG_TPD_RING_SIZE 0x41C
 302 #define IPQESS_TPD_RING_SIZE_SHIFT 0
 303 #define IPQESS_TPD_RING_SIZE_MASK 0xFFFF
 304
 305 /* Transmit descriptor base address */
 306 #define IPQESS_REG_TPD_BASE_ADDR_Q(x) (0x420 + ((x) << 2)) /* x = queue id */
 307
 308 /* TPD Index Register */
 309 #define IPQESS_REG_TPD_IDX_Q(x) (0x460 + ((x) << 2)) /* x = queue id */
 310
 311 #define IPQESS_TPD_PROD_IDX_BITS 0x0000FFFF
 312 #define IPQESS_TPD_CONS_IDX_BITS 0xFFFF0000
 313 #define IPQESS_TPD_PROD_IDX_MASK 0xFFFF
 314 #define IPQESS_TPD_CONS_IDX_MASK 0xFFFF
 315 #define IPQESS_TPD_PROD_IDX_SHIFT 0
 316 #define IPQESS_TPD_CONS_IDX_SHIFT 16
 317
 318 /* TX Virtual Queue Mapping Control Register */
 319 #define IPQESS_REG_VQ_CTRL0 0x4A0
 320 #define IPQESS_REG_VQ_CTRL1 0x4A4
 321
 322 /* Virtual QID shift, it takes queue as input, and computes
 323  * Virtual QID position in virtual qid control register
 324  */
 325 #define IPQESS_VQ_ID_SHIFT(i) (((i) * 3) % 24)
 326
 327 /* Virtual Queue Default Value */
 328 #define IPQESS_VQ_REG_VALUE 0x240240
 329
 330 /* Tx side Port Interface Control Register */
 331 #define IPQESS_REG_PORT_CTRL 0x4A8
 332 #define IPQESS_PAD_EN_SHIFT 15
 333
 334 /* Tx side VLAN Configuration Register */
 335 #define IPQESS_REG_VLAN_CFG 0x4AC
 336
 337 #define IPQESS_VLAN_CFG_SVLAN_TPID_SHIFT 0
 338 #define IPQESS_VLAN_CFG_SVLAN_TPID_MASK 0xffff
 339 #define IPQESS_VLAN_CFG_CVLAN_TPID_SHIFT 16
 340 #define IPQESS_VLAN_CFG_CVLAN_TPID_MASK 0xffff
 341
 342 #define IPQESS_TX_CVLAN 16
 343 #define IPQESS_TX_INS_CVLAN 17
 344 #define IPQESS_TX_CVLAN_TAG_SHIFT 0
 345
 346 #define IPQESS_TX_SVLAN 14
 347 #define IPQESS_TX_INS_SVLAN 15
 348 #define IPQESS_TX_SVLAN_TAG_SHIFT 16
 349
 350 /* Tx Queue Packet Statistic Register */
 351 #define IPQESS_REG_TX_STAT_PKT_Q(x) (0x700 + ((x) << 3)) /* x = queue id */
 352
 353 #define IPQESS_TX_STAT_PKT_MASK 0xFFFFFF
 354
 355 /* Tx Queue Byte Statistic Register */
 356 #define IPQESS_REG_TX_STAT_BYTE_Q(x) (0x704 + ((x) << 3)) /* x = queue id */
 357
 358 /* Load Balance Based Ring Offset Register */
 359 #define IPQESS_REG_LB_RING 0x800
 360 #define IPQESS_LB_RING_ENTRY_MASK 0xff
 361 #define IPQESS_LB_RING_ID_MASK 0x7
 362 #define IPQESS_LB_RING_PROFILE_ID_MASK 0x3
 363 #define IPQESS_LB_RING_ENTRY_BIT_OFFSET 8
 364 #define IPQESS_LB_RING_ID_OFFSET 0
 365 #define IPQESS_LB_RING_PROFILE_ID_OFFSET 3
 366 #define IPQESS_LB_REG_VALUE 0x6040200
 367
 368 /* Load Balance Priority Mapping Register */
 369 #define IPQESS_REG_LB_PRI_START 0x804
 370 #define IPQESS_REG_LB_PRI_END 0x810
 371 #define IPQESS_LB_PRI_REG_INC 4
 372 #define IPQESS_LB_PRI_ENTRY_BIT_OFFSET 4
 373 #define IPQESS_LB_PRI_ENTRY_MASK 0xf
 374
 375 /* RSS Priority Mapping Register */
 376 #define IPQESS_REG_RSS_PRI 0x820
 377 #define IPQESS_RSS_PRI_ENTRY_MASK 0xf
 378 #define IPQESS_RSS_RING_ID_MASK 0x7
 379 #define IPQESS_RSS_PRI_ENTRY_BIT_OFFSET 4
 380
 381 /* RSS Indirection Register */
 382 #define IPQESS_REG_RSS_IDT(x) (0x840 + ((x) << 2)) /* x = No. of indirection table */
 383 #define IPQESS_NUM_IDT 16
 384 #define IPQESS_RSS_IDT_VALUE 0x64206420
 385
 386 /* Default RSS Ring Register */
 387 #define IPQESS_REG_DEF_RSS 0x890
 388 #define IPQESS_DEF_RSS_MASK 0x7
 389
 390 /* RSS Hash Function Type Register */
 391 #define IPQESS_REG_RSS_TYPE 0x894
 392 #define IPQESS_RSS_TYPE_NONE 0x01
 393 #define IPQESS_RSS_TYPE_IPV4TCP 0x02
 394 #define IPQESS_RSS_TYPE_IPV6_TCP 0x04
 395 #define IPQESS_RSS_TYPE_IPV4_UDP 0x08
 396 #define IPQESS_RSS_TYPE_IPV6UDP 0x10
 397 #define IPQESS_RSS_TYPE_IPV4 0x20
 398 #define IPQESS_RSS_TYPE_IPV6 0x40
 399 #define IPQESS_RSS_HASH_MODE_MASK 0x7f
 400
 401 #define IPQESS_REG_RSS_HASH_VALUE 0x8C0
 402
 403 #define IPQESS_REG_RSS_TYPE_RESULT 0x8C4
 404
 405 #define IPQESS_HASH_TYPE_START 0
 406 #define IPQESS_HASH_TYPE_END 5
 407 #define IPQESS_HASH_TYPE_SHIFT 12
 408
 409 #define IPQESS_RFS_FLOW_ENTRIES 1024
 410 #define IPQESS_RFS_FLOW_ENTRIES_MASK (IPQESS_RFS_FLOW_ENTRIES - 1)
 411 #define IPQESS_RFS_EXPIRE_COUNT_PER_CALL 128
 412
 413 /* RFD Base Address Register */
 414 #define IPQESS_REG_RFD_BASE_ADDR_Q(x) (0x950 + ((x) << 2)) /* x = queue id */
 415
 416 /* RFD Index Register */
 417 #define IPQESS_REG_RFD_IDX_Q(x) (0x9B0 + ((x) << 2)) /* x = queue id */
 418
 419 #define IPQESS_RFD_PROD_IDX_BITS 0x00000FFF
 420 #define IPQESS_RFD_CONS_IDX_BITS 0x0FFF0000
 421 #define IPQESS_RFD_PROD_IDX_MASK 0xFFF
 422 #define IPQESS_RFD_CONS_IDX_MASK 0xFFF
 423 #define IPQESS_RFD_PROD_IDX_SHIFT 0
 424 #define IPQESS_RFD_CONS_IDX_SHIFT 16
 425
 426 /* Rx Descriptor Control Register */
 427 #define IPQESS_REG_RX_DESC0 0xA10
 428 #define IPQESS_RFD_RING_SIZE_MASK 0xFFF
 429 #define IPQESS_RX_BUF_SIZE_MASK 0xFFFF
 430 #define IPQESS_RFD_RING_SIZE_SHIFT 0
 431 #define IPQESS_RX_BUF_SIZE_SHIFT 16
 432
 433 #define IPQESS_REG_RX_DESC1 0xA14
 434 #define IPQESS_RXQ_RFD_BURST_NUM_MASK 0x3F
 435 #define IPQESS_RXQ_RFD_PF_THRESH_MASK 0x1F
 436 #define IPQESS_RXQ_RFD_LOW_THRESH_MASK 0xFFF
 437 #define IPQESS_RXQ_RFD_BURST_NUM_SHIFT 0
 438 #define IPQESS_RXQ_RFD_PF_THRESH_SHIFT 8
 439 #define IPQESS_RXQ_RFD_LOW_THRESH_SHIFT 16
 440
 441 /* RXQ Control Register */
 442 #define IPQESS_REG_RXQ_CTRL 0xA18
 443 #define IPQESS_FIFO_THRESH_TYPE_SHIF 0
 444 #define IPQESS_FIFO_THRESH_128_BYTE 0x0
 445 #define IPQESS_FIFO_THRESH_64_BYTE 0x1
 446 #define IPQESS_RXQ_CTRL_RMV_VLAN 0x00000002
 447 #define IPQESS_RXQ_CTRL_EN_MASK                 GENMASK(15, 8)
 448 #define IPQESS_RXQ_CTRL_EN(__qid)               BIT(8 + (__qid))
 449
 450 /* AXI Burst Size Config */
 451 #define IPQESS_REG_AXIW_CTRL_MAXWRSIZE 0xA1C
 452 #define IPQESS_AXIW_MAXWRSIZE_VALUE 0x0
 453
 454 /* Rx Statistics Register */
 455 #define IPQESS_REG_RX_STAT_BYTE_Q(x) (0xA30 + ((x) << 2)) /* x = queue id */
 456 #define IPQESS_REG_RX_STAT_PKT_Q(x) (0xA50 + ((x) << 2)) /* x = queue id */
 457
 458 /* WoL Pattern Length Register */
 459 #define IPQESS_REG_WOL_PATTERN_LEN0 0xC00
 460 #define IPQESS_WOL_PT_LEN_MASK 0xFF
 461 #define IPQESS_WOL_PT0_LEN_SHIFT 0
 462 #define IPQESS_WOL_PT1_LEN_SHIFT 8
 463 #define IPQESS_WOL_PT2_LEN_SHIFT 16
 464 #define IPQESS_WOL_PT3_LEN_SHIFT 24
 465
 466 #define IPQESS_REG_WOL_PATTERN_LEN1 0xC04
 467 #define IPQESS_WOL_PT4_LEN_SHIFT 0
 468 #define IPQESS_WOL_PT5_LEN_SHIFT 8
 469 #define IPQESS_WOL_PT6_LEN_SHIFT 16
 470
 471 /* WoL Control Register */
 472 #define IPQESS_REG_WOL_CTRL 0xC08
 473 #define IPQESS_WOL_WK_EN 0x00000001
 474 #define IPQESS_WOL_MG_EN 0x00000002
 475 #define IPQESS_WOL_PT0_EN 0x00000004
 476 #define IPQESS_WOL_PT1_EN 0x00000008
 477 #define IPQESS_WOL_PT2_EN 0x00000010
 478 #define IPQESS_WOL_PT3_EN 0x00000020
 479 #define IPQESS_WOL_PT4_EN 0x00000040
 480 #define IPQESS_WOL_PT5_EN 0x00000080
 481 #define IPQESS_WOL_PT6_EN 0x00000100
 482
 483 /* MAC Control Register */
 484 #define IPQESS_REG_MAC_CTRL0 0xC20
 485 #define IPQESS_REG_MAC_CTRL1 0xC24
 486
 487 /* WoL Pattern Register */
 488 #define IPQESS_REG_WOL_PATTERN_START 0x5000
 489 #define IPQESS_PATTERN_PART_REG_OFFSET 0x40
 490
 491
 492 /* TX descriptor fields */
 493 #define IPQESS_TPD_HDR_SHIFT 0
 494 #define IPQESS_TPD_PPPOE_EN 0x00000100
 495 #define IPQESS_TPD_IP_CSUM_EN 0x00000200
 496 #define IPQESS_TPD_TCP_CSUM_EN 0x0000400
 497 #define IPQESS_TPD_UDP_CSUM_EN 0x00000800
 498 #define IPQESS_TPD_CUSTOM_CSUM_EN 0x00000C00
 499 #define IPQESS_TPD_LSO_EN 0x00001000
 500 #define IPQESS_TPD_LSO_V2_EN 0x00002000
 501 /* The VLAN_TAGGED bit is not used in the publicly available
 502  * drivers. The definition has been stolen from the Atheros
 503  * 'alx' driver (drivers/net/ethernet/atheros/alx/hw.h). It
 504  * seems that it has the same meaning in regard to the EDMA
 505  * hardware.
 506  */
 507 #define IPQESS_TPD_VLAN_TAGGED 0x00004000
 508 #define IPQESS_TPD_IPV4_EN 0x00010000
 509 #define IPQESS_TPD_MSS_MASK 0x1FFF
 510 #define IPQESS_TPD_MSS_SHIFT 18
 511 #define IPQESS_TPD_CUSTOM_CSUM_SHIFT 18
 512
 513 /* RRD descriptor fields */
 514 #define IPQESS_RRD_NUM_RFD_MASK 0x000F
 515 #define IPQESS_RRD_PKT_SIZE_MASK 0x3FFF
 516 #define IPQESS_RRD_SRC_PORT_NUM_MASK 0x4000
 517 #define IPQESS_RRD_SVLAN 0x8000
 518 #define IPQESS_RRD_FLOW_COOKIE_MASK 0x07FF;
 519
 520 #define IPQESS_RRD_PKT_SIZE_MASK 0x3FFF
 521 #define IPQESS_RRD_CSUM_FAIL_MASK 0xC000
 522 #define IPQESS_RRD_CVLAN 0x0001
 523 #define IPQESS_RRD_DESC_VALID 0x8000
 524
 525 #define IPQESS_RRD_PRIORITY_SHIFT 4
 526 #define IPQESS_RRD_PRIORITY_MASK 0x7
 527 #define IPQESS_RRD_PORT_TYPE_SHIFT 7
 528 #define IPQESS_RRD_PORT_TYPE_MASK 0x1F
 529
 530 #endif