2 * Copyright (c) 2016, The Linux Foundation. All rights reserved.
4 * Permission to use, copy, modify, and/or distribute this software for
5 * any purpose with or without fee is hereby granted, provided that the
6 * above copyright notice and this permission notice appear in all copies.
7 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
8 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
9 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
10 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
11 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
12 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
13 * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 #include <linux/module.h>
17 #include <linux/list.h>
18 #include <linux/bitops.h>
19 #include <linux/switch.h>
20 #include <linux/delay.h>
21 #include <linux/phy.h>
22 #include <linux/clk.h>
23 #include <linux/reset.h>
24 #include <linux/lockdep.h>
25 #include <linux/workqueue.h>
26 #include <linux/of_device.h>
27 #include <linux/of_address.h>
28 #include <linux/of_mdio.h>
29 #include <linux/mdio.h>
30 #include <linux/gpio.h>
34 static struct ar40xx_priv
*ar40xx_priv
;
36 #define MIB_DESC(_s , _o, _n) \
43 static const struct ar40xx_mib_desc ar40xx_mibs
[] = {
44 MIB_DESC(1, AR40XX_STATS_RXBROAD
, "RxBroad"),
45 MIB_DESC(1, AR40XX_STATS_RXPAUSE
, "RxPause"),
46 MIB_DESC(1, AR40XX_STATS_RXMULTI
, "RxMulti"),
47 MIB_DESC(1, AR40XX_STATS_RXFCSERR
, "RxFcsErr"),
48 MIB_DESC(1, AR40XX_STATS_RXALIGNERR
, "RxAlignErr"),
49 MIB_DESC(1, AR40XX_STATS_RXRUNT
, "RxRunt"),
50 MIB_DESC(1, AR40XX_STATS_RXFRAGMENT
, "RxFragment"),
51 MIB_DESC(1, AR40XX_STATS_RX64BYTE
, "Rx64Byte"),
52 MIB_DESC(1, AR40XX_STATS_RX128BYTE
, "Rx128Byte"),
53 MIB_DESC(1, AR40XX_STATS_RX256BYTE
, "Rx256Byte"),
54 MIB_DESC(1, AR40XX_STATS_RX512BYTE
, "Rx512Byte"),
55 MIB_DESC(1, AR40XX_STATS_RX1024BYTE
, "Rx1024Byte"),
56 MIB_DESC(1, AR40XX_STATS_RX1518BYTE
, "Rx1518Byte"),
57 MIB_DESC(1, AR40XX_STATS_RXMAXBYTE
, "RxMaxByte"),
58 MIB_DESC(1, AR40XX_STATS_RXTOOLONG
, "RxTooLong"),
59 MIB_DESC(2, AR40XX_STATS_RXGOODBYTE
, "RxGoodByte"),
60 MIB_DESC(2, AR40XX_STATS_RXBADBYTE
, "RxBadByte"),
61 MIB_DESC(1, AR40XX_STATS_RXOVERFLOW
, "RxOverFlow"),
62 MIB_DESC(1, AR40XX_STATS_FILTERED
, "Filtered"),
63 MIB_DESC(1, AR40XX_STATS_TXBROAD
, "TxBroad"),
64 MIB_DESC(1, AR40XX_STATS_TXPAUSE
, "TxPause"),
65 MIB_DESC(1, AR40XX_STATS_TXMULTI
, "TxMulti"),
66 MIB_DESC(1, AR40XX_STATS_TXUNDERRUN
, "TxUnderRun"),
67 MIB_DESC(1, AR40XX_STATS_TX64BYTE
, "Tx64Byte"),
68 MIB_DESC(1, AR40XX_STATS_TX128BYTE
, "Tx128Byte"),
69 MIB_DESC(1, AR40XX_STATS_TX256BYTE
, "Tx256Byte"),
70 MIB_DESC(1, AR40XX_STATS_TX512BYTE
, "Tx512Byte"),
71 MIB_DESC(1, AR40XX_STATS_TX1024BYTE
, "Tx1024Byte"),
72 MIB_DESC(1, AR40XX_STATS_TX1518BYTE
, "Tx1518Byte"),
73 MIB_DESC(1, AR40XX_STATS_TXMAXBYTE
, "TxMaxByte"),
74 MIB_DESC(1, AR40XX_STATS_TXOVERSIZE
, "TxOverSize"),
75 MIB_DESC(2, AR40XX_STATS_TXBYTE
, "TxByte"),
76 MIB_DESC(1, AR40XX_STATS_TXCOLLISION
, "TxCollision"),
77 MIB_DESC(1, AR40XX_STATS_TXABORTCOL
, "TxAbortCol"),
78 MIB_DESC(1, AR40XX_STATS_TXMULTICOL
, "TxMultiCol"),
79 MIB_DESC(1, AR40XX_STATS_TXSINGLECOL
, "TxSingleCol"),
80 MIB_DESC(1, AR40XX_STATS_TXEXCDEFER
, "TxExcDefer"),
81 MIB_DESC(1, AR40XX_STATS_TXDEFER
, "TxDefer"),
82 MIB_DESC(1, AR40XX_STATS_TXLATECOL
, "TxLateCol"),
86 ar40xx_read(struct ar40xx_priv
*priv
, int reg
)
88 return readl(priv
->hw_addr
+ reg
);
92 ar40xx_psgmii_read(struct ar40xx_priv
*priv
, int reg
)
94 return readl(priv
->psgmii_hw_addr
+ reg
);
98 ar40xx_write(struct ar40xx_priv
*priv
, int reg
, u32 val
)
100 writel(val
, priv
->hw_addr
+ reg
);
104 ar40xx_rmw(struct ar40xx_priv
*priv
, int reg
, u32 mask
, u32 val
)
108 ret
= ar40xx_read(priv
, reg
);
111 ar40xx_write(priv
, reg
, ret
);
116 ar40xx_psgmii_write(struct ar40xx_priv
*priv
, int reg
, u32 val
)
118 writel(val
, priv
->psgmii_hw_addr
+ reg
);
122 ar40xx_phy_dbg_write(struct ar40xx_priv
*priv
, int phy_addr
,
123 u16 dbg_addr
, u16 dbg_data
)
125 struct mii_bus
*bus
= priv
->mii_bus
;
127 mutex_lock(&bus
->mdio_lock
);
128 bus
->write(bus
, phy_addr
, AR40XX_MII_ATH_DBG_ADDR
, dbg_addr
);
129 bus
->write(bus
, phy_addr
, AR40XX_MII_ATH_DBG_DATA
, dbg_data
);
130 mutex_unlock(&bus
->mdio_lock
);
134 ar40xx_phy_dbg_read(struct ar40xx_priv
*priv
, int phy_addr
,
135 u16 dbg_addr
, u16
*dbg_data
)
137 struct mii_bus
*bus
= priv
->mii_bus
;
139 mutex_lock(&bus
->mdio_lock
);
140 bus
->write(bus
, phy_addr
, AR40XX_MII_ATH_DBG_ADDR
, dbg_addr
);
141 *dbg_data
= bus
->read(bus
, phy_addr
, AR40XX_MII_ATH_DBG_DATA
);
142 mutex_unlock(&bus
->mdio_lock
);
146 ar40xx_phy_mmd_write(struct ar40xx_priv
*priv
, u32 phy_id
,
147 u16 mmd_num
, u16 reg_id
, u16 reg_val
)
149 struct mii_bus
*bus
= priv
->mii_bus
;
151 mutex_lock(&bus
->mdio_lock
);
152 bus
->write(bus
, phy_id
,
153 AR40XX_MII_ATH_MMD_ADDR
, mmd_num
);
154 bus
->write(bus
, phy_id
,
155 AR40XX_MII_ATH_MMD_DATA
, reg_id
);
156 bus
->write(bus
, phy_id
,
157 AR40XX_MII_ATH_MMD_ADDR
,
159 bus
->write(bus
, phy_id
,
160 AR40XX_MII_ATH_MMD_DATA
, reg_val
);
161 mutex_unlock(&bus
->mdio_lock
);
165 ar40xx_phy_mmd_read(struct ar40xx_priv
*priv
, u32 phy_id
,
166 u16 mmd_num
, u16 reg_id
)
169 struct mii_bus
*bus
= priv
->mii_bus
;
171 mutex_lock(&bus
->mdio_lock
);
172 bus
->write(bus
, phy_id
,
173 AR40XX_MII_ATH_MMD_ADDR
, mmd_num
);
174 bus
->write(bus
, phy_id
,
175 AR40XX_MII_ATH_MMD_DATA
, reg_id
);
176 bus
->write(bus
, phy_id
,
177 AR40XX_MII_ATH_MMD_ADDR
,
179 value
= bus
->read(bus
, phy_id
, AR40XX_MII_ATH_MMD_DATA
);
180 mutex_unlock(&bus
->mdio_lock
);
184 /* Start of swconfig support */
187 ar40xx_phy_poll_reset(struct ar40xx_priv
*priv
)
189 u32 i
, in_reset
, retries
= 500;
190 struct mii_bus
*bus
= priv
->mii_bus
;
192 /* Assume RESET was recently issued to some or all of the phys */
193 in_reset
= GENMASK(AR40XX_NUM_PHYS
- 1, 0);
196 /* 1ms should be plenty of time.
197 * 802.3 spec allows for a max wait time of 500ms
199 usleep_range(1000, 2000);
201 for (i
= 0; i
< AR40XX_NUM_PHYS
; i
++) {
204 /* skip devices which have completed reset */
205 if (!(in_reset
& BIT(i
)))
208 val
= mdiobus_read(bus
, i
, MII_BMCR
);
212 /* mark when phy is no longer in reset state */
213 if (!(val
& BMCR_RESET
))
221 dev_warn(&bus
->dev
, "Failed to reset all phys! (in_reset: 0x%x)\n",
226 ar40xx_phy_init(struct ar40xx_priv
*priv
)
233 for (i
= 0; i
< AR40XX_NUM_PORTS
- 1; i
++) {
234 ar40xx_phy_dbg_read(priv
, i
, AR40XX_PHY_DEBUG_0
, &val
);
235 val
&= ~AR40XX_PHY_MANU_CTRL_EN
;
236 ar40xx_phy_dbg_write(priv
, i
, AR40XX_PHY_DEBUG_0
, val
);
237 mdiobus_write(bus
, i
,
238 MII_ADVERTISE
, ADVERTISE_ALL
|
239 ADVERTISE_PAUSE_CAP
|
240 ADVERTISE_PAUSE_ASYM
);
241 mdiobus_write(bus
, i
, MII_CTRL1000
, ADVERTISE_1000FULL
);
242 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
245 ar40xx_phy_poll_reset(priv
);
249 ar40xx_port_phy_linkdown(struct ar40xx_priv
*priv
)
256 for (i
= 0; i
< AR40XX_NUM_PORTS
- 1; i
++) {
257 mdiobus_write(bus
, i
, MII_CTRL1000
, 0);
258 mdiobus_write(bus
, i
, MII_ADVERTISE
, 0);
259 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
260 ar40xx_phy_dbg_read(priv
, i
, AR40XX_PHY_DEBUG_0
, &val
);
261 val
|= AR40XX_PHY_MANU_CTRL_EN
;
262 ar40xx_phy_dbg_write(priv
, i
, AR40XX_PHY_DEBUG_0
, val
);
263 /* disable transmit */
264 ar40xx_phy_dbg_read(priv
, i
, AR40XX_PHY_DEBUG_2
, &val
);
266 ar40xx_phy_dbg_write(priv
, i
, AR40XX_PHY_DEBUG_2
, val
);
271 ar40xx_set_mirror_regs(struct ar40xx_priv
*priv
)
275 /* reset all mirror registers */
276 ar40xx_rmw(priv
, AR40XX_REG_FWD_CTRL0
,
277 AR40XX_FWD_CTRL0_MIRROR_PORT
,
278 (0xF << AR40XX_FWD_CTRL0_MIRROR_PORT_S
));
279 for (port
= 0; port
< AR40XX_NUM_PORTS
; port
++) {
280 ar40xx_rmw(priv
, AR40XX_REG_PORT_LOOKUP(port
),
281 AR40XX_PORT_LOOKUP_ING_MIRROR_EN
, 0);
283 ar40xx_rmw(priv
, AR40XX_REG_PORT_HOL_CTRL1(port
),
284 AR40XX_PORT_HOL_CTRL1_EG_MIRROR_EN
, 0);
287 /* now enable mirroring if necessary */
288 if (priv
->source_port
>= AR40XX_NUM_PORTS
||
289 priv
->monitor_port
>= AR40XX_NUM_PORTS
||
290 priv
->source_port
== priv
->monitor_port
) {
294 ar40xx_rmw(priv
, AR40XX_REG_FWD_CTRL0
,
295 AR40XX_FWD_CTRL0_MIRROR_PORT
,
296 (priv
->monitor_port
<< AR40XX_FWD_CTRL0_MIRROR_PORT_S
));
299 ar40xx_rmw(priv
, AR40XX_REG_PORT_LOOKUP(priv
->source_port
), 0,
300 AR40XX_PORT_LOOKUP_ING_MIRROR_EN
);
303 ar40xx_rmw(priv
, AR40XX_REG_PORT_HOL_CTRL1(priv
->source_port
),
304 0, AR40XX_PORT_HOL_CTRL1_EG_MIRROR_EN
);
308 ar40xx_sw_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
310 struct ar40xx_priv
*priv
= swdev_to_ar40xx(dev
);
311 u8 ports
= priv
->vlan_table
[val
->port_vlan
];
315 for (i
= 0; i
< dev
->ports
; i
++) {
316 struct switch_port
*p
;
318 if (!(ports
& BIT(i
)))
321 p
= &val
->value
.ports
[val
->len
++];
323 if ((priv
->vlan_tagged
& BIT(i
)) ||
324 (priv
->pvid
[i
] != val
->port_vlan
))
325 p
->flags
= BIT(SWITCH_PORT_FLAG_TAGGED
);
333 ar40xx_sw_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
335 struct ar40xx_priv
*priv
= swdev_to_ar40xx(dev
);
336 u8
*vt
= &priv
->vlan_table
[val
->port_vlan
];
340 for (i
= 0; i
< val
->len
; i
++) {
341 struct switch_port
*p
= &val
->value
.ports
[i
];
343 if (p
->flags
& BIT(SWITCH_PORT_FLAG_TAGGED
)) {
344 if (val
->port_vlan
== priv
->pvid
[p
->id
])
345 priv
->vlan_tagged
|= BIT(p
->id
);
347 priv
->vlan_tagged
&= ~BIT(p
->id
);
348 priv
->pvid
[p
->id
] = val
->port_vlan
;
357 ar40xx_reg_wait(struct ar40xx_priv
*priv
, u32 reg
, u32 mask
, u32 val
,
362 for (i
= 0; i
< timeout
; i
++) {
365 t
= ar40xx_read(priv
, reg
);
366 if ((t
& mask
) == val
)
369 usleep_range(1000, 2000);
376 ar40xx_mib_op(struct ar40xx_priv
*priv
, u32 op
)
380 lockdep_assert_held(&priv
->mib_lock
);
382 /* Capture the hardware statistics for all ports */
383 ar40xx_rmw(priv
, AR40XX_REG_MIB_FUNC
,
384 AR40XX_MIB_FUNC
, (op
<< AR40XX_MIB_FUNC_S
));
386 /* Wait for the capturing to complete. */
387 ret
= ar40xx_reg_wait(priv
, AR40XX_REG_MIB_FUNC
,
388 AR40XX_MIB_BUSY
, 0, 10);
394 ar40xx_mib_fetch_port_stat(struct ar40xx_priv
*priv
, int port
, bool flush
)
399 u32 num_mibs
= ARRAY_SIZE(ar40xx_mibs
);
401 WARN_ON(port
>= priv
->dev
.ports
);
403 lockdep_assert_held(&priv
->mib_lock
);
405 base
= AR40XX_REG_PORT_STATS_START
+
406 AR40XX_REG_PORT_STATS_LEN
* port
;
408 mib_stats
= &priv
->mib_stats
[port
* num_mibs
];
412 len
= num_mibs
* sizeof(*mib_stats
);
413 memset(mib_stats
, 0, len
);
416 for (i
= 0; i
< num_mibs
; i
++) {
417 const struct ar40xx_mib_desc
*mib
;
420 mib
= &ar40xx_mibs
[i
];
421 t
= ar40xx_read(priv
, base
+ mib
->offset
);
422 if (mib
->size
== 2) {
425 hi
= ar40xx_read(priv
, base
+ mib
->offset
+ 4);
434 ar40xx_mib_capture(struct ar40xx_priv
*priv
)
436 return ar40xx_mib_op(priv
, AR40XX_MIB_FUNC_CAPTURE
);
440 ar40xx_mib_flush(struct ar40xx_priv
*priv
)
442 return ar40xx_mib_op(priv
, AR40XX_MIB_FUNC_FLUSH
);
446 ar40xx_sw_set_reset_mibs(struct switch_dev
*dev
,
447 const struct switch_attr
*attr
,
448 struct switch_val
*val
)
450 struct ar40xx_priv
*priv
= swdev_to_ar40xx(dev
);
453 u32 num_mibs
= ARRAY_SIZE(ar40xx_mibs
);
455 mutex_lock(&priv
->mib_lock
);
457 len
= priv
->dev
.ports
* num_mibs
* sizeof(*priv
->mib_stats
);
458 memset(priv
->mib_stats
, 0, len
);
459 ret
= ar40xx_mib_flush(priv
);
461 mutex_unlock(&priv
->mib_lock
);
466 ar40xx_sw_set_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
467 struct switch_val
*val
)
469 struct ar40xx_priv
*priv
= swdev_to_ar40xx(dev
);
471 priv
->vlan
= !!val
->value
.i
;
476 ar40xx_sw_get_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
477 struct switch_val
*val
)
479 struct ar40xx_priv
*priv
= swdev_to_ar40xx(dev
);
481 val
->value
.i
= priv
->vlan
;
486 ar40xx_sw_set_mirror_rx_enable(struct switch_dev
*dev
,
487 const struct switch_attr
*attr
,
488 struct switch_val
*val
)
490 struct ar40xx_priv
*priv
= swdev_to_ar40xx(dev
);
492 mutex_lock(&priv
->reg_mutex
);
493 priv
->mirror_rx
= !!val
->value
.i
;
494 ar40xx_set_mirror_regs(priv
);
495 mutex_unlock(&priv
->reg_mutex
);
501 ar40xx_sw_get_mirror_rx_enable(struct switch_dev
*dev
,
502 const struct switch_attr
*attr
,
503 struct switch_val
*val
)
505 struct ar40xx_priv
*priv
= swdev_to_ar40xx(dev
);
507 mutex_lock(&priv
->reg_mutex
);
508 val
->value
.i
= priv
->mirror_rx
;
509 mutex_unlock(&priv
->reg_mutex
);
514 ar40xx_sw_set_mirror_tx_enable(struct switch_dev
*dev
,
515 const struct switch_attr
*attr
,
516 struct switch_val
*val
)
518 struct ar40xx_priv
*priv
= swdev_to_ar40xx(dev
);
520 mutex_lock(&priv
->reg_mutex
);
521 priv
->mirror_tx
= !!val
->value
.i
;
522 ar40xx_set_mirror_regs(priv
);
523 mutex_unlock(&priv
->reg_mutex
);
529 ar40xx_sw_get_mirror_tx_enable(struct switch_dev
*dev
,
530 const struct switch_attr
*attr
,
531 struct switch_val
*val
)
533 struct ar40xx_priv
*priv
= swdev_to_ar40xx(dev
);
535 mutex_lock(&priv
->reg_mutex
);
536 val
->value
.i
= priv
->mirror_tx
;
537 mutex_unlock(&priv
->reg_mutex
);
542 ar40xx_sw_set_mirror_monitor_port(struct switch_dev
*dev
,
543 const struct switch_attr
*attr
,
544 struct switch_val
*val
)
546 struct ar40xx_priv
*priv
= swdev_to_ar40xx(dev
);
548 mutex_lock(&priv
->reg_mutex
);
549 priv
->monitor_port
= val
->value
.i
;
550 ar40xx_set_mirror_regs(priv
);
551 mutex_unlock(&priv
->reg_mutex
);
557 ar40xx_sw_get_mirror_monitor_port(struct switch_dev
*dev
,
558 const struct switch_attr
*attr
,
559 struct switch_val
*val
)
561 struct ar40xx_priv
*priv
= swdev_to_ar40xx(dev
);
563 mutex_lock(&priv
->reg_mutex
);
564 val
->value
.i
= priv
->monitor_port
;
565 mutex_unlock(&priv
->reg_mutex
);
570 ar40xx_sw_set_mirror_source_port(struct switch_dev
*dev
,
571 const struct switch_attr
*attr
,
572 struct switch_val
*val
)
574 struct ar40xx_priv
*priv
= swdev_to_ar40xx(dev
);
576 mutex_lock(&priv
->reg_mutex
);
577 priv
->source_port
= val
->value
.i
;
578 ar40xx_set_mirror_regs(priv
);
579 mutex_unlock(&priv
->reg_mutex
);
585 ar40xx_sw_get_mirror_source_port(struct switch_dev
*dev
,
586 const struct switch_attr
*attr
,
587 struct switch_val
*val
)
589 struct ar40xx_priv
*priv
= swdev_to_ar40xx(dev
);
591 mutex_lock(&priv
->reg_mutex
);
592 val
->value
.i
= priv
->source_port
;
593 mutex_unlock(&priv
->reg_mutex
);
598 ar40xx_sw_set_linkdown(struct switch_dev
*dev
,
599 const struct switch_attr
*attr
,
600 struct switch_val
*val
)
602 struct ar40xx_priv
*priv
= swdev_to_ar40xx(dev
);
604 if (val
->value
.i
== 1)
605 ar40xx_port_phy_linkdown(priv
);
607 ar40xx_phy_init(priv
);
613 ar40xx_sw_set_port_reset_mib(struct switch_dev
*dev
,
614 const struct switch_attr
*attr
,
615 struct switch_val
*val
)
617 struct ar40xx_priv
*priv
= swdev_to_ar40xx(dev
);
621 port
= val
->port_vlan
;
622 if (port
>= dev
->ports
)
625 mutex_lock(&priv
->mib_lock
);
626 ret
= ar40xx_mib_capture(priv
);
630 ar40xx_mib_fetch_port_stat(priv
, port
, true);
633 mutex_unlock(&priv
->mib_lock
);
638 ar40xx_sw_get_port_mib(struct switch_dev
*dev
,
639 const struct switch_attr
*attr
,
640 struct switch_val
*val
)
642 struct ar40xx_priv
*priv
= swdev_to_ar40xx(dev
);
646 char *buf
= priv
->buf
;
648 u32 num_mibs
= ARRAY_SIZE(ar40xx_mibs
);
650 port
= val
->port_vlan
;
651 if (port
>= dev
->ports
)
654 mutex_lock(&priv
->mib_lock
);
655 ret
= ar40xx_mib_capture(priv
);
659 ar40xx_mib_fetch_port_stat(priv
, port
, false);
661 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
662 "Port %d MIB counters\n",
665 mib_stats
= &priv
->mib_stats
[port
* num_mibs
];
666 for (i
= 0; i
< num_mibs
; i
++)
667 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
676 mutex_unlock(&priv
->mib_lock
);
681 ar40xx_sw_set_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
682 struct switch_val
*val
)
684 struct ar40xx_priv
*priv
= swdev_to_ar40xx(dev
);
686 priv
->vlan_id
[val
->port_vlan
] = val
->value
.i
;
691 ar40xx_sw_get_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
692 struct switch_val
*val
)
694 struct ar40xx_priv
*priv
= swdev_to_ar40xx(dev
);
696 val
->value
.i
= priv
->vlan_id
[val
->port_vlan
];
701 ar40xx_sw_get_pvid(struct switch_dev
*dev
, int port
, int *vlan
)
703 struct ar40xx_priv
*priv
= swdev_to_ar40xx(dev
);
704 *vlan
= priv
->pvid
[port
];
709 ar40xx_sw_set_pvid(struct switch_dev
*dev
, int port
, int vlan
)
711 struct ar40xx_priv
*priv
= swdev_to_ar40xx(dev
);
713 /* make sure no invalid PVIDs get set */
714 if (vlan
>= dev
->vlans
)
717 priv
->pvid
[port
] = vlan
;
722 ar40xx_read_port_link(struct ar40xx_priv
*priv
, int port
,
723 struct switch_port_link
*link
)
728 memset(link
, 0, sizeof(*link
));
730 status
= ar40xx_read(priv
, AR40XX_REG_PORT_STATUS(port
));
732 link
->aneg
= !!(status
& AR40XX_PORT_AUTO_LINK_EN
);
733 if (link
->aneg
|| (port
!= AR40XX_PORT_CPU
))
734 link
->link
= !!(status
& AR40XX_PORT_STATUS_LINK_UP
);
741 link
->duplex
= !!(status
& AR40XX_PORT_DUPLEX
);
742 link
->tx_flow
= !!(status
& AR40XX_PORT_STATUS_TXFLOW
);
743 link
->rx_flow
= !!(status
& AR40XX_PORT_STATUS_RXFLOW
);
745 speed
= (status
& AR40XX_PORT_SPEED
) >>
746 AR40XX_PORT_STATUS_SPEED_S
;
749 case AR40XX_PORT_SPEED_10M
:
750 link
->speed
= SWITCH_PORT_SPEED_10
;
752 case AR40XX_PORT_SPEED_100M
:
753 link
->speed
= SWITCH_PORT_SPEED_100
;
755 case AR40XX_PORT_SPEED_1000M
:
756 link
->speed
= SWITCH_PORT_SPEED_1000
;
759 link
->speed
= SWITCH_PORT_SPEED_UNKNOWN
;
765 ar40xx_sw_get_port_link(struct switch_dev
*dev
, int port
,
766 struct switch_port_link
*link
)
768 struct ar40xx_priv
*priv
= swdev_to_ar40xx(dev
);
770 ar40xx_read_port_link(priv
, port
, link
);
774 static const struct switch_attr ar40xx_sw_attr_globals
[] = {
776 .type
= SWITCH_TYPE_INT
,
777 .name
= "enable_vlan",
778 .description
= "Enable VLAN mode",
779 .set
= ar40xx_sw_set_vlan
,
780 .get
= ar40xx_sw_get_vlan
,
784 .type
= SWITCH_TYPE_NOVAL
,
785 .name
= "reset_mibs",
786 .description
= "Reset all MIB counters",
787 .set
= ar40xx_sw_set_reset_mibs
,
790 .type
= SWITCH_TYPE_INT
,
791 .name
= "enable_mirror_rx",
792 .description
= "Enable mirroring of RX packets",
793 .set
= ar40xx_sw_set_mirror_rx_enable
,
794 .get
= ar40xx_sw_get_mirror_rx_enable
,
798 .type
= SWITCH_TYPE_INT
,
799 .name
= "enable_mirror_tx",
800 .description
= "Enable mirroring of TX packets",
801 .set
= ar40xx_sw_set_mirror_tx_enable
,
802 .get
= ar40xx_sw_get_mirror_tx_enable
,
806 .type
= SWITCH_TYPE_INT
,
807 .name
= "mirror_monitor_port",
808 .description
= "Mirror monitor port",
809 .set
= ar40xx_sw_set_mirror_monitor_port
,
810 .get
= ar40xx_sw_get_mirror_monitor_port
,
811 .max
= AR40XX_NUM_PORTS
- 1
814 .type
= SWITCH_TYPE_INT
,
815 .name
= "mirror_source_port",
816 .description
= "Mirror source port",
817 .set
= ar40xx_sw_set_mirror_source_port
,
818 .get
= ar40xx_sw_get_mirror_source_port
,
819 .max
= AR40XX_NUM_PORTS
- 1
822 .type
= SWITCH_TYPE_INT
,
824 .description
= "Link down all the PHYs",
825 .set
= ar40xx_sw_set_linkdown
,
830 static const struct switch_attr ar40xx_sw_attr_port
[] = {
832 .type
= SWITCH_TYPE_NOVAL
,
834 .description
= "Reset single port MIB counters",
835 .set
= ar40xx_sw_set_port_reset_mib
,
838 .type
= SWITCH_TYPE_STRING
,
840 .description
= "Get port's MIB counters",
842 .get
= ar40xx_sw_get_port_mib
,
846 const struct switch_attr ar40xx_sw_attr_vlan
[] = {
848 .type
= SWITCH_TYPE_INT
,
850 .description
= "VLAN ID (0-4094)",
851 .set
= ar40xx_sw_set_vid
,
852 .get
= ar40xx_sw_get_vid
,
857 /* End of swconfig support */
860 ar40xx_wait_bit(struct ar40xx_priv
*priv
, int reg
, u32 mask
, u32 val
)
866 t
= ar40xx_read(priv
, reg
);
867 if ((t
& mask
) == val
)
873 usleep_range(10, 20);
876 pr_err("ar40xx: timeout for reg %08x: %08x & %08x != %08x\n",
877 (unsigned int)reg
, t
, mask
, val
);
882 ar40xx_atu_flush(struct ar40xx_priv
*priv
)
886 ret
= ar40xx_wait_bit(priv
, AR40XX_REG_ATU_FUNC
,
887 AR40XX_ATU_FUNC_BUSY
, 0);
889 ar40xx_write(priv
, AR40XX_REG_ATU_FUNC
,
890 AR40XX_ATU_FUNC_OP_FLUSH
|
891 AR40XX_ATU_FUNC_BUSY
);
897 ar40xx_ess_reset(struct ar40xx_priv
*priv
)
899 reset_control_assert(priv
->ess_rst
);
901 reset_control_deassert(priv
->ess_rst
);
902 /* Waiting for all inner tables init done.
907 pr_info("ESS reset ok!\n");
910 /* Start of psgmii self test */
913 ar40xx_malibu_psgmii_ess_reset(struct ar40xx_priv
*priv
)
916 struct mii_bus
*bus
= priv
->mii_bus
;
917 /* reset phy psgmii */
918 /* fix phy psgmii RX 20bit */
919 mdiobus_write(bus
, 5, 0x0, 0x005b);
920 /* reset phy psgmii */
921 mdiobus_write(bus
, 5, 0x0, 0x001b);
922 /* release reset phy psgmii */
923 mdiobus_write(bus
, 5, 0x0, 0x005b);
925 for (n
= 0; n
< AR40XX_PSGMII_CALB_NUM
; n
++) {
928 status
= ar40xx_phy_mmd_read(priv
, 5, 1, 0x28);
931 /* Polling interval to check PSGMII PLL in malibu is ready
932 * the worst time is 8.67ms
933 * for 25MHz reference clock
934 * [512+(128+2048)*49]*80ns+100us
939 /*check malibu psgmii calibration done end..*/
941 /*freeze phy psgmii RX CDR*/
942 mdiobus_write(bus
, 5, 0x1a, 0x2230);
944 ar40xx_ess_reset(priv
);
946 /*check psgmii calibration done start*/
947 for (n
= 0; n
< AR40XX_PSGMII_CALB_NUM
; n
++) {
950 status
= ar40xx_psgmii_read(priv
, 0xa0);
953 /* Polling interval to check PSGMII PLL in ESS is ready */
957 /* check dakota psgmii calibration done end..*/
959 /* relesae phy psgmii RX CDR */
960 mdiobus_write(bus
, 5, 0x1a, 0x3230);
961 /* release phy psgmii RX 20bit */
962 mdiobus_write(bus
, 5, 0x0, 0x005f);
966 ar40xx_psgmii_single_phy_testing(struct ar40xx_priv
*priv
, int phy
)
973 u32 tx_all_ok
, rx_all_ok
;
974 struct mii_bus
*bus
= priv
->mii_bus
;
976 mdiobus_write(bus
, phy
, 0x0, 0x9000);
977 mdiobus_write(bus
, phy
, 0x0, 0x4140);
979 for (j
= 0; j
< AR40XX_PSGMII_CALB_NUM
; j
++) {
982 status
= mdiobus_read(bus
, phy
, 0x11);
983 if (status
& AR40XX_PHY_SPEC_STATUS_LINK
)
985 /* the polling interval to check if the PHY link up or not
986 * maxwait_timer: 750 ms +/-10 ms
987 * minwait_timer : 1 us +/- 0.1us
988 * time resides in minwait_timer ~ maxwait_timer
989 * see IEEE 802.3 section 40.4.5.2
995 ar40xx_phy_mmd_write(priv
, phy
, 7, 0x8029, 0x0000);
996 ar40xx_phy_mmd_write(priv
, phy
, 7, 0x8029, 0x0003);
999 ar40xx_phy_mmd_write(priv
, phy
, 7, 0x8020, 0xa000);
1000 /* wait for all traffic end
1001 * 4096(pkt num)*1524(size)*8ns(125MHz)=49.9ms
1006 tx_ok
= ar40xx_phy_mmd_read(priv
, phy
, 7, 0x802e);
1007 tx_ok_high16
= ar40xx_phy_mmd_read(priv
, phy
, 7, 0x802d);
1008 tx_error
= ar40xx_phy_mmd_read(priv
, phy
, 7, 0x802f);
1009 rx_ok
= ar40xx_phy_mmd_read(priv
, phy
, 7, 0x802b);
1010 rx_ok_high16
= ar40xx_phy_mmd_read(priv
, phy
, 7, 0x802a);
1011 rx_error
= ar40xx_phy_mmd_read(priv
, phy
, 7, 0x802c);
1012 tx_all_ok
= tx_ok
+ (tx_ok_high16
<< 16);
1013 rx_all_ok
= rx_ok
+ (rx_ok_high16
<< 16);
1014 if (tx_all_ok
== 0x1000 && tx_error
== 0) {
1016 priv
->phy_t_status
&= (~BIT(phy
));
1018 pr_info("PHY %d single test PSGMII issue happen!\n", phy
);
1019 priv
->phy_t_status
|= BIT(phy
);
1022 mdiobus_write(bus
, phy
, 0x0, 0x1840);
1026 ar40xx_psgmii_all_phy_testing(struct ar40xx_priv
*priv
)
1029 struct mii_bus
*bus
= priv
->mii_bus
;
1031 mdiobus_write(bus
, 0x1f, 0x0, 0x9000);
1032 mdiobus_write(bus
, 0x1f, 0x0, 0x4140);
1034 for (j
= 0; j
< AR40XX_PSGMII_CALB_NUM
; j
++) {
1035 for (phy
= 0; phy
< AR40XX_NUM_PORTS
- 1; phy
++) {
1038 status
= mdiobus_read(bus
, phy
, 0x11);
1039 if (!(status
& BIT(10)))
1043 if (phy
>= (AR40XX_NUM_PORTS
- 1))
1045 /* The polling interva to check if the PHY link up or not */
1049 ar40xx_phy_mmd_write(priv
, 0x1f, 7, 0x8029, 0x0000);
1050 ar40xx_phy_mmd_write(priv
, 0x1f, 7, 0x8029, 0x0003);
1053 ar40xx_phy_mmd_write(priv
, 0x1f, 7, 0x8020, 0xa000);
1054 /* wait for all traffic end
1055 * 4096(pkt num)*1524(size)*8ns(125MHz)=49.9ms
1059 for (phy
= 0; phy
< AR40XX_NUM_PORTS
- 1; phy
++) {
1060 u32 tx_ok
, tx_error
;
1061 u32 rx_ok
, rx_error
;
1064 u32 tx_all_ok
, rx_all_ok
;
1067 tx_ok
= ar40xx_phy_mmd_read(priv
, phy
, 7, 0x802e);
1068 tx_ok_high16
= ar40xx_phy_mmd_read(priv
, phy
, 7, 0x802d);
1069 tx_error
= ar40xx_phy_mmd_read(priv
, phy
, 7, 0x802f);
1070 rx_ok
= ar40xx_phy_mmd_read(priv
, phy
, 7, 0x802b);
1071 rx_ok_high16
= ar40xx_phy_mmd_read(priv
, phy
, 7, 0x802a);
1072 rx_error
= ar40xx_phy_mmd_read(priv
, phy
, 7, 0x802c);
1073 tx_all_ok
= tx_ok
+ (tx_ok_high16
<<16);
1074 rx_all_ok
= rx_ok
+ (rx_ok_high16
<<16);
1075 if (tx_all_ok
== 0x1000 && tx_error
== 0) {
1077 priv
->phy_t_status
&= ~BIT(phy
+ 8);
1079 pr_info("PHY%d test see issue!\n", phy
);
1080 priv
->phy_t_status
|= BIT(phy
+ 8);
1084 pr_debug("PHY all test 0x%x \r\n", priv
->phy_t_status
);
1088 ar40xx_psgmii_self_test(struct ar40xx_priv
*priv
)
1091 struct mii_bus
*bus
= priv
->mii_bus
;
1093 ar40xx_malibu_psgmii_ess_reset(priv
);
1095 /* switch to access MII reg for copper */
1096 mdiobus_write(bus
, 4, 0x1f, 0x8500);
1097 for (phy
= 0; phy
< AR40XX_NUM_PORTS
- 1; phy
++) {
1098 /*enable phy mdio broadcast write*/
1099 ar40xx_phy_mmd_write(priv
, phy
, 7, 0x8028, 0x801f);
1101 /* force no link by power down */
1102 mdiobus_write(bus
, 0x1f, 0x0, 0x1840);
1104 ar40xx_phy_mmd_write(priv
, 0x1f, 7, 0x8021, 0x1000);
1105 ar40xx_phy_mmd_write(priv
, 0x1f, 7, 0x8062, 0x05e0);
1108 mdiobus_write(bus
, 0x1f, 0x10, 0x6800);
1109 for (i
= 0; i
< AR40XX_PSGMII_CALB_NUM
; i
++) {
1110 priv
->phy_t_status
= 0;
1112 for (phy
= 0; phy
< AR40XX_NUM_PORTS
- 1; phy
++) {
1113 ar40xx_rmw(priv
, AR40XX_REG_PORT_LOOKUP(phy
+ 1),
1114 AR40XX_PORT_LOOKUP_LOOPBACK
,
1115 AR40XX_PORT_LOOKUP_LOOPBACK
);
1118 for (phy
= 0; phy
< AR40XX_NUM_PORTS
- 1; phy
++)
1119 ar40xx_psgmii_single_phy_testing(priv
, phy
);
1121 ar40xx_psgmii_all_phy_testing(priv
);
1123 if (priv
->phy_t_status
)
1124 ar40xx_malibu_psgmii_ess_reset(priv
);
1129 if (i
>= AR40XX_PSGMII_CALB_NUM
)
1130 pr_info("PSGMII cannot recover\n");
1132 pr_debug("PSGMII recovered after %d times reset\n", i
);
1134 /* configuration recover */
1136 ar40xx_phy_mmd_write(priv
, 0x1f, 7, 0x8021, 0x0);
1138 ar40xx_phy_mmd_write(priv
, 0x1f, 7, 0x8029, 0x0);
1139 /* disable traffic */
1140 ar40xx_phy_mmd_write(priv
, 0x1f, 7, 0x8020, 0x0);
1144 ar40xx_psgmii_self_test_clean(struct ar40xx_priv
*priv
)
1147 struct mii_bus
*bus
= priv
->mii_bus
;
1149 /* disable phy internal loopback */
1150 mdiobus_write(bus
, 0x1f, 0x10, 0x6860);
1151 mdiobus_write(bus
, 0x1f, 0x0, 0x9040);
1153 for (phy
= 0; phy
< AR40XX_NUM_PORTS
- 1; phy
++) {
1154 /* disable mac loop back */
1155 ar40xx_rmw(priv
, AR40XX_REG_PORT_LOOKUP(phy
+ 1),
1156 AR40XX_PORT_LOOKUP_LOOPBACK
, 0);
1157 /* disable phy mdio broadcast write */
1158 ar40xx_phy_mmd_write(priv
, phy
, 7, 0x8028, 0x001f);
1161 /* clear fdb entry */
1162 ar40xx_atu_flush(priv
);
1165 /* End of psgmii self test */
1168 ar40xx_mac_mode_init(struct ar40xx_priv
*priv
, u32 mode
)
1170 if (mode
== PORT_WRAPPER_PSGMII
) {
1171 ar40xx_psgmii_write(priv
, AR40XX_PSGMII_MODE_CONTROL
, 0x2200);
1172 ar40xx_psgmii_write(priv
, AR40XX_PSGMIIPHY_TX_CONTROL
, 0x8380);
1177 int ar40xx_cpuport_setup(struct ar40xx_priv
*priv
)
1181 t
= AR40XX_PORT_STATUS_TXFLOW
|
1182 AR40XX_PORT_STATUS_RXFLOW
|
1183 AR40XX_PORT_TXHALF_FLOW
|
1184 AR40XX_PORT_DUPLEX
|
1185 AR40XX_PORT_SPEED_1000M
;
1186 ar40xx_write(priv
, AR40XX_REG_PORT_STATUS(0), t
);
1187 usleep_range(10, 20);
1189 t
|= AR40XX_PORT_TX_EN
|
1191 ar40xx_write(priv
, AR40XX_REG_PORT_STATUS(0), t
);
1197 ar40xx_init_port(struct ar40xx_priv
*priv
, int port
)
1201 ar40xx_rmw(priv
, AR40XX_REG_PORT_STATUS(port
),
1202 AR40XX_PORT_AUTO_LINK_EN
, 0);
1204 ar40xx_write(priv
, AR40XX_REG_PORT_HEADER(port
), 0);
1206 ar40xx_write(priv
, AR40XX_REG_PORT_VLAN0(port
), 0);
1208 t
= AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH
<< AR40XX_PORT_VLAN1_OUT_MODE_S
;
1209 ar40xx_write(priv
, AR40XX_REG_PORT_VLAN1(port
), t
);
1211 t
= AR40XX_PORT_LOOKUP_LEARN
;
1212 t
|= AR40XX_PORT_STATE_FORWARD
<< AR40XX_PORT_LOOKUP_STATE_S
;
1213 ar40xx_write(priv
, AR40XX_REG_PORT_LOOKUP(port
), t
);
1217 ar40xx_init_globals(struct ar40xx_priv
*priv
)
1221 /* enable CPU port and disable mirror port */
1222 t
= AR40XX_FWD_CTRL0_CPU_PORT_EN
|
1223 AR40XX_FWD_CTRL0_MIRROR_PORT
;
1224 ar40xx_write(priv
, AR40XX_REG_FWD_CTRL0
, t
);
1226 /* forward multicast and broadcast frames to CPU */
1227 t
= (AR40XX_PORTS_ALL
<< AR40XX_FWD_CTRL1_UC_FLOOD_S
) |
1228 (AR40XX_PORTS_ALL
<< AR40XX_FWD_CTRL1_MC_FLOOD_S
) |
1229 (AR40XX_PORTS_ALL
<< AR40XX_FWD_CTRL1_BC_FLOOD_S
);
1230 ar40xx_write(priv
, AR40XX_REG_FWD_CTRL1
, t
);
1232 /* enable jumbo frames */
1233 ar40xx_rmw(priv
, AR40XX_REG_MAX_FRAME_SIZE
,
1234 AR40XX_MAX_FRAME_SIZE_MTU
, 9018 + 8 + 2);
1236 /* Enable MIB counters */
1237 ar40xx_rmw(priv
, AR40XX_REG_MODULE_EN
, 0,
1238 AR40XX_MODULE_EN_MIB
);
1241 ar40xx_write(priv
, AR40XX_REG_EEE_CTRL
, 0);
1243 /* set flowctrl thershold for cpu port */
1244 t
= (AR40XX_PORT0_FC_THRESH_ON_DFLT
<< 16) |
1245 AR40XX_PORT0_FC_THRESH_OFF_DFLT
;
1246 ar40xx_write(priv
, AR40XX_REG_PORT_FLOWCTRL_THRESH(0), t
);
1250 ar40xx_hw_init(struct ar40xx_priv
*priv
)
1254 ar40xx_ess_reset(priv
);
1259 ar40xx_psgmii_self_test(priv
);
1260 ar40xx_psgmii_self_test_clean(priv
);
1262 ar40xx_mac_mode_init(priv
, priv
->mac_mode
);
1264 for (i
= 0; i
< priv
->dev
.ports
; i
++)
1265 ar40xx_init_port(priv
, i
);
1267 ar40xx_init_globals(priv
);
1272 /* Start of qm error WAR */
1275 int ar40xx_force_1g_full(struct ar40xx_priv
*priv
, u32 port_id
)
1279 if (port_id
< 0 || port_id
> 6)
1282 reg
= AR40XX_REG_PORT_STATUS(port_id
);
1283 return ar40xx_rmw(priv
, reg
, AR40XX_PORT_SPEED
,
1284 (AR40XX_PORT_SPEED_1000M
| AR40XX_PORT_DUPLEX
));
1288 int ar40xx_get_qm_status(struct ar40xx_priv
*priv
,
1289 u32 port_id
, u32
*qm_buffer_err
)
1294 if (port_id
< 1 || port_id
> 5) {
1300 reg
= AR40XX_REG_QM_PORT0_3_QNUM
;
1301 ar40xx_write(priv
, AR40XX_REG_QM_DEBUG_ADDR
, reg
);
1302 qm_val
= ar40xx_read(priv
, AR40XX_REG_QM_DEBUG_VALUE
);
1303 /* every 8 bits for each port */
1304 *qm_buffer_err
= (qm_val
>> (port_id
* 8)) & 0xFF;
1306 reg
= AR40XX_REG_QM_PORT4_6_QNUM
;
1307 ar40xx_write(priv
, AR40XX_REG_QM_DEBUG_ADDR
, reg
);
1308 qm_val
= ar40xx_read(priv
, AR40XX_REG_QM_DEBUG_VALUE
);
1309 /* every 8 bits for each port */
1310 *qm_buffer_err
= (qm_val
>> ((port_id
-4) * 8)) & 0xFF;
1317 ar40xx_sw_mac_polling_task(struct ar40xx_priv
*priv
)
1319 static int task_count
;
1322 u32 link
, speed
, duplex
;
1324 u16 port_phy_status
[AR40XX_NUM_PORTS
];
1325 static u32 qm_err_cnt
[AR40XX_NUM_PORTS
] = {0, 0, 0, 0, 0, 0};
1326 static u32 link_cnt
[AR40XX_NUM_PORTS
] = {0, 0, 0, 0, 0, 0};
1327 struct mii_bus
*bus
= NULL
;
1329 if (!priv
|| !priv
->mii_bus
)
1332 bus
= priv
->mii_bus
;
1336 for (i
= 1; i
< AR40XX_NUM_PORTS
; ++i
) {
1337 port_phy_status
[i
] =
1338 mdiobus_read(bus
, i
-1, AR40XX_PHY_SPEC_STATUS
);
1339 speed
= link
= duplex
= port_phy_status
[i
];
1340 speed
&= AR40XX_PHY_SPEC_STATUS_SPEED
;
1342 link
&= AR40XX_PHY_SPEC_STATUS_LINK
;
1344 duplex
&= AR40XX_PHY_SPEC_STATUS_DUPLEX
;
1347 if (link
!= priv
->ar40xx_port_old_link
[i
]) {
1350 if ((priv
->ar40xx_port_old_link
[i
] ==
1351 AR40XX_PORT_LINK_UP
) &&
1352 (link
== AR40XX_PORT_LINK_DOWN
)) {
1353 /* LINK_EN disable(MAC force mode)*/
1354 reg
= AR40XX_REG_PORT_STATUS(i
);
1355 ar40xx_rmw(priv
, reg
,
1356 AR40XX_PORT_AUTO_LINK_EN
, 0);
1358 /* Check queue buffer */
1360 ar40xx_get_qm_status(priv
, i
, &qm_buffer_err
);
1361 if (qm_buffer_err
) {
1362 priv
->ar40xx_port_qm_buf
[i
] =
1363 AR40XX_QM_NOT_EMPTY
;
1367 priv
->ar40xx_port_qm_buf
[i
] =
1369 ar40xx_force_1g_full(priv
, i
);
1370 /* Ref:QCA8337 Datasheet,Clearing
1371 * MENU_CTRL_EN prevents phy to
1372 * stuck in 100BT mode when
1373 * bringing up the link
1375 ar40xx_phy_dbg_read(priv
, i
-1,
1378 phy_val
&= (~AR40XX_PHY_MANU_CTRL_EN
);
1379 ar40xx_phy_dbg_write(priv
, i
-1,
1383 priv
->ar40xx_port_old_link
[i
] = link
;
1384 } else if ((priv
->ar40xx_port_old_link
[i
] ==
1385 AR40XX_PORT_LINK_DOWN
) &&
1386 (link
== AR40XX_PORT_LINK_UP
)) {
1388 if (priv
->port_link_up
[i
] < 1) {
1389 ++priv
->port_link_up
[i
];
1391 /* Change port status */
1392 reg
= AR40XX_REG_PORT_STATUS(i
);
1393 value
= ar40xx_read(priv
, reg
);
1394 priv
->port_link_up
[i
] = 0;
1396 value
&= ~(AR40XX_PORT_DUPLEX
|
1398 value
|= speed
| (duplex
? BIT(6) : 0);
1399 ar40xx_write(priv
, reg
, value
);
1400 /* clock switch need such time
1403 usleep_range(100, 200);
1405 value
|= AR40XX_PORT_AUTO_LINK_EN
;
1406 ar40xx_write(priv
, reg
, value
);
1407 /* HW need such time to make sure link
1408 * stable before enable MAC
1410 usleep_range(100, 200);
1412 if (speed
== AR40XX_PORT_SPEED_100M
) {
1414 /* Enable @100M, if down to 10M
1415 * clock will change smoothly
1417 ar40xx_phy_dbg_read(priv
, i
-1,
1421 AR40XX_PHY_MANU_CTRL_EN
;
1422 ar40xx_phy_dbg_write(priv
, i
-1,
1426 priv
->ar40xx_port_old_link
[i
] = link
;
1431 if (priv
->ar40xx_port_qm_buf
[i
] == AR40XX_QM_NOT_EMPTY
) {
1433 ar40xx_get_qm_status(priv
, i
, &qm_buffer_err
);
1434 if (qm_buffer_err
) {
1437 priv
->ar40xx_port_qm_buf
[i
] =
1440 ar40xx_force_1g_full(priv
, i
);
1447 ar40xx_qm_err_check_work_task(struct work_struct
*work
)
1449 struct ar40xx_priv
*priv
= container_of(work
, struct ar40xx_priv
,
1452 mutex_lock(&priv
->qm_lock
);
1454 ar40xx_sw_mac_polling_task(priv
);
1456 mutex_unlock(&priv
->qm_lock
);
1458 schedule_delayed_work(&priv
->qm_dwork
,
1459 msecs_to_jiffies(AR40XX_QM_WORK_DELAY
));
1463 ar40xx_qm_err_check_work_start(struct ar40xx_priv
*priv
)
1465 mutex_init(&priv
->qm_lock
);
1467 INIT_DELAYED_WORK(&priv
->qm_dwork
, ar40xx_qm_err_check_work_task
);
1469 schedule_delayed_work(&priv
->qm_dwork
,
1470 msecs_to_jiffies(AR40XX_QM_WORK_DELAY
));
1475 /* End of qm error WAR */
1478 ar40xx_vlan_init(struct ar40xx_priv
*priv
)
1483 /* By default Enable VLAN */
1485 priv
->vlan_table
[AR40XX_LAN_VLAN
] = priv
->cpu_bmp
| priv
->lan_bmp
;
1486 priv
->vlan_table
[AR40XX_WAN_VLAN
] = priv
->cpu_bmp
| priv
->wan_bmp
;
1487 priv
->vlan_tagged
= priv
->cpu_bmp
;
1488 bmp
= priv
->lan_bmp
;
1489 for_each_set_bit(port
, &bmp
, AR40XX_NUM_PORTS
)
1490 priv
->pvid
[port
] = AR40XX_LAN_VLAN
;
1492 bmp
= priv
->wan_bmp
;
1493 for_each_set_bit(port
, &bmp
, AR40XX_NUM_PORTS
)
1494 priv
->pvid
[port
] = AR40XX_WAN_VLAN
;
1500 ar40xx_mib_work_func(struct work_struct
*work
)
1502 struct ar40xx_priv
*priv
;
1505 priv
= container_of(work
, struct ar40xx_priv
, mib_work
.work
);
1507 mutex_lock(&priv
->mib_lock
);
1509 err
= ar40xx_mib_capture(priv
);
1513 ar40xx_mib_fetch_port_stat(priv
, priv
->mib_next_port
, false);
1516 priv
->mib_next_port
++;
1517 if (priv
->mib_next_port
>= priv
->dev
.ports
)
1518 priv
->mib_next_port
= 0;
1520 mutex_unlock(&priv
->mib_lock
);
1522 schedule_delayed_work(&priv
->mib_work
,
1523 msecs_to_jiffies(AR40XX_MIB_WORK_DELAY
));
1527 ar40xx_setup_port(struct ar40xx_priv
*priv
, int port
, u32 members
)
1530 u32 egress
, ingress
;
1531 u32 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
1534 egress
= AR40XX_PORT_VLAN1_OUT_MODE_UNMOD
;
1536 ingress
= AR40XX_IN_SECURE
;
1538 egress
= AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH
;
1539 ingress
= AR40XX_IN_PORT_ONLY
;
1542 t
= pvid
<< AR40XX_PORT_VLAN0_DEF_SVID_S
;
1543 t
|= pvid
<< AR40XX_PORT_VLAN0_DEF_CVID_S
;
1544 ar40xx_write(priv
, AR40XX_REG_PORT_VLAN0(port
), t
);
1546 t
= AR40XX_PORT_VLAN1_PORT_VLAN_PROP
;
1547 t
|= egress
<< AR40XX_PORT_VLAN1_OUT_MODE_S
;
1549 ar40xx_write(priv
, AR40XX_REG_PORT_VLAN1(port
), t
);
1552 t
|= AR40XX_PORT_LOOKUP_LEARN
;
1553 t
|= ingress
<< AR40XX_PORT_LOOKUP_IN_MODE_S
;
1554 t
|= AR40XX_PORT_STATE_FORWARD
<< AR40XX_PORT_LOOKUP_STATE_S
;
1555 ar40xx_write(priv
, AR40XX_REG_PORT_LOOKUP(port
), t
);
1559 ar40xx_vtu_op(struct ar40xx_priv
*priv
, u32 op
, u32 val
)
1561 if (ar40xx_wait_bit(priv
, AR40XX_REG_VTU_FUNC1
,
1562 AR40XX_VTU_FUNC1_BUSY
, 0))
1565 if ((op
& AR40XX_VTU_FUNC1_OP
) == AR40XX_VTU_FUNC1_OP_LOAD
)
1566 ar40xx_write(priv
, AR40XX_REG_VTU_FUNC0
, val
);
1568 op
|= AR40XX_VTU_FUNC1_BUSY
;
1569 ar40xx_write(priv
, AR40XX_REG_VTU_FUNC1
, op
);
1573 ar40xx_vtu_load_vlan(struct ar40xx_priv
*priv
, u32 vid
, u32 port_mask
)
1579 op
= AR40XX_VTU_FUNC1_OP_LOAD
| (vid
<< AR40XX_VTU_FUNC1_VID_S
);
1580 val
= AR40XX_VTU_FUNC0_VALID
| AR40XX_VTU_FUNC0_IVL
;
1581 for (i
= 0; i
< AR40XX_NUM_PORTS
; i
++) {
1584 if ((port_mask
& BIT(i
)) == 0)
1585 mode
= AR40XX_VTU_FUNC0_EG_MODE_NOT
;
1586 else if (priv
->vlan
== 0)
1587 mode
= AR40XX_VTU_FUNC0_EG_MODE_KEEP
;
1588 else if ((priv
->vlan_tagged
& BIT(i
)) ||
1589 (priv
->vlan_id
[priv
->pvid
[i
]] != vid
))
1590 mode
= AR40XX_VTU_FUNC0_EG_MODE_TAG
;
1592 mode
= AR40XX_VTU_FUNC0_EG_MODE_UNTAG
;
1594 val
|= mode
<< AR40XX_VTU_FUNC0_EG_MODE_S(i
);
1596 ar40xx_vtu_op(priv
, op
, val
);
1600 ar40xx_vtu_flush(struct ar40xx_priv
*priv
)
1602 ar40xx_vtu_op(priv
, AR40XX_VTU_FUNC1_OP_FLUSH
, 0);
1606 ar40xx_sw_hw_apply(struct switch_dev
*dev
)
1608 struct ar40xx_priv
*priv
= swdev_to_ar40xx(dev
);
1609 u8 portmask
[AR40XX_NUM_PORTS
];
1612 mutex_lock(&priv
->reg_mutex
);
1613 /* flush all vlan entries */
1614 ar40xx_vtu_flush(priv
);
1616 memset(portmask
, 0, sizeof(portmask
));
1618 for (j
= 0; j
< AR40XX_MAX_VLANS
; j
++) {
1619 u8 vp
= priv
->vlan_table
[j
];
1624 for (i
= 0; i
< dev
->ports
; i
++) {
1628 portmask
[i
] |= vp
& ~mask
;
1631 ar40xx_vtu_load_vlan(priv
, priv
->vlan_id
[j
],
1632 priv
->vlan_table
[j
]);
1635 /* 8021q vlan disabled */
1636 for (i
= 0; i
< dev
->ports
; i
++) {
1637 if (i
== AR40XX_PORT_CPU
)
1640 portmask
[i
] = BIT(AR40XX_PORT_CPU
);
1641 portmask
[AR40XX_PORT_CPU
] |= BIT(i
);
1645 /* update the port destination mask registers and tag settings */
1646 for (i
= 0; i
< dev
->ports
; i
++)
1647 ar40xx_setup_port(priv
, i
, portmask
[i
]);
1649 ar40xx_set_mirror_regs(priv
);
1651 mutex_unlock(&priv
->reg_mutex
);
1656 ar40xx_sw_reset_switch(struct switch_dev
*dev
)
1658 struct ar40xx_priv
*priv
= swdev_to_ar40xx(dev
);
1661 mutex_lock(&priv
->reg_mutex
);
1662 memset(&priv
->vlan
, 0, sizeof(struct ar40xx_priv
) -
1663 offsetof(struct ar40xx_priv
, vlan
));
1665 for (i
= 0; i
< AR40XX_MAX_VLANS
; i
++)
1666 priv
->vlan_id
[i
] = i
;
1668 ar40xx_vlan_init(priv
);
1670 priv
->mirror_rx
= false;
1671 priv
->mirror_tx
= false;
1672 priv
->source_port
= 0;
1673 priv
->monitor_port
= 0;
1675 mutex_unlock(&priv
->reg_mutex
);
1677 rv
= ar40xx_sw_hw_apply(dev
);
1682 ar40xx_start(struct ar40xx_priv
*priv
)
1686 ret
= ar40xx_hw_init(priv
);
1690 ret
= ar40xx_sw_reset_switch(&priv
->dev
);
1694 /* at last, setup cpu port */
1695 ret
= ar40xx_cpuport_setup(priv
);
1699 schedule_delayed_work(&priv
->mib_work
,
1700 msecs_to_jiffies(AR40XX_MIB_WORK_DELAY
));
1702 ar40xx_qm_err_check_work_start(priv
);
1707 static const struct switch_dev_ops ar40xx_sw_ops
= {
1709 .attr
= ar40xx_sw_attr_globals
,
1710 .n_attr
= ARRAY_SIZE(ar40xx_sw_attr_globals
),
1713 .attr
= ar40xx_sw_attr_port
,
1714 .n_attr
= ARRAY_SIZE(ar40xx_sw_attr_port
),
1717 .attr
= ar40xx_sw_attr_vlan
,
1718 .n_attr
= ARRAY_SIZE(ar40xx_sw_attr_vlan
),
1720 .get_port_pvid
= ar40xx_sw_get_pvid
,
1721 .set_port_pvid
= ar40xx_sw_set_pvid
,
1722 .get_vlan_ports
= ar40xx_sw_get_ports
,
1723 .set_vlan_ports
= ar40xx_sw_set_ports
,
1724 .apply_config
= ar40xx_sw_hw_apply
,
1725 .reset_switch
= ar40xx_sw_reset_switch
,
1726 .get_port_link
= ar40xx_sw_get_port_link
,
1729 /* Platform driver probe function */
1731 static int ar40xx_probe(struct platform_device
*pdev
)
1733 struct device_node
*switch_node
;
1734 struct device_node
*psgmii_node
;
1735 struct device_node
*mdio_node
;
1736 const __be32
*mac_mode
;
1737 struct clk
*ess_clk
;
1738 struct switch_dev
*swdev
;
1739 struct ar40xx_priv
*priv
;
1742 struct resource psgmii_base
= {0};
1743 struct resource switch_base
= {0};
1746 priv
= devm_kzalloc(&pdev
->dev
, sizeof(*priv
), GFP_KERNEL
);
1750 platform_set_drvdata(pdev
, priv
);
1753 switch_node
= of_node_get(pdev
->dev
.of_node
);
1754 if (of_address_to_resource(switch_node
, 0, &switch_base
) != 0)
1757 priv
->hw_addr
= devm_ioremap_resource(&pdev
->dev
, &switch_base
);
1758 if (IS_ERR(priv
->hw_addr
)) {
1759 dev_err(&pdev
->dev
, "Failed to ioremap switch_base!\n");
1760 return PTR_ERR(priv
->hw_addr
);
1764 psgmii_node
= of_find_node_by_name(NULL
, "ess-psgmii");
1766 dev_err(&pdev
->dev
, "Failed to find ess-psgmii node!\n");
1770 if (of_address_to_resource(psgmii_node
, 0, &psgmii_base
) != 0)
1773 priv
->psgmii_hw_addr
= devm_ioremap_resource(&pdev
->dev
, &psgmii_base
);
1774 if (IS_ERR(priv
->psgmii_hw_addr
)) {
1775 dev_err(&pdev
->dev
, "psgmii ioremap fail!\n");
1776 return PTR_ERR(priv
->psgmii_hw_addr
);
1779 mac_mode
= of_get_property(switch_node
, "switch_mac_mode", &len
);
1781 dev_err(&pdev
->dev
, "Failed to read switch_mac_mode\n");
1784 priv
->mac_mode
= be32_to_cpup(mac_mode
);
1786 ess_clk
= of_clk_get_by_name(switch_node
, "ess_clk");
1788 clk_prepare_enable(ess_clk
);
1790 priv
->ess_rst
= devm_reset_control_get(&pdev
->dev
, "ess_rst");
1791 if (IS_ERR(priv
->ess_rst
)) {
1792 dev_err(&pdev
->dev
, "Failed to get ess_rst control!\n");
1793 return PTR_ERR(priv
->ess_rst
);
1796 if (of_property_read_u32(switch_node
, "switch_cpu_bmp",
1798 of_property_read_u32(switch_node
, "switch_lan_bmp",
1800 of_property_read_u32(switch_node
, "switch_wan_bmp",
1802 dev_err(&pdev
->dev
, "Failed to read port properties\n");
1806 mutex_init(&priv
->reg_mutex
);
1807 mutex_init(&priv
->mib_lock
);
1808 INIT_DELAYED_WORK(&priv
->mib_work
, ar40xx_mib_work_func
);
1810 /* register switch */
1813 mdio_node
= of_find_compatible_node(NULL
, NULL
, "qcom,ipq4019-mdio");
1815 dev_err(&pdev
->dev
, "Probe failed - Cannot find mdio node by phandle!\n");
1817 goto err_missing_phy
;
1820 priv
->mii_bus
= of_mdio_find_bus(mdio_node
);
1822 if (priv
->mii_bus
== NULL
) {
1823 dev_err(&pdev
->dev
, "Probe failed - Missing PHYs!\n");
1825 goto err_missing_phy
;
1828 swdev
->alias
= dev_name(&priv
->mii_bus
->dev
);
1830 swdev
->cpu_port
= AR40XX_PORT_CPU
;
1831 swdev
->name
= "QCA AR40xx";
1832 swdev
->vlans
= AR40XX_MAX_VLANS
;
1833 swdev
->ports
= AR40XX_NUM_PORTS
;
1834 swdev
->ops
= &ar40xx_sw_ops
;
1835 ret
= register_switch(swdev
, NULL
);
1837 dev_err(&pdev
->dev
, "Switch registration failed!\n");
1841 num_mibs
= ARRAY_SIZE(ar40xx_mibs
);
1842 len
= priv
->dev
.ports
* num_mibs
*
1843 sizeof(*priv
->mib_stats
);
1844 priv
->mib_stats
= devm_kzalloc(&pdev
->dev
, len
, GFP_KERNEL
);
1845 if (!priv
->mib_stats
) {
1847 goto err_unregister_switch
;
1854 err_unregister_switch
:
1855 unregister_switch(&priv
->dev
);
1857 platform_set_drvdata(pdev
, NULL
);
1861 static int ar40xx_remove(struct platform_device
*pdev
)
1863 struct ar40xx_priv
*priv
= platform_get_drvdata(pdev
);
1865 cancel_delayed_work_sync(&priv
->qm_dwork
);
1866 cancel_delayed_work_sync(&priv
->mib_work
);
1868 unregister_switch(&priv
->dev
);
1873 static const struct of_device_id ar40xx_of_mtable
[] = {
1874 {.compatible
= "qcom,ess-switch" },
1878 struct platform_driver ar40xx_drv
= {
1879 .probe
= ar40xx_probe
,
1880 .remove
= ar40xx_remove
,
1883 .of_match_table
= ar40xx_of_mtable
,
1887 module_platform_driver(ar40xx_drv
);
1889 MODULE_DESCRIPTION("IPQ40XX ESS driver");
1890 MODULE_LICENSE("Dual BSD/GPL");