2 * Device Tree Source for Meraki MR33 (Stinkbug)
4 * Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com>
5 * Copyright (C) 2017 Christian Lamparter <chunkeey@googlemail.com>
7 * Based on Cisco Meraki DTS from GPL release r25-linux-3.14-20170427
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without
11 * any warranty of any kind, whether express or implied.
14 #include "qcom-ipq4019.dtsi"
15 #include "qcom-ipq4019-bus.dtsi"
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/input/input.h>
18 #include <dt-bindings/soc/qcom,tcsr.h>
21 model = "Meraki MR33 Access Point";
22 compatible = "meraki,mr33", "qcom,ipq4019";
25 led-boot = &status_green;
26 led-failsafe = &status_red;
27 led-running = &status_green;
28 led-upgrade = &power_orange;
31 /* Do we really need this defined? */
33 device_type = "memory";
34 reg = <0x80000000 0x10000000>;
38 #address-cells = <0x1>;
43 reg = <0x87b80000 0x280000>;
48 reg = <0x87e00000 0x080000>;
53 reg = <0x87e80000 0x180000>;
61 pinctrl-0 = <&mdio_pins>;
62 pinctrl-names = "default";
63 /delete-node/ ethernet-phy@0;
64 /delete-node/ ethernet-phy@2;
65 /delete-node/ ethernet-phy@3;
66 /delete-node/ ethernet-phy@4;
69 /* It is a 56-bit counter that supplies the count to the ARM arch
70 timers and without upstream driver */
72 compatible = "qcom,qca-gcnt";
77 compatible = "qcom,tcsr";
78 reg = <0x1953000 0x1000>;
79 qcom,ess-interface-select = <TCSR_ESS_PSGMII_RGMII5>;
83 compatible = "qcom,tcsr";
84 reg = <0x1949000 0x100>;
85 qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
89 compatible = "qcom,tcsr";
90 reg = <0x1957000 0x100>;
91 qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
95 pinctrl-0 = <&serial_0_pins>;
96 pinctrl-names = "default";
101 pinctrl-0 = <&serial_1_pins>;
102 pinctrl-names = "default";
106 compatible = "ti,cc2650";
107 enable-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
120 switch_mac_mode = <0x3>; /* mac mode for RGMII RMII */
121 switch_lan_bmp = <0x0>; /* lan port bitmap */
122 switch_wan_bmp = <0x10>; /* wan port bitmap */
128 phy-mode = "rgmii-rxid";
134 compatible = "gpio-keys";
138 gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
139 linux,code = <KEY_RESTART>;
144 compatible = "gpio-leds";
146 power_orange: power {
147 label = "mr33:orange:power";
148 gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
163 qcom,phy_mdio_addr = <1>;
164 qcom,poll_required = <1>;
169 pinctrl-0 = <&i2c_0_pins>;
170 pinctrl-names = "default";
173 compatible = "atmel,24c64";
176 read-only; /* This holds our MAC & Meraki board-data */
181 pinctrl-0 = <&i2c_1_pins>;
182 pinctrl-names = "default";
186 enable-gpio = <&tlmm 48 GPIO_ACTIVE_HIGH>;
187 compatible = "ti,lp5562";
188 clock-mode = /bits/8 <2>;
193 chan-name = "mr33:red:status";
194 led-cur = /bits/ 8 <0x20>;
195 max-cur = /bits/ 8 <0x60>;
198 status_green: chan1 {
199 chan-name = "mr33:green:status";
200 led-cur = /bits/ 8 <0x20>;
201 max-cur = /bits/ 8 <0x60>;
205 chan-name = "mr33:blue:status";
206 led-cur = /bits/ 8 <0x20>;
207 max-cur = /bits/ 8 <0x60>;
211 chan-name = "mr33:white:status";
212 led-cur = /bits/ 8 <0x20>;
213 max-cur = /bits/ 8 <0x60>;
219 pinctrl-0 = <&nand_pins>;
220 pinctrl-names = "default";
225 compatible = "fixed-partitions";
226 #address-cells = <1>;
231 reg = <0x000000000000 0x000000100000>;
236 reg = <0x000000100000 0x000000100000>;
240 label = "bootconfig";
241 reg = <0x000000200000 0x000000100000>;
246 reg = <0x000000300000 0x000000100000>;
251 reg = <0x000000400000 0x000000100000>;
256 reg = <0x000000500000 0x000000080000>;
261 reg = <0x000000580000 0x000000080000>;
266 reg = <0x000000600000 0x000000080000>;
271 reg = <0x000000700000 0x000000200000>;
275 label = "u-boot-backup";
276 reg = <0x000000900000 0x000000200000>;
281 reg = <0x000000b00000 0x000000080000>;
286 reg = <0x000000c00000 0x000007000000>;
294 perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
295 wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
304 * GPIO43 should be 0/1 whenever the unit is
305 * powered through PoE or AC-Adapter.
306 * That said, playing with this seems to
310 mdio_pins: mdio_pinmux {
323 serial_0_pins: serial_pinmux {
325 pins = "gpio16", "gpio17";
326 function = "blsp_uart0";
331 serial_1_pins: serial1_pinmux {
333 /* We use the i2c-0 pins for serial_1 */
334 pins = "gpio8", "gpio9";
335 function = "blsp_uart1";
340 i2c_0_pins: i2c_0_pinmux {
342 function = "blsp_i2c0";
343 pins = "gpio20", "gpio21";
346 pins = "gpio20", "gpio21";
347 drive-strength = <16>;
352 i2c_1_pins: i2c_1_pinmux {
354 function = "blsp_i2c1";
355 pins = "gpio34", "gpio35";
358 pins = "gpio34", "gpio35";
359 drive-strength = <16>;
364 nand_pins: nand_pins {
366 * There are 18 pins. 15 pins are common between LCD and NAND.
367 * The QPIC controller arbitrates between LCD and NAND. Of the
368 * remaining 4, 2 are for NAND and 2 are for LCD exclusively.
370 * The meraki source hints that the bluetooth module claims
371 * pin 52 as well. But sadly, there's no data whenever this
372 * is a NAND or LCD exclusive pin or not.
376 pins = "gpio52", "gpio53", "gpio58",
383 pins = "gpio54", "gpio55", "gpio56",
384 "gpio57", "gpio60", "gpio61",
385 "gpio62", "gpio63", "gpio64",
386 "gpio65", "gpio66", "gpio67",
396 /* qcom,ath10k-calibration-variant = "MERAKI-MR33"; */
401 /* qcom,ath10k-calibration-variant = "MERAKI-MR33"; */