2 * Device Tree Source for Meraki MR33 (Stinkbug)
4 * Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com>
5 * Copyright (C) 2017 Christian Lamparter <chunkeey@googlemail.com>
7 * Based on Cisco Meraki DTS from GPL release r25-linux-3.14-20170427
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without
11 * any warranty of any kind, whether express or implied.
14 #include "qcom-ipq4019.dtsi"
15 #include "qcom-ipq4019-bus.dtsi"
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/input/input.h>
18 #include <dt-bindings/soc/qcom,tcsr.h>
21 model = "Meraki MR33 Access Point";
22 compatible = "meraki,mr33", "qcom,ipq4019";
25 led-boot = &status_green;
26 led-failsafe = &status_red;
27 led-running = &status_green;
28 led-upgrade = &power_orange;
31 /* Do we really need this defined? */
33 device_type = "memory";
34 reg = <0x80000000 0x10000000>;
38 #address-cells = <0x1>;
43 reg = <0x87e00000 0x080000>;
48 reg = <0x87e80000 0x180000>;
56 pinctrl-0 = <&mdio_pins>;
57 pinctrl-names = "default";
58 /delete-node/ ethernet-phy@0;
59 /delete-node/ ethernet-phy@2;
60 /delete-node/ ethernet-phy@3;
61 /delete-node/ ethernet-phy@4;
64 /* It is a 56-bit counter that supplies the count to the ARM arch
65 timers and without upstream driver */
67 compatible = "qcom,qca-gcnt";
72 compatible = "qcom,tcsr";
73 reg = <0x1953000 0x1000>;
74 qcom,ess-interface-select = <TCSR_ESS_PSGMII_RGMII5>;
78 compatible = "qcom,tcsr";
79 reg = <0x1949000 0x100>;
80 qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
84 compatible = "qcom,tcsr";
85 reg = <0x1957000 0x100>;
86 qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
90 pinctrl-0 = <&serial_0_pins>;
91 pinctrl-names = "default";
96 pinctrl-0 = <&serial_1_pins>;
97 pinctrl-names = "default";
101 compatible = "ti,cc2650";
102 enable-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
115 switch_mac_mode = <0x3>; /* mac mode for RGMII RMII */
116 switch_lan_bmp = <0x0>; /* lan port bitmap */
117 switch_wan_bmp = <0x10>; /* wan port bitmap */
123 phy-mode = "rgmii-rxid";
129 compatible = "gpio-keys";
133 gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
134 linux,code = <KEY_RESTART>;
139 compatible = "gpio-leds";
141 power_orange: power {
142 label = "mr33:orange:power";
143 gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
158 qcom,phy_mdio_addr = <1>;
159 qcom,poll_required = <1>;
164 pinctrl-0 = <&i2c_0_pins>;
165 pinctrl-names = "default";
168 compatible = "atmel,24c64";
171 read-only; /* This holds our MAC & Meraki board-data */
176 pinctrl-0 = <&i2c_1_pins>;
177 pinctrl-names = "default";
181 enable-gpio = <&tlmm 48 GPIO_ACTIVE_HIGH>;
182 compatible = "ti,lp5562";
183 clock-mode = /bits/8 <2>;
188 chan-name = "mr33:red:status";
189 led-cur = /bits/ 8 <0x20>;
190 max-cur = /bits/ 8 <0x60>;
193 status_green: chan1 {
194 chan-name = "mr33:green:status";
195 led-cur = /bits/ 8 <0x20>;
196 max-cur = /bits/ 8 <0x60>;
200 chan-name = "mr33:blue:status";
201 led-cur = /bits/ 8 <0x20>;
202 max-cur = /bits/ 8 <0x60>;
206 chan-name = "mr33:white:status";
207 led-cur = /bits/ 8 <0x20>;
208 max-cur = /bits/ 8 <0x60>;
214 pinctrl-0 = <&nand_pins>;
215 pinctrl-names = "default";
220 compatible = "fixed-partitions";
221 #address-cells = <1>;
226 reg = <0x000000000000 0x000000100000>;
231 reg = <0x000000100000 0x000000100000>;
235 label = "bootconfig";
236 reg = <0x000000200000 0x000000100000>;
241 reg = <0x000000300000 0x000000100000>;
246 reg = <0x000000400000 0x000000100000>;
251 reg = <0x000000500000 0x000000080000>;
256 reg = <0x000000580000 0x000000080000>;
261 reg = <0x000000600000 0x000000080000>;
266 reg = <0x000000700000 0x000000200000>;
270 label = "u-boot-backup";
271 reg = <0x000000900000 0x000000200000>;
276 reg = <0x000000b00000 0x000000080000>;
281 reg = <0x000000c00000 0x000007000000>;
289 perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
290 wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
299 * GPIO43 should be 0/1 whenever the unit is
300 * powered through PoE or AC-Adapter.
301 * That said, playing with this seems to
305 mdio_pins: mdio_pinmux {
318 serial_0_pins: serial_pinmux {
320 pins = "gpio16", "gpio17";
321 function = "blsp_uart0";
326 serial_1_pins: serial1_pinmux {
328 /* We use the i2c-0 pins for serial_1 */
329 pins = "gpio8", "gpio9";
330 function = "blsp_uart1";
335 i2c_0_pins: i2c_0_pinmux {
337 function = "blsp_i2c0";
338 pins = "gpio20", "gpio21";
341 pins = "gpio20", "gpio21";
342 drive-strength = <16>;
347 i2c_1_pins: i2c_1_pinmux {
349 function = "blsp_i2c1";
350 pins = "gpio34", "gpio35";
353 pins = "gpio34", "gpio35";
354 drive-strength = <16>;
359 nand_pins: nand_pins {
361 * There are 18 pins. 15 pins are common between LCD and NAND.
362 * The QPIC controller arbitrates between LCD and NAND. Of the
363 * remaining 4, 2 are for NAND and 2 are for LCD exclusively.
365 * The meraki source hints that the bluetooth module claims
366 * pin 52 as well. But sadly, there's no data whenever this
367 * is a NAND or LCD exclusive pin or not.
371 pins = "gpio52", "gpio53", "gpio58",
378 pins = "gpio54", "gpio55", "gpio56",
379 "gpio57", "gpio60", "gpio61",
380 "gpio62", "gpio63", "gpio64",
381 "gpio65", "gpio66", "gpio67",
391 /* qcom,ath10k-calibration-variant = "MERAKI-MR33"; */
396 /* qcom,ath10k-calibration-variant = "MERAKI-MR33"; */